Javier A. DeLaCruz

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
3D chip with shared clock distribution network
- Patent number 12,142,528
- Issue date Nov 12, 2024
- Adeia Semiconductor Inc.
- Javier A. DeLaCruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-volatile dynamic random access memory
- Patent number 12,113,054
- Issue date Oct 8, 2024
- ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
- Javier A. Delacruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bonded structures
- Patent number 12,100,684
- Issue date Sep 24, 2024
- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Liang Wang
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Wire bonding method and apparatus for electromagnetic interference...
- Patent number 12,094,835
- Issue date Sep 17, 2024
- ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
- Shaowu Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Direct gang bonding methods including directly bonding first elemen...
- Patent number 12,080,672
- Issue date Sep 3, 2024
- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hard IP blocks with physically bidirectional passageways
- Patent number 12,074,092
- Issue date Aug 27, 2024
- Adeia Semiconductor Inc.
- Javier A. Delacruz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bonded structures with integrated passive component
- Patent number 12,057,383
- Issue date Aug 6, 2024
- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bond enhancement structure in microelectronics for trapping contami...
- Patent number 11,967,575
- Issue date Apr 23, 2024
- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Guilian Gao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Mixed exposure for large die
- Patent number 11,929,347
- Issue date Mar 12, 2024
- ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
- Javier A. Delacruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device disaggregation for improved performance
- Patent number 11,916,076
- Issue date Feb 27, 2024
- Adeia Semiconductor Inc.
- Javier A. Delacruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bonded structures with integrated passive component
- Patent number 11,901,281
- Issue date Feb 13, 2024
- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated voltage regulator and passive components
- Patent number 11,894,345
- Issue date Feb 6, 2024
- Adeia Semiconductor Inc.
- Javier A. Delacruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked IC structure with orthogonal interconnect layers
- Patent number 11,881,454
- Issue date Jan 23, 2024
- Adeia Semiconductor Inc.
- Ilyas Mohammed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus for non-volatile random access memory stacks
- Patent number 11,876,076
- Issue date Jan 16, 2024
- ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
- Javier A. DeLaCruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Scalable architecture for reduced cycles across SOC
- Patent number 11,862,602
- Issue date Jan 2, 2024
- ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
- Javier A. Delacruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Systems and methods for releveled bump planes for chiplets
- Patent number 11,862,604
- Issue date Jan 2, 2024
- Adeia Semiconductor Inc.
- Javier A. Delacruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated optical waveguides, direct-bonded waveguide interface jo...
- Patent number 11,860,415
- Issue date Jan 2, 2024
- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Shaowu Huang
- G02 - OPTICS
Information Patent Grant
Protective elements for bonded structures
- Patent number 11,848,284
- Issue date Dec 19, 2023
- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Javier A DeLaCruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wire bonding method and apparatus for electromagnetic interference...
- Patent number 11,837,556
- Issue date Dec 5, 2023
- ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
- Shaowu Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Over and under interconnects
- Patent number 11,830,804
- Issue date Nov 28, 2023
- Invensas LLC
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D chip sharing data bus
- Patent number 11,824,042
- Issue date Nov 21, 2023
- Xcelsis Corporation
- Javier A. DeLaCruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Symbiotic network on layers
- Patent number 11,824,046
- Issue date Nov 21, 2023
- Invensas LLC
- Javier A. DeLaCruz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Direct-bonded native interconnects and active base die
- Patent number 11,823,906
- Issue date Nov 21, 2023
- Xcelsis Corporation
- Javier A. Delacruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Directly bonded structures without intervening adhesive and methods...
- Patent number 11,817,409
- Issue date Nov 14, 2023
- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Active bridging apparatus
- Patent number 11,804,469
- Issue date Oct 31, 2023
- Invensas LLC
- Javier A. Delacruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer-level bonding of obstructive elements
- Patent number 11,728,287
- Issue date Aug 15, 2023
- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Javier A. DeLaCruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuitry for electrical redundancy in bonded structures
- Patent number 11,721,653
- Issue date Aug 8, 2023
- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Javier A. DeLACruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor level interconnection methodologies utilizing 3D interco...
- Patent number 11,688,776
- Issue date Jun 27, 2023
- Adeia Semiconductor Inc.
- Javier A. Delacruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bonded structures
- Patent number 11,670,615
- Issue date Jun 6, 2023
- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Liang Wang
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Bonded structures with integrated passive component
- Patent number 11,626,363
- Issue date Apr 11, 2023
- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
DIRECT GANG BONDING METHODS AND STRUCTURES
- Publication number 20240387439
- Publication date Nov 21, 2024
- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OVER AND UNDER INTERCONNECTS
- Publication number 20240347443
- Publication date Oct 17, 2024
- ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED VOLTAGE REGULATOR AND PASSIVE COMPONENTS
- Publication number 20240312957
- Publication date Sep 19, 2024
- Adeia Semiconductor Inc.
- Javier A. DeLaCruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Direct-Bonded Native Interconnects And Active Base Die
- Publication number 20240265305
- Publication date Aug 8, 2024
- Adeia Semiconductor Inc.
- Javier A. DeLaCruz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3D CHIP SHARING DATA BUS
- Publication number 20240266325
- Publication date Aug 8, 2024
- Adeia Semiconductor Inc.
- Javier A. DeLaCruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ACTIVE BRIDGING APPARATUS
- Publication number 20240258271
- Publication date Aug 1, 2024
- ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
- Javier A. Delacruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Symbiotic Network On Layers
- Publication number 20240250071
- Publication date Jul 25, 2024
- ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
- Javier A. DeLaCruz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Device Disaggregation For Improved Performance
- Publication number 20240234424
- Publication date Jul 11, 2024
- Adeia Semiconductor Inc.
- Javier A. DeLaCruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED IC STRUCTURE WITH ORTHOGONAL INTERCONNECT LAYERS
- Publication number 20240234320
- Publication date Jul 11, 2024
- Adeia Semiconductor Inc.
- Ilyas Mohammed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WIRE BONDING METHOD AND APPARATUS FOR ELECTROMAGNETIC INTERFERENCE...
- Publication number 20240162162
- Publication date May 16, 2024
- ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
- Shaowu Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CIRCUITRY FOR ELECTRICAL REDUNDANCY IN BONDED STRUCTURES
- Publication number 20240162178
- Publication date May 16, 2024
- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Javier A. DeLaCruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEMS AND METHODS FOR RELEVELED BUMP PLANES FOR CHIPLETS
- Publication number 20240162190
- Publication date May 16, 2024
- Adeia Semiconductor Inc.
- Javier A. DeLaCruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUS FOR NON-VOLATILE RANDOM ACCESS MEMORY STACKS
- Publication number 20240145438
- Publication date May 2, 2024
- ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
- Javier A. DeLaCruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BONDED STRUCTURES WITH INTEGRATED PASSIVE COMPONENT
- Publication number 20240128186
- Publication date Apr 18, 2024
- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED OPTICAL WAVEGUIDES, DIRECT-BONDED WAVEGUIDE INTERFACE JO...
- Publication number 20240118492
- Publication date Apr 11, 2024
- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Shaowu HUANG
- G02 - OPTICS
Information Patent Application
PROTECTIVE ELEMENTS FOR BONDED STRUCTURES
- Publication number 20240096823
- Publication date Mar 21, 2024
- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Javier A. DeLaCruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER-LEVEL BONDING OF OBSTRUCTIVE ELEMENTS
- Publication number 20240079351
- Publication date Mar 7, 2024
- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Javier A. DeLaCruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BONDED STRUCTURES WITHOUT INTERVENING ADHESIVE
- Publication number 20230420399
- Publication date Dec 28, 2023
- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CIRCUITRY FOR ELECTRICAL REDUNDANCY IN BONDED STRUCTURES
- Publication number 20230395544
- Publication date Dec 7, 2023
- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Javier A. DeLaCruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D MEMORY CIRCUIT
- Publication number 20230376234
- Publication date Nov 23, 2023
- Invensas LLC
- Javier A. DeLaCruz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE ARCHITECTURE FOR REDUCED CYCLES ACROSS SOC
- Publication number 20230369286
- Publication date Nov 16, 2023
- ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
- Javier A. DeLaCruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BONDED STRUCTURES
- Publication number 20230361072
- Publication date Nov 9, 2023
- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Liang Wang
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
PROTECTIVE ELEMENTS FOR BONDED STRUCTURES
- Publication number 20230317628
- Publication date Oct 5, 2023
- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BONDED STRUCTURES WITH INTEGRATED PASSIVE COMPONENT
- Publication number 20230317591
- Publication date Oct 5, 2023
- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CAVITY PACKAGES
- Publication number 20230260858
- Publication date Aug 17, 2023
- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Shaowu Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BOND ENHANCEMENT FOR DIRECT-BONDING PROCESSES
- Publication number 20230187398
- Publication date Jun 15, 2023
- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Guilian GAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR LEVEL INTERCONNECTION METHODOLOGIES UTILIZING 3D INTERCO...
- Publication number 20230138732
- Publication date May 4, 2023
- Adeia Semiconductor Inc.
- Javier A. DeLaCruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D CHIP WITH SHARED CLOCK DISTRIBUTION NETWORK
- Publication number 20230137580
- Publication date May 4, 2023
- Adeia Semiconductor Inc.
- Javier A. DeLaCruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED VOLTAGE REGULATOR AND PASSIVE COMPONENTS
- Publication number 20230090121
- Publication date Mar 23, 2023
- Adeia Semiconductor Inc.
- Javier A. DeLaCruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED ARCHITECTURE FOR THREE-DIMENSIONAL NAND
- Publication number 20230050150
- Publication date Feb 16, 2023
- Xcelsis Corporation
- Stephen Morein
- H01 - BASIC ELECTRIC ELEMENTS

Javier A. DeLaCruz

Person

Patents Grantslast 30 patents

3D chip with shared clock distribution network

Non-volatile dynamic random access memory

Bonded structures

Wire bonding method and apparatus for electromagnetic interference...

Direct gang bonding methods including directly bonding first elemen...

Hard IP blocks with physically bidirectional passageways

Bonded structures with integrated passive component

Bond enhancement structure in microelectronics for trapping contami...

Mixed exposure for large die

Device disaggregation for improved performance

Bonded structures with integrated passive component

Integrated voltage regulator and passive components

Stacked IC structure with orthogonal interconnect layers

Apparatus for non-volatile random access memory stacks

Scalable architecture for reduced cycles across SOC

Systems and methods for releveled bump planes for chiplets

Integrated optical waveguides, direct-bonded waveguide interface jo...

Protective elements for bonded structures

Wire bonding method and apparatus for electromagnetic interference...

Over and under interconnects

3D chip sharing data bus

Symbiotic network on layers

Direct-bonded native interconnects and active base die

Directly bonded structures without intervening adhesive and methods...

Active bridging apparatus

Wafer-level bonding of obstructive elements

Circuitry for electrical redundancy in bonded structures

Transistor level interconnection methodologies utilizing 3D interco...

Bonded structures

Bonded structures with integrated passive component

Patents Applicationslast 30 patents

DIRECT GANG BONDING METHODS AND STRUCTURES

OVER AND UNDER INTERCONNECTS

INTEGRATED VOLTAGE REGULATOR AND PASSIVE COMPONENTS

Direct-Bonded Native Interconnects And Active Base Die

3D CHIP SHARING DATA BUS

ACTIVE BRIDGING APPARATUS

Symbiotic Network On Layers

Device Disaggregation For Improved Performance

STACKED IC STRUCTURE WITH ORTHOGONAL INTERCONNECT LAYERS

WIRE BONDING METHOD AND APPARATUS FOR ELECTROMAGNETIC INTERFERENCE...

CIRCUITRY FOR ELECTRICAL REDUNDANCY IN BONDED STRUCTURES

SYSTEMS AND METHODS FOR RELEVELED BUMP PLANES FOR CHIPLETS

APPARATUS FOR NON-VOLATILE RANDOM ACCESS MEMORY STACKS

BONDED STRUCTURES WITH INTEGRATED PASSIVE COMPONENT

INTEGRATED OPTICAL WAVEGUIDES, DIRECT-BONDED WAVEGUIDE INTERFACE JO...

PROTECTIVE ELEMENTS FOR BONDED STRUCTURES

WAFER-LEVEL BONDING OF OBSTRUCTIVE ELEMENTS

BONDED STRUCTURES WITHOUT INTERVENING ADHESIVE

CIRCUITRY FOR ELECTRICAL REDUNDANCY IN BONDED STRUCTURES

3D MEMORY CIRCUIT

SCALABLE ARCHITECTURE FOR REDUCED CYCLES ACROSS SOC

BONDED STRUCTURES

PROTECTIVE ELEMENTS FOR BONDED STRUCTURES

BONDED STRUCTURES WITH INTEGRATED PASSIVE COMPONENT

CAVITY PACKAGES

BOND ENHANCEMENT FOR DIRECT-BONDING PROCESSES

TRANSISTOR LEVEL INTERCONNECTION METHODOLOGIES UTILIZING 3D INTERCO...

3D CHIP WITH SHARED CLOCK DISTRIBUTION NETWORK

INTEGRATED VOLTAGE REGULATOR AND PASSIVE COMPONENTS

STACKED ARCHITECTURE FOR THREE-DIMENSIONAL NAND