Leland Szewerenko

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
System and method for reduced latency data transfers from flash mem...
- Patent number 8,341,311
- Issue date Dec 25, 2012
- Entorian Technologies, Inc
- Leland Szewerenko
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit module having force resistant construction
- Patent number 7,804,985
- Issue date Sep 28, 2010
- Entorian Technologies LP
- Leland Szewerenko
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density IC module
- Patent number 7,759,791
- Issue date Jul 20, 2010
- Entorian Technologies LP
- Julian Partridge
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit module turbulence enhancement systems and methods
- Patent number 7,579,687
- Issue date Aug 25, 2009
- Entorian Technologies, LP
- Leland Szewerenko
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Contrast interposer stacking system and method
- Patent number 7,573,129
- Issue date Aug 11, 2009
- Entorian Technologies, LP
- Julian Partridge
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Managed memory component
- Patent number 7,508,069
- Issue date Mar 24, 2009
- Entorian Technologies, LP
- James Douglas Wehrly, Jr.
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Stackable micropackages and stacked modules
- Patent number 7,468,553
- Issue date Dec 23, 2008
- Entorian Technologies, LP
- Leland Szewerenko
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit module having force resistant construction
- Patent number 7,417,310
- Issue date Aug 26, 2008
- Entorian Technologies, LP
- Leland Szewerenko
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Real-time data exchange on demand
- Patent number 7,343,591
- Issue date Mar 11, 2008
- Texas Instruments Incorporated
- Leland J. Szewerenko
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managed memory component
- Patent number 7,304,382
- Issue date Dec 4, 2007
- Staktek Group L.P.
- James Douglas Wehrly, Jr.
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Multiprocessor emulation support using dynamic linking
- Patent number 6,931,636
- Issue date Aug 16, 2005
- Texas Instruments Incorporated
- Douglas Deao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for far branch and call instructions
- Patent number 6,928,641
- Issue date Aug 9, 2005
- Texas Instruments Incorporated
- Leland Szewerenko
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for visual linker
- Patent number 6,883,167
- Issue date Apr 19, 2005
- Texas Instruments Incorporated
- Leland Szewerenko
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for automatically configuring a debug system
- Patent number 6,785,850
- Issue date Aug 31, 2004
- Texas Instruments Incorporated
- Jonathan Dzoba
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data exchange system and method for processors
- Patent number 6,775,793
- Issue date Aug 10, 2004
- Texas Instruments Incorporated
- Douglas Deao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Debugger with real-time data exchange
- Patent number 6,543,048
- Issue date Apr 1, 2003
- Texas Instruments Incorporated
- Edward Kuzemchak
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
BUILDING EQUIPMENT ACCESS MANAGEMENT SYSTEM WITH DYNAMIC ACCESS COD...
- Publication number 20250005980
- Publication date Jan 2, 2025
- TYCO FIRE & SECURITY GMBH
- Ian M. Casper
- G07 - CHECKING-DEVICES
Information Patent Application
Circuit Module Turbulence Enhancement
- Publication number 20090309214
- Publication date Dec 17, 2009
- Entorian Technologies, LP
- Leland Szewerenko
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Package-Borne Selective Enablement Stacking
- Publication number 20090294946
- Publication date Dec 3, 2009
- Leland Szewerenko
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Contrast Interposer Stacking System And Method
- Publication number 20090294948
- Publication date Dec 3, 2009
- Julian Partridge
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Managed Memory Component
- Publication number 20090160042
- Publication date Jun 25, 2009
- Entorian Technologies, LP
- James Douglas Wehrly, JR.
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
Circuit Module Having Force Resistant Construction
- Publication number 20080308924
- Publication date Dec 18, 2008
- Entorian Technologies, LP
- Leland Szewerenko
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Package-Borne Selective Enablement Stacking
- Publication number 20080246134
- Publication date Oct 9, 2008
- Staktek Group L.P.
- Leland Szewerenko
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Managed Memory System
- Publication number 20080222365
- Publication date Sep 11, 2008
- Staktek Group L.P.
- Leland Szewerenko
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuit Module Having Force Resistant Construction
- Publication number 20080122054
- Publication date May 29, 2008
- Leland Szewerenko
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
High Density IC Module
- Publication number 20080093734
- Publication date Apr 24, 2008
- Staktek Group L.P.
- Julian Partridge
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Stackable Micropackages and Stacked Modules
- Publication number 20080093724
- Publication date Apr 24, 2008
- Staktek Group L.P.
- Leland Szewerenko
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Vapor heat spreader
- Publication number 20080062652
- Publication date Mar 13, 2008
- Wayne Lieberman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Contrast Interposer Stacking System And Method
- Publication number 20070290314
- Publication date Dec 20, 2007
- Julian Partridge
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Managed memory component
- Publication number 20070164416
- Publication date Jul 19, 2007
- James Douglas Wehrly
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
Managed memory component
- Publication number 20070159545
- Publication date Jul 12, 2007
- James Douglas Wehrly
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Managed memory component
- Publication number 20070158821
- Publication date Jul 12, 2007
- Leland Szewerenko
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Managed memory component
- Publication number 20070158800
- Publication date Jul 12, 2007
- James Douglas Wehrly
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Low profile managed memory component
- Publication number 20070158811
- Publication date Jul 12, 2007
- James Douglas Wehrly
- G11 - INFORMATION STORAGE
Information Patent Application
Circuit module turbulence enhacement systems and methods
- Publication number 20060129888
- Publication date Jun 15, 2006
- Staktek Group. L.P.
- Leland Szewerenko
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Real-time data exchange on demand
- Publication number 20040024924
- Publication date Feb 5, 2004
- Leland J. Szewerenko
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiprocessor emulation support using dynamic linking
- Publication number 20020026304
- Publication date Feb 28, 2002
- Douglas Deao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Data exchange system and method for processors
- Publication number 20010056555
- Publication date Dec 27, 2001
- Douglas Deao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for linking multiple processors having shared memory
- Publication number 20010047512
- Publication date Nov 29, 2001
- Leland Szewerenko
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for automatically configuring a debug system
- Publication number 20010042226
- Publication date Nov 15, 2001
- Jonathan Dzoba
- G06 - COMPUTING CALCULATING COUNTING

Leland Szewerenko

Person

Patents Grantslast 30 patents

System and method for reduced latency data transfers from flash mem...

Circuit module having force resistant construction

High density IC module

Circuit module turbulence enhancement systems and methods

Contrast interposer stacking system and method

Managed memory component

Stackable micropackages and stacked modules

Circuit module having force resistant construction

Real-time data exchange on demand

Managed memory component

Multiprocessor emulation support using dynamic linking

Method and system for far branch and call instructions

Method and system for visual linker

System and method for automatically configuring a debug system

Data exchange system and method for processors

Debugger with real-time data exchange

Patents Applicationslast 30 patents

BUILDING EQUIPMENT ACCESS MANAGEMENT SYSTEM WITH DYNAMIC ACCESS COD...

Circuit Module Turbulence Enhancement

Package-Borne Selective Enablement Stacking

Contrast Interposer Stacking System And Method

Managed Memory Component

Circuit Module Having Force Resistant Construction

Package-Borne Selective Enablement Stacking

Managed Memory System

Circuit Module Having Force Resistant Construction

High Density IC Module

Stackable Micropackages and Stacked Modules

Vapor heat spreader

Contrast Interposer Stacking System And Method

Managed memory component

Managed memory component

Managed memory component

Managed memory component

Low profile managed memory component

Circuit module turbulence enhacement systems and methods

Real-time data exchange on demand

Multiprocessor emulation support using dynamic linking

Data exchange system and method for processors

Method and system for linking multiple processors having shared memory

System and method for automatically configuring a debug system