Martin Kerber

Person

Muenchen, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Signal transmission arrangement
- Patent number 9,431,379
- Issue date Aug 30, 2016
- Infineon Technologies Austria AG
- Martin Kerber
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Signal transmission arrangement
- Patent number 8,970,000
- Issue date Mar 3, 2015
- Infineon Technologies Austria AG
- Martin Kerber
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Detection of pre-catastrophic, stress induced leakage current condi...
- Patent number 8,823,385
- Issue date Sep 2, 2014
- Infineon Technologies AG
- Martin Kerber
- G01 - MEASURING TESTING
Information Patent Grant
Semiconductor structure including guard ring
- Patent number 8,716,832
- Issue date May 6, 2014
- Infineon Technologies AG
- Martin Kerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High voltage semiconductor devices and methods of forming the same
- Patent number 8,410,575
- Issue date Apr 2, 2013
- Infineon Technologies Austria AG
- Martin Kerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for reducing charge trapping in high-k dielect...
- Patent number 7,894,240
- Issue date Feb 22, 2011
- Qimonda AG
- Michael Beck
- G11 - INFORMATION STORAGE
Information Patent Grant
System that detects damage in adjacent dice
- Patent number 7,782,074
- Issue date Aug 24, 2010
- Infineon Technologies AG
- Martin Kerber
- G01 - MEASURING TESTING
Information Patent Grant
Procedure for arranging chips of a first substrate on a second subs...
- Patent number 7,772,039
- Issue date Aug 10, 2010
- Infineon Technologies AG
- Martin Kerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for the elimination of the effects of defects on wafers
- Patent number 7,704,853
- Issue date Apr 27, 2010
- Infineon Technologies AG
- Martin Kerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test arrangement having chips of a first substrate on a second subs...
- Patent number 7,652,493
- Issue date Jan 26, 2010
- Infineon Technologies AG
- Martin Kerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor wafer having a dielectric reliability test structure,...
- Patent number 7,550,986
- Issue date Jun 23, 2009
- Infineon Technologies AG
- Martin Kerber
- G01 - MEASURING TESTING
Information Patent Grant
Electronic switching circuit, switching circuit test arrangement an...
- Patent number 7,403,026
- Issue date Jul 22, 2008
- Infineon Technologies AG
- Martin Kerber
- G01 - MEASURING TESTING
Information Patent Grant
Method of producing a semiconductor surface covered with fluorine
- Patent number 6,566,271
- Issue date May 20, 2003
- Infineon Technologies AG
- Alexander Gschwandtner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lateral bipolar transistor
- Patent number 6,433,387
- Issue date Aug 13, 2002
- Siemens Aktiengesellschaft
- Martin Kerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS circuit with all-around dielectrically insulated source-drain...
- Patent number 6,404,034
- Issue date Jun 11, 2002
- Infineon Technologies AG
- Dietrich Widmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure for a MOS transistor
- Patent number 6,239,478
- Issue date May 29, 2001
- Infineon Technologies AG
- Martin Kerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density integrated semiconductor memory and method for produci...
- Patent number 6,157,060
- Issue date Dec 5, 2000
- Siemens Aktiengesellschaft
- Martin Kerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for manufacturing a CMOS circuit with all-around dielectric...
- Patent number 6,124,156
- Issue date Sep 26, 2000
- Infineon Technologies AG
- Dietrich Widmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of producing the source regions of a flash EEPROM memory cel...
- Patent number 6,090,665
- Issue date Jul 18, 2000
- Siemens Aktiengesellschaft
- Martin Kerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for producing very small structural widths on a semiconducto...
- Patent number 6,027,972
- Issue date Feb 22, 2000
- Siemens Aktiengesellschaft
- Martin Kerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cell and method for producing the memory cell
- Patent number 5,976,932
- Issue date Nov 2, 1999
- Siemens Aktiengesellschaft
- Martin Kerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor configuration for an insulating transistor
- Patent number 5,962,901
- Issue date Oct 5, 1999
- Siemens Aktiengesellschaft
- Martin Kerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS Semiconductor structure and process for producing the same
- Patent number 5,925,919
- Issue date Jul 20, 1999
- Siemens Aktiengesellschaft
- Martin Kerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for producing sublithographic etching masks
- Patent number 5,916,821
- Issue date Jun 29, 1999
- Siemens Aktiengesellschaft
- Martin Kerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for manufacturing an integrated CMOS circuit
- Patent number 5,882,965
- Issue date Mar 16, 1999
- Siemens Aktiengesellschaft
- Udo Schwalke
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing semiconductor components
- Patent number 5,882,963
- Issue date Mar 16, 1999
- Siemens Aktiengesellschaft
- Martin Kerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SOI-BiCMOS method
- Patent number 5,846,858
- Issue date Dec 8, 1998
- Siemens Aktiengesellschaft
- Martin Kerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated switching circuit with CMOS circuit and method for produ...
- Patent number 5,847,433
- Issue date Dec 8, 1998
- Siemens Aktiengesellschaft
- Martin Kerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure for an MOS transistor and method for fabric...
- Patent number 5,817,570
- Issue date Oct 6, 1998
- Siemens Aktiengesellschaft
- Martin Kerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
MOS transistor for biotechnical applications
- Patent number 5,801,428
- Issue date Sep 1, 1998
- Siemens Aktiengesellschaft
- Andreas Vom Felde
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Signal Transmission Arrangement
- Publication number 20150132890
- Publication date May 14, 2015
- Infineon Technologies Austria AG
- Martin Kerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor structure including guard ring
- Publication number 20130075859
- Publication date Mar 28, 2013
- Martin Kerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Detection of Pre-Catastrophic, Stress Induced Leakage Current Condi...
- Publication number 20120229145
- Publication date Sep 13, 2012
- INFINEON TECHNOLOGIES AG
- Martin Kerber
- G01 - MEASURING TESTING
Information Patent Application
High Voltage Semiconductor Devices and Methods of Forming the Same
- Publication number 20110241160
- Publication date Oct 6, 2011
- Martin Kerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Signal Transmission Arrangement
- Publication number 20110176339
- Publication date Jul 21, 2011
- Martin Kerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and Apparatus for Reducing Charge Trapping in High-K Dielect...
- Publication number 20100054022
- Publication date Mar 4, 2010
- QIMONDA AG
- Michael Beck
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM THAT DETECTS DAMAGE IN ADJACENT DICE
- Publication number 20090072852
- Publication date Mar 19, 2009
- Martin Kerber
- G01 - MEASURING TESTING
Information Patent Application
Method for arranging chips of a first substrate on a second substrate
- Publication number 20080217615
- Publication date Sep 11, 2008
- Infineon Technologies AG
- Martin Kerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS FOR REDUCING PLASMA-INDUCED DAMAGE IN A SEMICO...
- Publication number 20080066866
- Publication date Mar 20, 2008
- Martin Kerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit device with current measurement
- Publication number 20080042681
- Publication date Feb 21, 2008
- INFINEON TECHNOLOGIES AG
- Martin Kerber
- G01 - MEASURING TESTING
Information Patent Application
Semiconductor wafer having a dielectric reliability test structure,...
- Publication number 20070252611
- Publication date Nov 1, 2007
- Infineon Technologies AG
- Martin Kerber
- G01 - MEASURING TESTING
Information Patent Application
Electronic switching circuit, switching circuit test arrangement an...
- Publication number 20060282725
- Publication date Dec 14, 2006
- Martin Kerber
- G01 - MEASURING TESTING
Information Patent Application
Method for the elimination of the effects of defects on wafers
- Publication number 20060240638
- Publication date Oct 26, 2006
- Martin Kerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Procedure for arranging chips of a first substrate on a second subs...
- Publication number 20060014308
- Publication date Jan 19, 2006
- Martin Kerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for forming a dielectric on a semiconductor substrate
- Publication number 20010046787
- Publication date Nov 29, 2001
- Martin Kerber
- H01 - BASIC ELECTRIC ELEMENTS

Martin Kerber

Person

Patents Grantslast 30 patents

Signal transmission arrangement

Signal transmission arrangement

Detection of pre-catastrophic, stress induced leakage current condi...

Semiconductor structure including guard ring

High voltage semiconductor devices and methods of forming the same

Method and apparatus for reducing charge trapping in high-k dielect...

System that detects damage in adjacent dice

Procedure for arranging chips of a first substrate on a second subs...

Method for the elimination of the effects of defects on wafers

Test arrangement having chips of a first substrate on a second subs...

Semiconductor wafer having a dielectric reliability test structure,...

Electronic switching circuit, switching circuit test arrangement an...

Method of producing a semiconductor surface covered with fluorine

Lateral bipolar transistor

CMOS circuit with all-around dielectrically insulated source-drain...

Semiconductor structure for a MOS transistor

High density integrated semiconductor memory and method for produci...

Process for manufacturing a CMOS circuit with all-around dielectric...

Method of producing the source regions of a flash EEPROM memory cel...

Method for producing very small structural widths on a semiconducto...

Memory cell and method for producing the memory cell

Semiconductor configuration for an insulating transistor

CMOS Semiconductor structure and process for producing the same

Method for producing sublithographic etching masks

Process for manufacturing an integrated CMOS circuit

Method of manufacturing semiconductor components

SOI-BiCMOS method

Integrated switching circuit with CMOS circuit and method for produ...

Semiconductor structure for an MOS transistor and method for fabric...

MOS transistor for biotechnical applications

Patents Applicationslast 30 patents

Signal Transmission Arrangement

Semiconductor structure including guard ring

Detection of Pre-Catastrophic, Stress Induced Leakage Current Condi...

High Voltage Semiconductor Devices and Methods of Forming the Same

Signal Transmission Arrangement

Method and Apparatus for Reducing Charge Trapping in High-K Dielect...

SYSTEM THAT DETECTS DAMAGE IN ADJACENT DICE

Method for arranging chips of a first substrate on a second substrate

METHOD AND APPARATUS FOR REDUCING PLASMA-INDUCED DAMAGE IN A SEMICO...

Integrated circuit device with current measurement

Semiconductor wafer having a dielectric reliability test structure,...

Electronic switching circuit, switching circuit test arrangement an...

Method for the elimination of the effects of defects on wafers

Procedure for arranging chips of a first substrate on a second subs...

Method for forming a dielectric on a semiconductor substrate