N. Johan Knall

Person

Palo Alto, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Silicon nitride antifuse for use in diode-antifuse memory arrays
- Patent number 8,575,719
- Issue date Nov 5, 2013
- Sandisk 3D LLC
- Mark G. Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Process for fabricating a dielectric film using plasma oxidation
- Patent number 7,816,188
- Issue date Oct 19, 2010
- Sandisk 3D LLC
- Michael A. Vyvoda
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Electrically isolated pillars in active devices
- Patent number 7,413,945
- Issue date Aug 19, 2008
- Sandisk 3D LLC
- Michael A. Vyvoda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reverse-bias method for writing memory cells in a memory array
- Patent number 7,304,888
- Issue date Dec 4, 2007
- Sandisk 3D LLC
- N. Johan Knall
- G11 - INFORMATION STORAGE
Information Patent Grant
Electrically isolated pillars in active devices
- Patent number 7,245,000
- Issue date Jul 17, 2007
- SanDisk Corporation
- Michael A. Vyvoda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional memory array and method of fabrication
- Patent number 7,091,529
- Issue date Aug 15, 2006
- Sandisk 3D LLC
- N. Johan Knall
- G11 - INFORMATION STORAGE
Information Patent Grant
Patterning three dimensional structures
- Patent number 7,071,565
- Issue date Jul 4, 2006
- Sandisk 3D LLC
- Calvin K. Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Manufacturing method for integrated circuit having disturb-free pro...
- Patent number 7,022,572
- Issue date Apr 4, 2006
- Matrix Semiconductor, Inc.
- Roy E. Scheuerlein
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for disturb-free programming of passive elemen...
- Patent number 6,963,504
- Issue date Nov 8, 2005
- Matrix Semiconductor, Inc.
- Roy E. Scheuerlein
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit and method for selecting a set of memory-cell-la...
- Patent number 6,954,394
- Issue date Oct 11, 2005
- Matrix Semiconductor, Inc.
- N. Johan Knall
- G11 - INFORMATION STORAGE
Information Patent Grant
Electrically isolated pillars in active devices
- Patent number 6,952,043
- Issue date Oct 4, 2005
- Matrix Semiconductor, Inc.
- Michael A. Vyvoda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nonvolatile memory on SOI and compound semiconductor substrates and...
- Patent number 6,888,750
- Issue date May 3, 2005
- Matrix Semiconductor, Inc.
- Andrew J. Walker
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for disturb-free programming of passive elemen...
- Patent number 6,822,903
- Issue date Nov 23, 2004
- Matrix Semiconductor, Inc.
- Roy E. Scheuerlein
- G11 - INFORMATION STORAGE
Information Patent Grant
Three-dimensional memory array incorporating serial chain diode stack
- Patent number 6,784,517
- Issue date Aug 31, 2004
- Matrix Semiconductor, Inc.
- Bendik Kleveland
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell with antifuse layer formed at diode junction
- Patent number 6,777,773
- Issue date Aug 17, 2004
- Matrix Semiconductor, Inc.
- N. Johan Knall
- G11 - INFORMATION STORAGE
Information Patent Grant
Thermal processing for three dimensional circuits
- Patent number 6,770,939
- Issue date Aug 3, 2004
- Matrix Semiconductor, Inc.
- Vivek Subramanian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of antifuse structure in a three dimensional memory
- Patent number 6,768,185
- Issue date Jul 27, 2004
- Matrix Semiconductor, Inc.
- James M. Cleeves
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making a three-dimensional memory array incorporating se...
- Patent number 6,767,816
- Issue date Jul 27, 2004
- Matrix Semiconductor, Inc.
- Bendik Kleveland
- G11 - INFORMATION STORAGE
Information Patent Grant
Anti-fuse memory cell with asymmetric breakdown voltage
- Patent number 6,704,235
- Issue date Mar 9, 2004
- Matrix Semiconductor, Inc.
- N. Johan Knall
- G11 - INFORMATION STORAGE
Information Patent Grant
Three-dimensional memory array and method of fabrication
- Patent number 6,653,712
- Issue date Nov 25, 2003
- Matrix Semiconductor, Inc.
- N. Johan Knall
- G11 - INFORMATION STORAGE
Information Patent Grant
Same conductivity type highly-doped regions for antifuse memory cell
- Patent number 6,642,603
- Issue date Nov 4, 2003
- Matrix Semiconductor, Inc.
- N. Johan Knall
- G11 - INFORMATION STORAGE
Information Patent Grant
Three-dimensional memory array incorporating serial chain diode stack
- Patent number 6,631,085
- Issue date Oct 7, 2003
- Matrix Semiconductor, Inc.
- Bendik Kleveland
- G11 - INFORMATION STORAGE
Information Patent Grant
Patterning three dimensional structures
- Patent number 6,627,530
- Issue date Sep 30, 2003
- Matrix Semiconductor, Inc.
- Calvin K. Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thermal processing for three dimensional circuits
- Patent number 6,624,011
- Issue date Sep 23, 2003
- Matrix Semiconductor, Inc.
- Vivek Subramanian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of antifuse structure in a three dimensional memory
- Patent number 6,541,312
- Issue date Apr 1, 2003
- Matrix Semiconductor, Inc.
- James M. Cleeves
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low cost three-dimensional memory array
- Patent number 6,515,888
- Issue date Feb 4, 2003
- Matrix Semiconductor, Inc.
- Mark G. Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Digital memory method and system for storing multiple bit digital data
- Patent number 6,490,218
- Issue date Dec 3, 2002
- Matrix Semiconductor, Inc.
- Michael A. Vyvoda
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of forming nonvolatile memory device utilizing a hard mask
- Patent number 6,486,065
- Issue date Nov 26, 2002
- Matrix Semiconductor, Inc.
- Michael A. Vyvoda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional memory array and method of fabrication
- Patent number 6,420,215
- Issue date Jul 16, 2002
- Matrix Semiconductor, Inc.
- N. Johan Knall
- G11 - INFORMATION STORAGE
Information Patent Grant
Fabrication of gated electron-emitting devices utilizing distribute...
- Patent number 6,187,603
- Issue date Feb 13, 2001
- Candescent Technologies Corporation
- Duane A. Haven
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Reverse-bias method for writing memory cells in a memory array
- Publication number 20070002610
- Publication date Jan 4, 2007
- Matrix Semiconductor,Inc.
- N. Johan Knall
- G11 - INFORMATION STORAGE
Information Patent Application
Manufacturing method for integrated circuit having disturb-free pro...
- Publication number 20050101088
- Publication date May 12, 2005
- Roy E. Scheuerlein
- G11 - INFORMATION STORAGE
Information Patent Application
Apparatus and method for disturb-free programming of passive elemen...
- Publication number 20050073898
- Publication date Apr 7, 2005
- Roy E. Scheuerlein
- G11 - INFORMATION STORAGE
Information Patent Application
Apparatus and method for disturb-free programming of passive elemen...
- Publication number 20040190359
- Publication date Sep 30, 2004
- Roy E. Scheuerlein
- G11 - INFORMATION STORAGE
Information Patent Application
Three-dimensional memory array and method of fabrication
- Publication number 20040188798
- Publication date Sep 30, 2004
- N. Johan Knall
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated circuit and method for selecting a set of memory-cell-la...
- Publication number 20040100831
- Publication date May 27, 2004
- N. Johan Knall
- G11 - INFORMATION STORAGE
Information Patent Application
Three-dimensional memory array and method of fabrication
- Publication number 20040089917
- Publication date May 13, 2004
- N. Johan Knall
- G11 - INFORMATION STORAGE
Information Patent Application
Electrically isolated pillars in active devices
- Publication number 20040087072
- Publication date May 6, 2004
- Michael A. Vyvoda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Electrically isolated pillars in active devices
- Publication number 20040071034
- Publication date Apr 15, 2004
- Michael A. Vyvoda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Silicon nitride antifuse for use in diode-antifuse memory arrays
- Publication number 20040016991
- Publication date Jan 29, 2004
- MATRIX SEMICONDUCTOR, INC.
- Mark G. Johnson
- G11 - INFORMATION STORAGE
Information Patent Application
ELECTRICALLY ISOLATED PILLARS IN ACTIVE DEVICES
- Publication number 20040002186
- Publication date Jan 1, 2004
- Michael A. Vyvoda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Three-dimensional memory array incorporating serial chain diode stack
- Publication number 20030053332
- Publication date Mar 20, 2003
- Bendik Kleveland
- B82 - NANO-TECHNOLOGY
Information Patent Application
Method for making a three-dimensional memory array incorporating se...
- Publication number 20030031067
- Publication date Feb 13, 2003
- Bendik Kleveland
- B82 - NANO-TECHNOLOGY
Information Patent Application
Anti-fuse memory cell with asymmetric breakdown voltage
- Publication number 20030026158
- Publication date Feb 6, 2003
- MATRIX SEMICONDUCTOR, INC.
- N. Johan Knall
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Thermal processing for three dimensional circuits
- Publication number 20030025176
- Publication date Feb 6, 2003
- Vivek Subramanian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Anti-fuse memory cell with asymmetric breakdown voltage
- Publication number 20030026157
- Publication date Feb 6, 2003
- N. Johan Knall
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Patterning three dimensional structures
- Publication number 20030025210
- Publication date Feb 6, 2003
- Calvin K. Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process for fabricating a dielectric film using plasma oxidation
- Publication number 20030022526
- Publication date Jan 30, 2003
- Michael A. Vyvoda
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Three-dimensional memory array incorporating serial chain diode stack
- Publication number 20030022420
- Publication date Jan 30, 2003
- Bendik Kleveland
- B82 - NANO-TECHNOLOGY
Information Patent Application
Memory cell with antifuse layer formed at diode junction
- Publication number 20030021142
- Publication date Jan 30, 2003
- N. Johan Knall
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Formation of antifuse structure in a three dimensional memory
- Publication number 20030003632
- Publication date Jan 2, 2003
- James M. Cleeves
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Three-dimensional memory array and method of fabrication
- Publication number 20020140051
- Publication date Oct 3, 2002
- N. Johan Knall
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Formation of antifuse structure in a three dimensional memory
- Publication number 20020106838
- Publication date Aug 8, 2002
- James M. Cleeves
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL MEMORY ARRAY AND METHOD OF FABRICATION
- Publication number 20020088998
- Publication date Jul 11, 2002
- N. Johan Knall
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Patterning three dimensional structures
- Publication number 20020081833
- Publication date Jun 27, 2002
- Calvin K. Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING NONVOLATILE MEMORY DEVICE UTILIZING A HARD MASK
- Publication number 20020081851
- Publication date Jun 27, 2002
- Michael A. Vyvoda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Low-cost three-dimensional memory array
- Publication number 20020075719
- Publication date Jun 20, 2002
- Mark G. Johnson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Arithmetic unit
- Publication number 20020038202
- Publication date Mar 28, 2002
- Sebastien Ferroussat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Nonvolatile memory on SOI and compound semiconductor substrates and...
- Publication number 20010055838
- Publication date Dec 27, 2001
- Matrix Semiconductor Inc.
- Andrew J. Walker
- H01 - BASIC ELECTRIC ELEMENTS

N. Johan Knall

Person

Patents Grantslast 30 patents

Silicon nitride antifuse for use in diode-antifuse memory arrays

Process for fabricating a dielectric film using plasma oxidation

Electrically isolated pillars in active devices

Reverse-bias method for writing memory cells in a memory array

Electrically isolated pillars in active devices

Three-dimensional memory array and method of fabrication

Patterning three dimensional structures

Manufacturing method for integrated circuit having disturb-free pro...

Apparatus and method for disturb-free programming of passive elemen...

Integrated circuit and method for selecting a set of memory-cell-la...

Electrically isolated pillars in active devices

Nonvolatile memory on SOI and compound semiconductor substrates and...

Apparatus and method for disturb-free programming of passive elemen...

Three-dimensional memory array incorporating serial chain diode stack

Memory cell with antifuse layer formed at diode junction

Thermal processing for three dimensional circuits

Formation of antifuse structure in a three dimensional memory

Method for making a three-dimensional memory array incorporating se...

Anti-fuse memory cell with asymmetric breakdown voltage

Three-dimensional memory array and method of fabrication

Same conductivity type highly-doped regions for antifuse memory cell

Three-dimensional memory array incorporating serial chain diode stack

Patterning three dimensional structures

Thermal processing for three dimensional circuits

Formation of antifuse structure in a three dimensional memory

Low cost three-dimensional memory array

Digital memory method and system for storing multiple bit digital data

Method of forming nonvolatile memory device utilizing a hard mask

Three-dimensional memory array and method of fabrication

Fabrication of gated electron-emitting devices utilizing distribute...

Patents Applicationslast 30 patents

Reverse-bias method for writing memory cells in a memory array

Manufacturing method for integrated circuit having disturb-free pro...

Apparatus and method for disturb-free programming of passive elemen...

Apparatus and method for disturb-free programming of passive elemen...

Three-dimensional memory array and method of fabrication

Integrated circuit and method for selecting a set of memory-cell-la...

Three-dimensional memory array and method of fabrication

Electrically isolated pillars in active devices

Electrically isolated pillars in active devices

Silicon nitride antifuse for use in diode-antifuse memory arrays

ELECTRICALLY ISOLATED PILLARS IN ACTIVE DEVICES

Three-dimensional memory array incorporating serial chain diode stack

Method for making a three-dimensional memory array incorporating se...

Anti-fuse memory cell with asymmetric breakdown voltage

Thermal processing for three dimensional circuits

Anti-fuse memory cell with asymmetric breakdown voltage

Patterning three dimensional structures

Process for fabricating a dielectric film using plasma oxidation

Three-dimensional memory array incorporating serial chain diode stack

Memory cell with antifuse layer formed at diode junction

Formation of antifuse structure in a three dimensional memory

Three-dimensional memory array and method of fabrication

Formation of antifuse structure in a three dimensional memory

THREE-DIMENSIONAL MEMORY ARRAY AND METHOD OF FABRICATION

Patterning three dimensional structures

METHOD OF FORMING NONVOLATILE MEMORY DEVICE UTILIZING A HARD MASK

Low-cost three-dimensional memory array

Arithmetic unit

Nonvolatile memory on SOI and compound semiconductor substrates and...