1. Field of the Invention
The present invention relates to a carrier tape which is used when a plurality of relatively small electronic devices such as semiconductor devices are consecutively manufactured, to a method of manufacturing the electronic device with the carrier tape, and to an electronic device package with the carrier tape. This is a counterpart of and claims priority to Japanese Patent Application No. 2004-141401 filed on May 11, 2004, which is herein incorporated by reference.
2. Description of the Related Art
In the related art, a carrier tape has a plurality of sprocket holes which are formed along both of long edges of the carrier tape. The sprocket holes are arranged in a line at standardized pitches along each of the long edges. Before the electronic devices including a plurality of electronic components are consecutively manufactured in an assembly process, the carrier tape is reeled by a sprocket. Each of the standardized pitches of the sprocket holes is equal to the pitch between teeth of the sprocket. Depending on the sort of product, device holes are formed between the sprocket holes arranged along both of the long edges in the carrier tape by using a mold tool. In order to make the mold tool small, an invention has been proposed in Document 1 (Japanese Patent Publication Laid-Open No. 2001-179693). As described in paragraph [0012] on page 3 to paragraph [0018] on page 4 of the Document 1, a plurality of pilot holes are formed between the long edge and the line of the sprocket holes in the carrier tape and are divided into groups respectively including a predetermined number of the pilot holes. In the assembly process of the electronic devices, the pilot holes are used for an alignment between the electronic components and the device holes of the carrier tape.
However, in the above-mentioned carrier tape as described in the Document 1, since locations of the electronic components are decided by each group of the pilot holes, there are some regions in which the electronic component can not be located between adjacent groups of the pilot holes. That is, wasted spaces exists between adjacent groups of the pilot holes in the carrier tape, and furthermore, an exchange frequency of the carrier tape increases during the assembly process.
According to an aspect of the present invention, there is provided a carrier tape configured for use in an electronic device assembly process. The carrier tape includes a base film having a long edge and a plurality of first holes which extend through the base film. The first holes are aligned in a line that is adjacent to and parallel to the long edge of the base film and are spaced at a regular pitch. The carrier tape further includes a plurality of second holes which extend through the base film and which are aligned in the line. The second holes are spaced at the regular pitch and are respectively located between adjacent pairs of the first holes.
According to another aspect of the present invention, there is provided a method of manufacturing an electronic device in an assembly process includes processes described below. The tape carrier is provided which has a base film having a long edge and a plurality of first holes which extend through the base film. The first holes are aligned in a line that is adjacent to and parallel to the long edge of the base film and are spaced at a regular pitch. The carrier tape further includes a plurality of second holes which extend through the base film and which are aligned in the line. The second holes are spaced at the regular pitch and are respectively located between adjacent pairs of the first holes. Next, a first electronic component is aligned at a first region of the carrier tape by using at least one of the first holes and is mounted at the first region of the carrier tape. Then, the carrier tape is transferred by action of a sprocket having teeth extending into the first holes or the second holes of the carrier tape. Then, a second electronic component is aligned at a second region of the carrier tape by using at least one of the second holes and is mounted at the second region of the carrier tape.
According to the other aspect of the present invention, there is provided a tape carrier package which includes a carrier tape having a base film having a long edge and a plurality of first holes which extend through the base film. The first holes are aligned in a line that is adjacent to and parallel to the long edge of the base film and are spaced at a regular pitch. The carrier tape further includes a plurality of second holes which extend through the base film and which are aligned in the line. The second holes are spaced at the regular pitch and are respectively located between adjacent pairs of the first holes. The tape carrier package further includes a first electronic component located in a first region of the carrier tape and aligned with with one of the first holes. The first electronic component is covered with a first resin. The tape carrier package still further includes a second electronic component located in a second region, which is different from the first region, of the carrier tape and aligned with one of the second holes. The second electronic component is covered with a second resin.
The above and further aspects and novel features of the invention will more fully appear from the following detailed description, appended claims and the accompanying drawings.
Embodiments of the present invention will be described hereinafter with references to the accompanying drawings. The drawings used for this description illustrate major characteristic parts of embodiments in order that the present invention will be easily understood. However, the invention is not limited by these drawings.
As shown in
The configuration of a semiconductor unit 4 of a TCP type according to the first preferred embodiment of the present invention is described below.
There are a plurality of semiconductor element locating regions 2b between the long edge regions 2a of the carrier tape 1. A device hole 20 is formed in each of the semiconductor element locating regions 2b. A plurality of first outer leads 7 for input signals and a plurality of second outer leads 8 for output signals are formed on the carrier tape 1 around the device hole 20. Also, a plurality of inner leads 11 are formed on the carrier tape 1 between the device hole 20 and the first and second outer leads 7 and 8. A portion of the inner leads 11 and the first and second outer leads 7 and 8 are fixed on the carrier tape 1 through an adhesive layer 14 and covered with a solder resist 12. A plurality of semiconductor elements 10 including first and second semiconductor elements 10a and 10b are respectively located in the device holes 20 of the carrier tape 1. The semiconductor element 10 has a plurality of electrodes 9 connected with the inner leads 11. Each of the semiconductor elements 10 is covered with a molding resin 13. A plurality of test pads 15 are connected with the second outer leads 8 and are used for an electrical test of the semiconductor unit 4 on the carrier tape 1 before the TCP is divided into each of the semiconductor units 4. Each of the semiconductor units 4 is separated from the carrier tape 1 by a plurality of cutting regions including first and second cutting regions 5a and 5b.
Furthermore, as shown in
As shown in
When a plurality of the cutting regions, in which a plurality of the semiconductor elements 10 are respectively mounted, are set to be positioned on the carrier tape 1, a center line of the size B of the first hole 3 or the second hole 17 which is perpendicular to the longitudinal direction is conformed to a center line of a size C of one of the cutting regions (hereinafter referred to as “a cutting region size C”) which is perpendicular to the longitudinal direction (which is like the dashed line I-I′). The first hole 3 or the second hole 17 in the above-mentioned case may be called a criterial hole 19. In this example, the first cutting region 5a in which the first semiconductor element 10a is mounted is set to be positioned on the carrier tape 1 by taking one of the second holes 17 as a first criterial hole 19a. Likewise, the second cutting region 5b in which the second semiconductor unit 10b is located is set to be positioned on the carrier tape 1 by taking one of the first holes 3 as a second criterial hole 19b. The criterial holes 19 which are used for setting the cutting regions 5 are located at predetermined pitches L (hereinafter referred to as “criterial hole pitches L”) so that adjacent semiconductor units 4 can be kept away from each other and so that each of intervals between the adjacent semiconductor units 4 can be shortened as much as possible. When a total device size of the semiconductor unit 4 which takes the test pad 15 and the first outer lead 7 into account in the longitudinal direction is denoted by “T”, preferably the criterial hole pitch L is larger, for example, by 0.05 mm-0.2 mm than the total device size T.
A method of manufacturing a plurality of semiconductor devices including first and second semiconductor elements 10a and 10b by using the sprocket and the carrier tape 1 in the assembly process is described below.
At first, the carrier tape 1 with the long edge regions 2a is provided. The carrier tape 1 has a plurality of the first holes 3 and a plurality of the second holes 17 which extend through the base film 2 and are aligned in the long edge regions 2a of the base film 2. Also, a plurality of the device holes 20 are positioned in the semiconductor element locating region 2b, based on the criterial holes 19 which are selected among the first holes 3 and the second holes 17 at the criterial hole pitches L. Furthermore, the inner leads 11 and the first and second outer leads 7 and 8 are located around the device holes 20 by etching a beaten-copper layer formed on the semiconductor element locating region in photo lithography and etching processes.
Next, a plurality of the semiconductor elements 10 including the first and second semiconductor elements 10a and 10b are provided. Before the semiconductor elements 10 are located in the device holes 20, a positioning information about the first criterial hole 19a (which is one of the second holes 17) is input into the semiconductor equipment. The transferring movement of the carrier tape 1 is executed by the sprocket and the pulse motor while the detector 18 detects the anterior edges of the first hole 3 and the second hole 17. When the detector 18 detects an anterior edge of the first hole 3 or the second hole 17 before the anterior edge of the first criterial hole 19a is detected, the electrical drive unit begin to reduce a speed of the rotation of the sprocket by a feedforward control of the friction brake. The foregoing reduction in the rotational speed of the sprocket restrains the first hole 3 or the second hole 17, into which the tooth of the sprocket is placed, from getting damaged by a quick stop. When the detector 18 detects the anterior edge of the first criterial hole 19a, the transferring movement of the carrier tape 1 is interrupted by the friction brake. Then, the first semiconductor element 10a is mounted in the first cutting region 5a. At this time, a center line of the first semiconductor element 10a which is perpendicular to the longitudinal direction may be conformed to the center line of the first cutting region 5a which is perpendicular to the longitudinal direction. Also, the electrodes 9 are connected with the inner leads 11, for example, by an eutectic thermo compression method depending on temperature, pressure and time of loading of a bonding tool by which the inner leads 11 are connected with the electrodes 9 or by a welding method using ultrasonic waves.
After mounting the first semiconductor element 10a, the transferring movement of the carrier tape 1 is executed again. When the light emission element 18a and the light-sensitive element 18b detect an anterior edge of the first hole 3 or the second hole 17 before the anterior edge of the second criterial hole 19b is detected, the electrical drive unit begins to reduce the speed of the rotation of the sprocket by the feedforward control of the friction brake, in order to restrain the first hole 3 or the second hole 17 from getting damaged by the quick stop. Hereupon, as described above, the second criterial hole 19b is the one of the first holes 3 which is located away from the first criteria hole 19a at the criteria hole pitch L. When the light emission element 18a and the light-sensitive element 18b detect the anterior edge of the second criterial hole 19b, the transferring movement of the carrier tape 1 is interrupted by the friction brake. Then, the second semiconductor element 10b is located in the second cutting region 5b. At this time, a center line of the second semiconductor element 10b which is perpendicular to the longitudinal direction may be conformed to a center line of the second cutting region 5a which is perpendicular to the longitudinal direction. Also, the electrodes 9 are connected with the inner leads 11, for example, by an eutectic thermo compression method depending on temperature, pressure and time of loading of a bonding tool by which the inner leads 11 are connected with the electrodes 9 or by a welding method using ultrasonic waves.
From then on, remaining semiconductor elements 10 are sequentially located in remaining cutting regions 5 of the semiconductor element locating region 2b of the carrier tape 1 as well as the first and second semiconductor elements 10a and 10b are located. In this embodiment, all of the semiconductor elements 10 and all of the cutting regions 5 are located in the semiconductor element locating region 2b at the criterial hole pitches L. Also, an alignment hole 6 is located in each of the cutting regions 5. After locating all of the semiconductor elements 10 on one roll of the carrier tape 1, each of the semiconductor units 4 in the cutting regions 5 is separated from the carrier tape 1 by using a punch press and a dicing cutter. Alternatively, the carrier tape 1 may be divided into a plurality of semiconductor unit groups which respectively include some of a plurality of the semiconductor units 4 by being cut in rectangles. Also, after the semiconductor unit groups which are cut in rectangles are shipped to electronic makers as intermediate products, each of the semiconductor units 4 in the cutting regions 5 may be separated apart from the carrier tape 1 into individual products in the electronic makers.
In addition, the sprocket described in this embodiment is set in a place different from the place for the locating operation of the semiconductor elements 10. Therefore, the sprocket does not discourage the detector 18 from detecting the anterior edge of the first hole 3 or the second hole 17. Also, the sprocket described in this embodiment has teeth at the standardized pitches of the first holes 3 and the second holes 17. Therefore, when the teeth of the sprocket are put into the first holes 3, the teeth are not put into the second holes 17. On the other hand, when the teeth of the sprocket are put into the second holes 17, the teeth are not put into the first holes 3.
Hereupon, it is described below as an example that a plurality of semiconductor devices which has the total device size T of 14.6 mm are manufactured with the carrier tape 1. When the carrier tape 1 has only the first holes 3 which are arranged at the standardized pitches of 4.75 mm, the cutting regions 5 are located on the carrier tape 1 at pitches defined by five adjacent first holes 3. Each of these pitches corresponds to a pitch defined by nine of adjacent first holes 3 and second holes 17 in the present invention. That is, in this example, the value of the criterial hole pitch L is set to 19 mm. On the other hand, when the carrier tape 1 has both the first holes 3 and the second holes 17 which are alternatively arranged at pitches of 2.375 mm like in the present invention, the cutting regions 5 can be located on the carrier tape 1 at pitches defined by eight of the adjacent first holes 3 and second holes 17 in the present invention. That is, in this example, the value of the criterial hole pitch L can be set to 16.625 mm. Therefore, when the same number of pieces of the semiconductor devices is manufactured in the related art and the present invention, the entire length of the carrier tape 1 in the present invention can be shortened by 12.5% of the entire length of the carrier tape in the related art. As a result, it can be realized that the cost of the carrier tape is reduced.
Furthermore, it is described below as an example that a plurality of semiconductor devices which has the total device size T of 14.6 mm are manufactured with the carrier tape 1 which has an entire length of 40 m. Hereupon, it is assumed that an extraction rate of the carrier tape 1 is 95%. When the carrier tape 1 has only the first holes 3 which are arranged at the standardized pitches of 4.75 mm, 2000 pieces of the semiconductor devices are manufactured from one roll of the carrier tape 1 because one of the semiconductor devices requires the carrier tape of 19 mm. On the contrary, when the carrier tape 1 in the present invention is used, 2285 pieces of the semiconductor devices are manufactured from one roll of the carrier tape 1 because one of the semiconductor devices requires the carrier tape of 16.625 mm. That is, the number of the semiconductor devices tha can be manufactured in the present invention is about 1.14 times the related art. Therefore, the exchange frequency of the carrier tape can be decreased. As a result, it can be realized that the productive efficiency of the electronic devices is improved.
In the present invention, the configurations of the first hole 3 and the second hole 17 are concurrently represented by the quadrangles in the drawings. However, when a detector which detects the (anterior) edge of the first hole 3 or the second hole 17 is used, the configuration of the second hole 17 may be rectanglar or circular as long as the size B of the second hole 17 is equal to the size B of the first hole 3 in the longitudinal direction.
According to the first preferred embodiment, the carrier tape, which has a plurality of the first holes arranged on a line at the standardized pitches, includes a plurality of the second holes arranged on the same line as the first holes are at the standardized pitches. Moreover, each of the second holes is located between adjacent first holes of a plurality of the first holes. Therefore, a plurality of the cutting regions, in which the semiconductor elements are respectively mounted, can be set on the carrier tape at shorter pitches. As a result, the entire length of the carrier tape can be shortened, and thus the cost of the carrier tape is reduced. Also, the exchange frequency of the carrier tape can be decreased, and thus the productive efficiency of the electronic devices is improved. Also, in the present invention, a plurality of the second holes can be formed in the carrier tape which previously has a purality of the first holes spaced at the regular pitch without sophisticated changes of design. Therefore, the carrier tape which produces the above mentioned effects can be easily realized.
Furthermore, if the second holes are formed so that they have configurations into which the teeth of the sprocket are placed, the exchange of the carrier tapes can be easily executed without distinguishing between the first holes and the second holes in the assembly process. As a result, the efficiency in the exchange of the carrier tape can be improved. Also, in first preferred embodiment of the present invention, since the second holes are formed on the same line as the first holes are, increasing of the width of the carrier tape can be restrained. Therefore, the carrier tape of the present invention can be applied to existing manufacturing equipment.
In addition, in the present invention, though the first and second holes are formed in both of the long edge regions of the carrier tape, they may be formed only in one of the long edge regions of the carrier tape. Also, the first and second holes can be detected by an imaging sensor such as a CCD camera instead of the detector which detects the anterior edge of the first hole or the second hole. When the imaging sensor is used, a center point of the first hole or the second hole is detected. Therefore, it is not necessary that the size B of the second hole is equal to the size B of the first hole in the longitudinal direction. That is, the second holes can be easily formed.
In the second preferred embodiment, a plurality of semiconductor elements 10 are respectively located on the cutting regions 5 without forming the device holes in the carrier tape 1. Then, each of the cutting regions 5 is separated from the carrier tape 1 as in the first preferred embodiment. Each of these types of the semiconductor devices is called a Chip On Film (hereinafter referred to as “COF”) type semiconductor device. The other configurations of the semiconductor devices 21 according to the second preferred embodiment are the same as those according to the first preferred embodiment. The semiconductor element 10 has a chip surface where a plurality of the electrodes 9 are formed. The semiconductor elements 10 are located on the carrier tape 1 while the chip surfaces face the carrier tape 1. After locating the semiconductor elements 10 on the carrier tape 1, the molding resin 13 is provided between each of the semiconductor elements 10 and the carrier tape 1.
In the second preferred embodiment, the semiconductor elements 10 are sequentially located on the cutting regions 5 of the carrier tape 1 in accordance with the criterial holes 19 formed on the long edge region 2a as in the first preferred embodiment. Hereupon, it is assumed that the carrier tape 1 has the first holes 3 and the second holes 17 which are alternatively arranged at half the standardized pitches of 4.75 mm. It is described below as an example that a plurality of the COF type semiconductor devices 21 which has the total device size T of 14.6 mm are manufactured with the carrier tape 1. In this example, the value of the criterial hole pitch L can be set to 16.625 mm as described in the first preferred embodiment. One the other hand, when the carrier tape 1 has only the first holes 3 which are arranged at the standardized pitches of 4.75 mm, the value of the criterial hole pitch L is set to 19 mm. Therefore, when the same number of pieces of the COF type semiconductor devices 21 is manufactured in the related art and the present invention, the entire length of the carrier tape 1 in the present invention can be shortened by 12.5% of the entire length of the carrier tape in the related art. As a result, the cost of the carrier tape is reduced.
Furthermore, it is described below as an example that a plurality of the COF type semiconductor devices 21 which has a total device size T of 14.6 mm are manufactured with the carrier tape 1 which has an entire length of 40 m. Hereupon, it is assumed that the carrier tape 1 has the first holes 3 and the second holes 17 which are alternatively arranged at a half of the standardized pitch of 4.75 mm and that an extraction rate of the carrier tape 1 is 95%. In this example, 2285 pieces of the COF type semiconductor devices 21 are manufactured from one roll of the carrier tape 1. On the other hand, when the carrier tape 1 has only the first holes 3 which are arranged at the standardized pitches of 4.75 mm, 2000 pieces of the COF type semiconductor devices 21 are manufactured from one roll of the carrier tape 1. That is, the COF type semiconductor devices can be manufactured in the present invention about 1.14 times as many as in the related art. Therefore, the exchange frequency of the carrier tape can be decreased. As a result, the productive efficiency of the semiconductor devices is improved as in the first preferred embodiment.
As described above, according to the second preferred embodiment, the carrier tape, which has a plurality of the first holes arranged on a line at the standardized pitches, includes a plurality of the second holes arranged on the same line as the first holes at the standardized pitches. Moreover, each of the second holes is located between adjacent first holes. Therefore, a plurality of the cutting regions, in which the COF type semiconductor elements are respectively located, can be set on the carrier tape at shorter pitches. As a result, the entire length of the carrier tape can be shortened, and thus the cost of the carrier tape is reduced. Also, the exchange frequency of the carrier tape can be decreased, and thus productive efficiency of the COF type semiconductor devices is improved. Also, in the present invention, a plurality of the second holes can be formed in the carrier tape which previously has a purality of the first holes arranged at the standardized pitches without sophisticated changes of design. Therefore, the carrier tape which produces the above mentioned effects can be easily realized.
In the third preferred embodiment, a plurality of semiconductor elements 31 are respectively mounted on the cutting regions 5 without forming the device holes in the carrier tape 1. Then, each of the cutting regions 5 is separated from the carrier tape 1 as in the first preferred embodiment. In this embodiment, each of these types of semiconductor devices 31 is called a Ball Grid Array (hereinafter referred to as “BGA”) type semiconductor device. The configurations of the first holes 3 and the second holes 17 are the same as those according to the first and second preferred embodiment. The semiconductor element 10 has a top surface where a plurality of electrode pads 32 are formed and a rear surface opposite to the top surface. The carrier tape 1 has a plurality of wiring patterns 33 which are formed on the semiconductor element locating region 2b through a first adhesive layer 38. The wiring patterns 33 are covered with a solder resist layer 36. The semiconductor elements 10 are located on the solder resist layer 36 through a second adhesive layer 39. The electrode pads 32 of the semiconductor element 10 are connected with the wiring patterns 33 by a plurality of bonding wires 34. On opposite sides of the wiring patterns 33 are a plurality of land patterns 35. The carrier tape 1 has a plurality of land openings 41 in each of the cutting regions 5, and the land patterns 35 are exposed from the land openings 41. A plurality of external electrodes 40 are formed on the land patterns 35 through the opening 41.
In the third preferred embodiment, two of the semiconductor elements 10 are mounted on the carrier tape 1 in a direction perpendicular to the longitudinal direction in which the transferring movement of the carrier tape 1 is executed. That is, every two of the semiconductor elements 10 is located in the cutting regions 5 based on the criterial hole 19. After mounting the semiconductor elements 10 on the carrier tape 1, the electrode pads 32 are connected with the wiring patterns 33 by the bonding wires 34, and then, the semiconductor elements 10 are covered with molding resin 37.
Hereupon, it is described below as an example that a plurality of the BGA type semiconductor devices 31 which has a total device size T of 11.189 mm are manufactured with the carrier tape 1. Also, it is assumed that the carrier tape 1 has the first holes 3 and the second holes 17 which are alternatively arranged at a half of the standardized pitch of 4.75 mm as in the first and second preferred embodiments. In this example, the cutting regions 5 can be located on the carrier tape 1 at pitches defined by five adjacent first holes 3 and second holes 17 in the present invention. That is, in this example, the value of the criterial hole pitch L can be set to 11.875 mm. On the other hand, when the carrier tape 1 has only the first holes 3 which are arranged at the standardized pitches of 4.75 mm, the cutting regions 5 are located on the carrier tape 1 at pitches defined by three adjacent first holes 3. Each of these pitches corresponds to a pitch defined by six adjacent first holes 3 and second holes 17 in the present invention. That is, the value of the criterial hole pitch L is set to 14.25 mm. Therefore, when the same number of pieces of the BGA type semiconductor devices 31 is manufactured in the related art and the present invention, the entire length of the carrier tape 1 in the present invention can be shortened by 16.7% of the entire length of the carrier tape in the related art. As a result, the cost of the carrier tape is reduced.
Furthermore, it is described below as an example that a plurality of the BGA type semiconductor devices 31 which has a total device size T of 11.189 mm are manufactured with the carrier tape 1 which has an entire length of 40 m. Hereupon, it is assumed that the carrier tape 1 has the first holes 3 and the second holes 17 which are alternatively arranged at a half of the standardized pitch of 4.75 mm and that an extraction rate of the carrier tape 1 is 95%. In this example, 6400 pieces of the BGA type semiconductor devices 31 are manufactured from one roll of the carrier tape 1. On the other hand, when the carrier tape 1 has only the first holes 3 which are arranged at the standardized pitches of 4.75 mm, 5332 pieces of the BGA type semiconductor devices 31 are manufactured from one roll of the carrier tape 1. That is, the number of the BGA type semiconductor devices that can be manufactured in the present invention is about 1.20 times the related art. Therefore, the exchange frequency of the carrier tape can be decreased. As a result, it can be realized that the productive efficiency of the semiconductor devices is improved as in the first and second preferred embodiments.
As described above, according to the third preferred embodiment, the carrier tape, which has a plurality of the first holes arranged on a line at the standardized pitches, includes a plurality of the second holes arranged on the same line as the first holes are at the standardized pitches. Moreover, each of the second holes is located between adjacent first holes. Therefore, a plurality of the cutting regions, in which the BGA type semiconductor elements are respectively located, can be set on the carrier tape at shorter pitches. As a result, the entire length of the carrier tape can be shortened, and thus the cost of the carrier tape is reduced. Also, the exchange frequency of the carrier tape can be decreased, and thus the productive efficiency of the BGA type semiconductor devices is improved. Also, in the present invention, a plurality of the second holes can be formed in the carrier tape which previously has a purality of the first holes arranged at the standardized pitches without sophisticated changes of design. Therefore, the carrier tape which produces the above mentioned effects can be easily realized.
Also, in each of the above mentioned three preferred embodiments, each of the second holes 17 may be arranged so as to be closer to either one of the adjacent first holes 3 as long as the second holes 17 are spaced at the regular pitch P as shown in
Number | Date | Country | Kind |
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141401/2004 | May 2004 | JP | national |