Patent Application
20050212097
Device failure models and test methods define the sensitivity of electronic devices and assemblies that need to be protected from the effects of electrostatic discharge (ESD). Two of the key elements in any successful static-control program are the identification of those items—whether components, assemblies, or finished products—that are sensitive to ESD, and the determination of the level of their sensitivity. The damage done to an electrostatic-discharge-sensitive (ESDS) device by an ESD event depends on the device's ability either to dissipate the energy of the discharge or to withstand the current levels involved. This is known as device ESD sensitivity or ESD susceptibility.
Certain devices may be more readily damaged by discharges occurring within automated equipment, while others may be more prone to damage from handling by personnel. There exist models and test procedures that are used to characterize, determine, and classify the sensitivity of components to ESD. The test procedures are based on the three primary models of ESD events: human body model (HBM), machine model (MM), and charged device model (CDM). While the models employed to perform component testing cannot replicate the full spectrum of all possible ESD events, they have proven successful in reproducing over 95% of all ESD field-failure signatures. The use of standardized test procedures has allowed the industry to: development and measure suitable on-chip protection; make comparison among various devices; and, provide a system of ESD-sensitivity classification to assist in the ESD design and ESD monitoring requirements of the manufacturing and assembly environments.
The human body model (HBM) tests one of the common causes of electrostatic damage, the direct transfer of electrostatic charge through a significant series resistor (+/−1.5 kiloohms) from either the human body or a charged material to the ESDS device. When a person walks across a floor, an electrostatic charge accumulates on his or her body. Simple contact of a finger to the leads of an ESDS device or assembly permits the body to discharge, possibly causing device damage. Thus, the model used to simulate this event is called the human body model (HBM).
The machine model (MM) tests another kind of discharge, similar to the HBM event, which can occur from a charged conductive object such as a metallic tool or fixture. Originating in Japan as a result of attempts to create a worst-case HBM event, this ESD machine model, consists of a 200-picofarad capacitor discharged directly into a component, with no series resistor. As a worst-case HBM, the machine model may be overly severe. However, there are certain real-world situations that this model represents, such as the rapid discharge from a charged board assembly or from the charged cables of an automatic tester.
Finally, the charged device model (CDM) involves the transfer of charge from an ESDS device as an ESD event. A device may, for instance, become charged when sliding down the feeder in an automated assembler. If it then contacts the insertion head or some other conductive surface, a rapid discharge may occur from the device to the metal object. This so-called CDM event can even be more destructive than the HBM event for some devices. Although the duration of the discharge is very short, often less than one nanosecond, the peak current can reach several tens of amperes.
Several test methods have been explored to duplicate the real-world CDM event and replicate the conditions that have been observed in CDM-caused field failures. Efforts in this area are currently focusing on two separate test methods. The first, known as CDM, better simulates the actual charged-device event, while the second addresses devices that are inserted into a socket and then charged and discharged in the same socket. This second method is termed the socketed discharge model, or SDM.
A draft standard for CDM, designated ESD-DS5.3.1-1996, and a standard for CDM, designated ANSI/ESD STM5.3.1-1999, have been released by and are available from the Electrostatic Discharge Association, of Rome, N.Y., which has an Internet world-wide web site at www.esda.org. This test procedure can involve placing the device on a field plate with its leads pointing up, and then charging and discharging the device.
The current through the resistor 114 is directly affected by how quickly the charge placed on the example device 102 is able to be discharged to ground. Thus, slower discharge of the charge on the device 102 is desirable, because then the current through the resistor 114 is lower. The discharge time is inversely related to the RC constant of the resistor 114 and the capacitance 106. Lower capacitances and resistances therefore increase the discharge time, and thus reduce the current through the resistor 114. However, decreasing the capacitance of the example device 102 can be difficult to accomplish.
For these reasons, as well as other reasons, there is a need for the present invention.
The invention relates to an improved charged device model (CDM) electrostatic discharge (ESD) failure rate, during CDM ESD testing, by applying a capacitive coating to an integrated circuit (IC). An IC of the invention includes a primary substrate, a number of contacts, and a capacitive coating. The primary substrate has a top surface, a bottom surface, and a number of side surfaces. The contacts are on the top surface of the primary substrate, and are connectable to pins of a packaging element. The capacitive coating is on at least the bottom surface of the primary substrate, to make contact with a lead frame intended to secure the primary substrate to the packaging element.
An electronic device of the invention includes a packaging element, an IC, a number of contacts, a capacitive coating, and a lead frame. The packaging element has a number of pins to externally connect the electronic device. The IC has a top surface, a bottom surface, and a number of side surfaces. The contacts are on the top surface of the IC, and are connected to the pins of the packaging element. The capacitive coating is at least on the bottom surface of the IC. The lead frame is to secure the IC to the packaging element, where the capacitive coating is sandwiched between the IC and the lead frame.
A method of the invention first coats at least a bottom surface of an IC with a capacitive dielectric having a low k value. Contacts on the top surface of the IC are connected to corresponding pins of a packaging element. The bottom surface of the IC, including the capacitive dielectric, is secured to a lead frame. The lead frame is then secured to the packaging element, such that the capacitive dielectric is sandwiched between the IC and the lead frame. The method may conclude by performing ESD testing on the IC, such as by performing CMD testing on the IC.
Embodiments of the invention provide for advantages over the prior art. The capacitive coating provides a capacitance that is electrically in series with the internal, or parasitic, capacitance of the IC itself, such as of the primary substrate itself. Therefore, the total capacitance during CDM ESD testing is decreased, decreasing the RC constant that governs discharge of a charge placed on the IC during CDM ESD testing. As a result, discharge occurs more slowly, as the discharge current is related to the RC constant. The maximum discharge current at any given time thus is decreased as well. This allows the IC, and the electronic device of which it is a part, to better withstand CDM ESD testing, improving the CDM ESD failure rate.
Still other advantages, aspects, and embodiments of the invention will become apparent by reading the detailed description that follows, and by referring to the accompanying drawings.
The drawings referenced herein form a part of the specification. Features shown in the drawing are meant as illustrative of only some embodiments of the invention, and not of all embodiments of the invention, unless otherwise explicitly indicated, and implications to the contrary are otherwise not to be made.
In the following detailed description of exemplary embodiments of the invention, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific exemplary embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized, and logical, mechanical, and other changes may be made without departing from the spirit or scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims.
A capacitive coating 406 has been applied to the bottom surface of the primary substrate 402 of the IC 400 in
The capacitive coating 406 has been applied to the bottom surface of the primary substrate 402 of the IC 400 in
The electronic device 600, besides the IC 400, includes a packaging element 604 having a number of pins 606A, 606B, 606C, . . . , 606N, collectively referred to as the pins 606, and a lead frame 602. As has been described, the packaging element is generally a protective container for a semiconductor chip, such as the IC 400, that has electrically connectable external leads, or pins 606. Although the pins 606 are depicted as only being on the front side of the packaging element 604, this is for illustrative clarity. More typically, the pins 606 will be on more than one side of the packaging element 604, such as the front side and the back side, all the sides of the element 604, and/or on the bottom of the packaging element 604. The contacts 404 are correspondingly connected to the pins 606, enabling the IC 400 to be externally electrically connected, via the pins 606.
The lead frame 602 is to secure the IC 400 to the packaging element 604. As such, the bottom of the IC 400, specifically the capacitive coating 406, makes contact with the lead frame 602 on one side of the lead frame 602, and the other side of the lead frame 602 makes contact with the packaging element 604. In general, the lead frame 602 is a metallic frame containing leads and a based to which the IC 400 is connected. For illustrative clarity only, the lead frame 602 is represented as a rectangular block in
During charged device model (CDM) electrostatic discharge (ESD) testing, a charge is placed on the IC 400, such as on the substrate 402 of the IC 400, by connecting one or more of the pins 606, such as the pin 606C, to a high-voltage source. Thereafter, the high-voltage source is removed, and one or more of the pins 606 are grounded. As depicted in
The discharge of the charge 702 on the IC 400 occurs on a path from left to right, as denoted by the arrow 708. The discharge passes through the capacitances 704 and 705 in series with one another, through the resistance 706 in series with the capacitances 704 and 705, through the pin 606C of the electronic device 600, and finally to ground 608. Where the capacitance 704 is represented as the value C, and the resistance 706 is represented as the value R, the discharge constant is represented by the product RC if the capacitive coating 406 is not present. However, where the capacitive coating 406 is present, providing the capacitance 705 that may be represented as the value C′, the total capacitance of the capacitances 704 and 705 in series is represented by the quantity CC′/(C+C′), which is necessarily less than C. This decreases the discharge constant, now represented by the product RCC′/(C+C′). Because discharge time is inversely related to the discharge constant, decreasing the discharge constant slows discharge of the charge 702, reducing the maximum current at any given time over the discharge path to ground 608, as denoted by the arrow 708 in
That is, adding the capacitive coating 406 results in an effective capacitance 705 being placed in series with the internal, or parasitic, capacitance 704 of the IC 400. The capacitive coating 406 results in the effective capacitance 705 because at least some portion of the substrate 402 of the IC, and the lead frame 602, act as conductive plates to the capacitive coating 406, which serves as the dielectric. Adding the capacitance 705 in series with the capacitance 704 reduces the overall capacitance within the discharge path of the charge 702 to ground 608. This decreases the discharge constant, which increases discharge time, and reduces the maximum current through the discharge path to ground 608, as denoted by the arrow 708 in
Next, the contacts on the top surface of the IC are connected electrically to corresponding pins of a packaging element (904). The contacts may be the contacts 404 of
The bottom surface of the IC, with its capacitive dielectric, is then secured to a lead frame (906), and the lead frame is secured to the packaging element, such that the capacitive dielectric is sandwiched between the IC and the lead frame (908). The lead frame may be the lead frame 602 of
Finally, CDM ESD testing of the resulting electronic device may be performed (910). As has been described, the addition of the capacitive dielectric coating to the bottom surface of the IC reduces the total capacitance within the discharge path of the charge stored on the IC during CDM ESD testing. This reduces the RC, or discharge constant, increasing the time it takes for the charge to discharge to ground. Thus, the failure rate of the IC during CDM ESD testing is improved, because the IC is less likely to fail, as can be appreciated by those of ordinary skill within the art.
It is noted that, although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement is calculated to achieve the same purpose may be substituted for the specific embodiments shown. This application is intended to cover any adaptations or variations of the present invention. Therefore, it is manifestly intended that this invention be limited only by the claims and equivalents thereof.
