BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
FIGS. 1A-1F illustrate a manufacturing process of a chip structure according to an embodiment of the present invention.
FIG. 2A illustrates the appearance of another spacer according to the embodiment of the present invention.
FIG. 2B illustrates the appearance of yet another spacer according to the embodiment of the present invention.
FIGS. 3A-3D illustrate a manufacturing process of a chip structure according to another embodiment of the present invention.
FIG. 4 illustrates a chip package according to an embodiment of the present invention.
DESCRIPTION OF EMBODIMENTS
The present invention provides a chip structure including an integrated circuit (IC) element, a plurality of bumps, and at least one spacer. The IC element has a plurality of contacts. The bumps are disposed on the contacts. The spacer is disposed on the IC element and between two bumps adjacent to each other, wherein the maximum thickness of the spacer is less than or equal to the thickness of the bumps. The manufacturing process of the chip structure will be described in detail in following embodiments.
FIGS. 1A-1F illustrate a manufacturing process of a chip structure according to an embodiment of the present invention. Referring to FIG. 1A, a wafer W is first provided. The wafer W has a plurality of IC elements 110, and each of the IC elements 110 has a plurality of contacts 112, wherein the material of the contacts 112 may be aluminum or other conductive material.
Referring to FIG. 1B, bumps 120 are formed on the contacts 112. In the present embodiment, a metal layer 125 is formed on the wafer W through chemical vapor deposition (CVD), sputtering, or other method before forming the bumps 120, wherein the metal layer 125 is electrically connected to the contacts 112. After that, the bumps 120 are formed on the contacts 112 through photolithography and plating, wherein the material of the bumps 120 may be gold or other conductive material. It should be noted that the metal layer 125 may be a single layer of metal or composed of multiple layers of metal.
Referring to FIG. 1C, the metal layer 125 (as shown in FIG. 1B) is patterned to form a plurality of under bump metal layers 125a, wherein the under bump metal layers 125a are located between the bumps 120 and the contacts 112 respectively.
Referring to FIG. 1D, a dielectric layer 130 is formed on the wafer W and the bumps 120 through, for example, spin-coating, wherein the material of the dielectric layer 130 may be silicon oxide, silicon nitride, silicon oxy-nitride, polyimide, spin-on-glass (SOG), or other insulation material. It should be noted that when the dielectric layer 130 is formed on the wafer W and the bumps 120 through method such as spin-coating, the dielectric layer 130 and the surface of the wafer W can be bonded to each other closely without any space in between. Besides, in the present embodiment, a plurality of openings 132 may be further formed on the dielectric layer 130 through dry etching for the subsequent process, wherein the openings 132 expose the top surfaces of the bumps 120.
Referring to FIG. 1E, the thickness of the dielectric layer 130 (as shown in FIG. 1D) is reduced and the maximum thickness of the dielectric layer 130 is made equal to the thickness of the bumps so that the top surfaces of the bumps 120 are exposed completely. Accordingly, a spacer 135 can be formed on the IC elements 110 and between two bumps 120 adjacent to each other, wherein the spacer 135 is bonded to the surface of the wafer W closely.
Referring to FIG. 1F, the wafer W (as shown in FIG. 1E) is cut to form a plurality of chip structures 100a.
It should be noted that in foregoing FIG. 1F, the appearance of the spacer 135 is not for limiting the present invention. In other embodiments of the present invention, the maximum thickness of the spacer my also be less than the thickness of the bumps 120, as the spacer 135a of the chip structure 100b shown in FIG. 2A. Besides, the spacer may also have an opening, as the opening O of the chip structure 100c shown in FIG. 2B. In other words, the shape of the spacer is not limited by the present invention as long as the spacer is closely bonded to the IC element and disposed between two bumps adjacent to each other, wherein the maximum thickness of the spacer is less than or equal to the thickness of the bumps.
FIGS. 3A-3D illustrate a manufacturing process of a chip structure according to another embodiment of the present invention. Referring to FIG. 3A, a wafer W is first provided. The wafer W has a plurality of IC elements 110, and each of the IC elements 110 has a plurality of contacts 112, wherein the material of the contacts 112 may be aluminum or other conductive material.
Referring to FIG. 3B, at least one spacer 135c is formed on the IC elements 110 and between two contacts 112 adjacent to each other, wherein the material of the spacer 135c is dielectric material. For example, the formation method of the spacer 135c is to form a dielectric layer first on the wafer through spin-coating, wherein the material of the dielectric layer may be silicon oxide, silicon nitride, silicon oxy-nitride, polyimide, SOG, or other insulation material. It should be noted that since the dielectric layer is formed on the wafer and the bumps through spin-coating, the dielectric layer and the surface of the wafer can be bonded to each other closely without any space in between. After that, the dielectric layer is patterned to form the spacer 135c, wherein the spacer 135c is closely bonded to the surface of the wafer W.
Next, a metal layer 125 is formed on the wafer W through CVD, sputtering, or other method, wherein the metal layer 125 and the contacts 112 are electrically connected. After that, a plurality of bumps 120 are formed on the contacts 112 through photolithography and plating, wherein the material of the bumps 120 may be gold or other conductive material, and the maximum thickness of the spacer 135c is less than or equal to the thickness of the bumps. Accordingly, the spacer 135c is between two bumps 120 adjacent to each other. It should be noted that the metal layer 125 may be a single layer of metal or composed of multiple layers of metal.
Referring to FIG. 3C, the metal layer 125 (as shown in FIG. 3B) is patterned to form a plurality of under bump metal layers 125a, wherein the under bump metal layers 125a are located between the bumps 120 and the contacts 112 respectively.
Referring to FIG. 3D, the wafer W is cut to form a plurality of chip structures 100d.
A chip structure and a substrate can be further assembled into a chip package through packaging technology based on the foregoing chip structures 100a, 100b, 100c, and 100d. FIG. 4 illustrates a chip package according to an embodiment of the present invention. Referring to FIG. 4, the chip package 50 includes a chip structure 100a, a support structure 200, and an underfill 300. The support structure 200 includes a substrate 210 and a circuit layer 220. The substrate 210 may be a flexible substrate or a glass substrate. If the substrate 210 is a flexible substrate, it may be a single flexible dielectric layer or formed by stacking a multiple flexible dielectric layers and multiple circuit layers in a staggered way.
The circuit layer 220 is disposed on a surface 212 of the substrate 210. The chip structure 100a is disposed on and electrically connected to the support structure 200, wherein the bumps 120 are located between the contacts 112 and the internal leads of the circuit layer 220 and electrically connect the contacts 112 to the circuit layer 220 respectively. It should mentioned here that if the substrate 210 is a glass substrate, the bumps 120 may electrically connect the contacts 112 and the internal leads of the circuit layer 220 through an anisotropic conductive film (ACF). The underfill 300 is filled between the chip structure 100a and the support structure 200 and covers the bumps 120 of the chip structure 100a and the spacer 135. When the conducting part of the ACF is used to electrically connect the bumps 120 and the contacts 112, the underfill 300 may be the insulating part of the ACF. It should be noted that in the present embodiment, even though the chip structure 100a is disposed on the support structure 200, in other embodiments of the present invention, the chip structure 100b, 100c, or 100d may also be disposed on the support structure 200.
When the chip package is working, the spacer is bonded to the surface of the IC element closely, thus, the spacer can effectively prevent the bump material from growing outwardly or can greatly increase the growing path of the bump material, so as to effectively prevent short circuit between adjacent bumps due to the outward growth of the bump material. Thus, compared to the conventional art, the chip structure in the present invention can improve the insulation between adjacent bumps greatly. Additionally, since short circuit between adjacent bumps due to the outward growth of the bump material is prevented, a chip package with such chip structures provided by the present invention has higher operation reliability.
Besides the foregoing application for resolving the conventional problems in bonding between chip and flexible substrate, the structures and manufacturing process in the present invention may also be applied to bonding between chips and other materials. The structures and manufacturing method in the present invention can effectively prevent short circuit between metal bumps, so that the present invention can be used in any situation wherein metal bumps are used for connection with external circuit.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Patent Application
20080079134
