Patent Application
20240186230
This application claims the benefit under 35 USC § 119 of Chinese Patent Application No. 2022115428793, filed on Dec. 2, 2022, in the China Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes.
The present application relates to the technical field of semiconductor packaging, in particular to a component package substrate structure and a manufacturing method thereof.
With the development of electronic technology, the performance requirements of electronic products are higher and higher, the size requirements are smaller and thinner, so that the high-density integration and miniaturization of electronic components such as chips, package substrates and packaging structures is an inevitable trend.
In the prior art solution, a package substrate embeds a component in a packaging material, and the component is usually mounted in a cavity, and then packaged and built up. However, the process flow for forming the cavity is relatively complicated, especially when a small-sized cavity needs to be formed, and etching the copper pillars by pattern transfer is required, and the process flow is more cumbersome, increasing a lot of process costs and processing time. At the same time, the method for embedding the components first and then building up will lead to the waste of the circuit of the outer substrate, which will cause the loss of components and greatly increase the manufacturing cost.
In view of this, an object of the present application is to provide a component package substrate structure and a manufacturing method thereof.
Based on the above-mentioned object, the present application provides a method for manufacturing a component package substrate structure, which includes:
An embodiment of the present application also provides a component package substrate structure including:
The component package substrate structure can be manufactured using the manufacturing method described in the present invention.
It can be seen from the above that the component package substrate structure and the manufacturing method thereof provided in the present application that a component can be embedded after a substrate circuit is completed, the component embedding process can be postponed, the conduction between the postponed component and the substrate circuit is achieved by forming a stepped hole, discard of the component as useless due to the poor substrate circuit can be avoided, the component packaging yield can be improved, the component packaging process cost can be reduced to a certain extent and the processing time can be reduced, the component can be embedded after the circuit quality detection of the outer substrate, and the problem of the discard of the component as useless due to the poor substrate circuit can be solved.
In order to explain the present application or the technical solutions in the related art more clearly, a brief description will be given below with reference to the description of the embodiments or the related art; obviously, the drawings in the description below are merely the embodiments of the present application, and it would have been obvious for a person skilled in the art to obtain other drawings according to these drawings without involving any inventive effort.
The objects, technical solutions and advantages of the present application will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.
It should be noted that, unless otherwise defined, technical or scientific terms used in the examples of the present application shall have the ordinary meaning as understood by a person skilled in the art to which the present application belongs. The use of the terms “first”, “second”, and the like in the embodiments herein does not denote any order, quantity, or importance, but rather is used to distinguish one element from another. The word “including” or “includes”, and the like, means that the elements or items preceding the word encompass the elements or items listed after the word and equivalents thereof, but do not exclude other elements or items. “Connected” or “coupled” and like terms are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Up”, “down”, “left”, “right”, etc. are only used to indicate a relative positional relationship, which may change accordingly when the absolute position of the object being described changes.
In the technical solution of semiconductor packaging, it is most common to make a blind Cavity, or a through Cavity, and then to mount a component into the Cavity, and then to perform packaging and building up. In this way, the component is usually placed in the innermost layer, and the discard of the outer layer as useless will directly lead to the loss of the embedded device in the inner layer, especially when the integration degree of the embedded chip is higher and higher, the yield loss of the substrate circuit will increase the cost due to the discard of the embedded component as useless. On the other hand, the manufacturing process of Cavity is complicated, which increases the process cost and processing time of the whole packaging process. Therefore, in the prior art solution, there are problems that the process cost and the processing time are very high, and the circuit of the outer substrate is discarded as useless, resulting in the discard of the component as useless, etc.
Based on this, the embodiments of the present application provide a component package substrate structure and a manufacturing method thereof. By embedding a component after an outer substrate circuit is completed, the component embedding process can be postponed, the conduction between the postponed component and the substrate circuit is achieved by forming a stepped hole, discard of the component as useless due to the poor substrate circuit can be avoided, the component packaging yield can be improved, the component packaging process cost can be reduced to a certain extent and the processing time can be reduced, the component can be embedded after the circuit quality detection of the outer substrate, and the problem of the discard of the component as useless due to the poor substrate circuit can be solved.
As shown in the figure, a component package substrate structure provided by an embodiment of the present application may include a circuit board 100, a second dielectric layer 200, a component 300 and a first dielectric layer 400.
The circuit board 100 includes at least one circuit layer. It is understood that a circuit layer is provided at least on one side surface of the circuit board 100 near the component 300. The specific number of circuit layers can be set according to practical application requirements. For example, the circuit layers may include a first circuit layer 110 and a second circuit layer 120 provided on a side of the circuit board 100 remote from the component 300 (i.e. a lower surface of the circuit board 100) and a side of the circuit board 100 close to the component 300 (i.e. an upper surface of the circuit board 100), respectively. In some embodiments, the circuit layer may also include a third circuit layer 130 provided between the first circuit layer 110 and the second circuit layer 120, as shown in
The second dielectric layer 200 may be provided on a side of the circuit board 100 having a circuit layer (e.g. an upper surface of the circuit board 100). As shown in
The component 300 has a terminal face facing the second dielectric layer 200, and a connection pad 310 connected to the terminal of the component 300 is provided on the terminal face, and as shown in
A first dielectric layer 400 is provided on the second dielectric layer 200, and the first dielectric layer 400 covers the component 300 such that the component 300 is embedded within the first dielectric layer 400. The first dielectric layer 400 has a first via hole 410 (see
The conductive column 500b is formed by filling the stepped hole 530, and the conductive column 500b penetrates at least the second via hole 210 and the opening 312 so that the connection pad 310 can conduct with the circuit layer of the circuit board 100 via the conductive column 500b.
With regard to the component package substrate structure provided in the embodiments of the present application, by providing the connection pad 310 with the annular ring structure 311, in the case where the component 300 is embedded after the circuit board 100 (i.e., the substrate) is completed, the conductive connection pad 310 and the conductive column 500b of the circuit layer can also be formed, so that the embedding process of the component 300 can be postponed, and the cost of the component packaging process and the processing time can be reduced to a certain extent, thus solving the problem of the component being discarded as useless due to the poor circuit of the substrate.
In some embodiments, as shown in
In some embodiments, the conductive column 500b may fill only the opening 312 of the annular ring structure 311 of the second via hole and the connection pad 310, instead of forming the window pad 510 on the first dielectric layer 400, with only the inner line conduction being formed by the conductive column 500b. As shown in
In some embodiments, the thickness of the first dielectric layer 400 may be greater than the thickness of the second dielectric layer 200 to better package the device to perform a “plastically-packaging” function.
The first dielectric layer 400 and/or the second dielectric layer 200 may be a resin film or a liquid packaging material or the like, such as RCC, RCF or ABF or the like.
The conductive column 500b/interlayer conductive column 140 mentioned in this embodiment may include at least one copper through-hole post as an IO channel to achieve conduction between layers, and the size and/or shape of multiple copper through-hole posts may be the same or different; the copper through-hole post can be either a solid copper post or a hollow post electroplated with copper.
It is noted that some embodiments of the present application have been described above. Other embodiments are within the scope of the following claims.
Referring to
The manufacturing method includes the steps of: providing a first temporary bearing plate 600-step (a), as shown in
Next, the component 300 is fitted to the first temporary bearing plate 600-step (b), as shown in
In general, fitting the component 300 on the first temporary bearing plate 600 may specifically include the following sub-steps:
Then, the first dielectric layer 400 and the second temporary bearing plate 700 are laminated on the surface of the component 300-step (c), as shown in
Next, the first temporary bearing plate 600 is removed, exposing the terminal face of the component 300 and the first surface of the first dielectric layer 400-step (d), as shown in
Then, a connection pad 310 connecting terminals of the component 300 is formed on the first surface, and the connection pad 310 has an annular ring structure 311-step (e), as shown in
Next, a circuit board 100 is manufactured-step (f), as shown in
Then, the second dielectric layer 200 and the circuit board 100 are laminated on the first surface; the circuit board 100 includes at least one circuit layer; the second temporary bearing plate 700 is removed to expose a second surface of the first dielectric layer 400 away from the terminal face-step (g), as shown in
In some embodiments, the second temporary bearing plate 700 may be completely removed by simply tearing the first and second copper layers 730 and 720 apart and then etching away the first copper layer 730, taking advantage of the physical bonding properties of the first and second copper layers 730 and 720.
Next, a stepped hole 530 is formed, including a first via hole 410 penetrating the first dielectric layer 400, an opening 312 of the annular ring structure 311, and a second via hole 210 penetrating the second dielectric layer 200-step (h), as shown in
Then, a conductive column 500b for conductively connecting the connection pad 310 of the component 300 with the circuit layer on the surface of the circuit board 100 is formed by filling the stepped hole 530, and the conductive column 500b passes through at least the opening 312 and the second via hole 210 to make the connection pad 310 conductive with the circuit layer-step (i), as shown in
In some embodiments, a substep (i2) of removing the window pad 510 and forming a conductive column 500b through only the second via hole 210 and the opening 312 may also be included, resulting in the structure as shown in
The component package substrate structure and the manufacturing method thereof provided in the embodiments of the present application are as follows: the component 300 is embedded after the circuit board 100 (i.e., a substrate) is completed, and after the embedding process of the component 300 is performed, the component 300 and the substrate circuit are conducted through the stepped hole 530 to avoid the component being discarded as useless due to the failure of the substrate circuit and improve the packaging yield of the component 300. The stepped hole 530 can realize the conduction between the component 300 and the inner layer line and the back side fan-out of the component 300, and has a high degree of freedom in wiring, so that a multi-device package can be achieved and the package integration degree can be improved. The length of the signal circuit can be reduced and the loss of signal transmission process can be reduced by the conductive interconnection via the conductive columns in the stepped hole.
In some cases, the acts or steps recited in the claims may be performed in an order other than that of the embodiments described above and still achieve the desired results. Additionally, the processes depicted in the figures do not necessarily require the particular order or sequential order shown to achieve desired results. Multi-tasking and parallel processing are also possible or may be advantageous in some embodiments.
A person skilled in the art will appreciate that the discussion of any embodiment above is merely exemplary and is not intended to imply that the scope of the present application, including the claims, is limited to these examples; combinations of features in the above embodiments, or between different embodiments, may also be made within the spirit of the present application, the steps may be implemented in any order, and there may be many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for clarity.
In addition, well-known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided figures for simplicity of illustration and discussion, and so as not to obscure the embodiments of the present application. Further, devices may be shown in block diagram form in order to avoid obscuring the embodiments of the present application, and this also takes into account the fact that the details regarding the implementation of such block diagram devices are highly dependent upon the platform on which the embodiments of the present application are to be implemented (i.e. such details should be well understood by a person skilled in the art). Where specific details (e.g. circuits) are set forth in order to describe example embodiments of the present application, it will be apparent to a person skilled in the art that the embodiments of the present application may be practiced without, or with variation of, these specific details. Accordingly, the description is to be regarded as illustrative rather than restrictive.
While the present application has been described in conjunction with specific embodiments thereof, it is evident that many alternatives, modifications, and variations will be apparent to a person skilled in the art in light of the foregoing description. For example, other memory architectures (e.g. dynamic RAM (DRAM)) may use the discussed embodiments.
The embodiments of the present application are intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Therefore, any omissions, modifications, substitutions, improvements and the like that may be made without departing from the spirit or scope of the embodiments of the present application are intended to be included within the scope of the present application.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022115428793 | Dec 2022 | CN | national |
