Data fetch circuit and control method thereof

Abstract

To provide a data fetch circuit, which reliably cuts off transmission of a high impedance state of a data strobe signal even if a manufacture condition or an operation condition is changed, and a control method thereof. The data fetch circuit includes an RL measuring part 10 for measuring a latency measurement value RLB from an input of a read instruction signal RD to a valid edge of a data strobe signal DQS and an RL count comparing part 30 for outputting a BL count start signal BST for giving an instruction of a cancel of the cut-off of the data strobe signal DQS after standing by during the time based on the latency measurement value RLB in accordance with an input of a delay read instruction signal RDD.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the structure of an SDRAM interface circuit according to a first embodiment;

FIG. 2 is a circuit diagram showing a specific example of the SDRAM interface circuit;

FIG. 3 is a circuit diagram showing an example of a transition detecting part;

FIG. 4 is a timing chart showing operation of the SDRAM interface circuit according to the first embodiment;

FIG. 5 is a block diagram showing the structure of an SDRAM interface circuit according to a second embodiment; and

FIG. 6 is a block diagram showing the structure of an SDRAM interface circuit of a prior art.

Claims

1. A data fetch circuit that masks an input of an invalid data strobe signal when it fetches a data signal synchronously with the data strobe signal inputted from the outside with the data signal in accordance with a read instruction signal inputted from the outside, comprising: a response time measuring part for measuring a response time from the input of the read instruction signal to a valid edge of the data strobe signal; anda standby part for giving an instruction of a cancel of the mask of the data strobe signal after standing by during the time based on the response time in accordance with a standby start signal based on the read instruction signal.

2. The data fetch circuit according to claim 1, wherein the data strobe signal makes a transition from a high impedance to a first logic level in accordance with the read instruction signal and thereafter makes a transition to a second logic level through a predetermined time to output the valid edge; and the response time measuring part comprises: a transition detecting part for detecting the transition of the data strobe signal from the high impedance to the first logic level; and a measuring part for measuring a detection time from the input of the read instruction signal to an output of a detection result of the transition detecting part; andthe data fetch circuit further comprises a standby adjusting part for adding the predetermined time to the detection time.

3. The data fetch circuit according to claim 2, wherein the standby adjusting part sets a value in which the predetermined time is added to the detection time as the standby time of the standby part.

4. The data fetch circuit according to claim 2, wherein the standby adjusting part delays the read instruction signal by the predetermined time and inputs the delayed read instruction signal as the standby start signal of the standby part.

5. The data fetch circuit according to claim 2, wherein the transition detecting part comprises: a first comparator in which the strobe input signal is inputted to an inversion input terminal and a first threshold voltage for detecting the first logic level is inputted to a non-inversion input terminal; a second comparator in which an inversion data strobe signal complementary to the data strobe signal is inputted to a non-inversion input terminal and a second threshold voltage for detecting the second logic level is inputted to an inversion input terminal; and a gate circuit that calculate an AND operation of outputs of the first and second comparators.

6. The data fetch circuit according to claim 1, wherein the response time measuring part makes measurement of the response time valid in accordance with a measurement instruction signal inputted from the outside.

7. The data fetch circuit according to claim 1, wherein the response time measuring part comprises: a counter part for starting counting clock signals in accordance with the input of the read instruction signal; and a holding part for holding an output of the counter part in accordance with the valid edge of the data strobe signal.

8. The data fetch circuit according to claim 7, wherein the counter part includes a shift register to which the read instruction signal is inputted as a data input and the clock signal is inputted as a clock input.

9. A control method of a data fetch circuit that masks an input of an invalid data strobe signal when it fetches a data signal synchronously with a data strobe signal inputted from the outside with the data signal in accordance with a read instruction signal inputted from the outside, comprising the steps of: measuring a response time from the input of the read instruction signal to a valid edge of the data strobe signal; andgiving an instruction of a cancel of the mask of the data strobe signal after standing by during the time based on the response time based on the read instruction signal.

10. The control method of a data fetch circuit according to claim 9, wherein the data strobe signal makes a transition from a high impedance to a first logic level in accordance with the read instruction signal and thereafter makes a transition to a second logic level through a predetermined time to output the valid edge; andthe step of measuring the response time comprises the steps of:detecting the transition of the data strobe signal from the high impedance to the first logic level; andmeasuring a detection time from the input of the read instruction signal to an output of a detection result of the step of detecting the transition; andadding the predetermined time to the detection time.

11. The control method of a data fetch circuit according to claim 9, wherein the step of counting the response time further comprises the step of making measurement of the response time valid in accordance with a measurement instruction signal inputted from the outside.

12. The control method of a data fetch circuit according to claim 9, wherein the step of measuring the response time comprises the steps of: starting counting clock signals in accordance with the input of the read instruction signal; and holding a count result of the step of starting the counting in accordance with the valid edge of the data strobe signal.