Definable integrated passives for circuitry

Abstract

A method of fabricating a passive integrated circuit. The integrated circuitry is fabricated in a single plane, the circuitry including passive components such as capacitors, resistors, and inductors. The method features the steps of forming on a substrate a first pattern of conductive material and a first set of passive component elements, and depositing a patterned dielectric layer onto the substrate. The first pattern of conductive material provides electrical connectivity to the first set of passive component elements. An apparatus fabricated according to method is disclosed

Description

BACKGROUND OF THE INVENTION

[0004] 1. Field of the Invention (Technical Field)

[0005] The present invention relates to integrated passive circuitry designs and fabrication thereof.

[0006] 2. Background Art

[0007] Traditional integrated passives are fabricated in a multi-layer construction with each plane serving a single function. Connection of the passives to the surface mounted active components is achieved through circuit patterning and vias that serve as conductive paths between individual layers. Illustrative of the prior art are U.S. Pat. Nos. 5,578,860, 5,818,090, 5,923,077, 5,998,275, and 6,021,050. The present invention provides the capability to form or insert multiple electrically functional components within the same plane.

SUMMARY OF THE INVENTION (DISCLOSURE OF THE INVENTION)

[0008] Thus, there is provided according to the invention a method of forming integrated circuitry in a single plane, the circuitry comprising a plurality of passive components selected from the group consisting of capacitors, resistors, and inductors, the method comprising the steps of forming on a substrate a first pattern of conductive material and a first set of passive component elements, and depositing a patterned dielectric layer onto the substrate, wherein the first pattern of conductive material provides electrical connectivity to the first set of passive component elements. Preferably, in the forming step the substrate comprises alumina. Also, in the forming step the first set of passive component elements optionally comprises interdigitated capacitor electrodes. The method may also comprise the step of forming a floating plane over the dielectric layer. Optionally, in the forming step the first set of passive component elements may comprise a first set of electrodes of a set of parallel plate capacitors.

[0009] The inventive method additionally may also comprise the further step of forming a second pattern of conductive material and a second set of passive component elements wherein the second pattern of conductive material provides electrical connectivity to the second set of passive component elements. The second set of passive component elements preferably comprises a second set of electrodes of a set of parallel plate capacitors paired with the first set of electrodes.

[0010] The inventive method additionally may also comprise the step of forming a second pattern of conductive material and a second set of passive component elements, wherein the second pattern of conductive material provides electrical connectivity to the second set of passive component elements.

[0011] Thus, there also is provided according to the present invention an integrated circuit in a single plane formed by the aforementioned process of the invention. The circuit may comprise a plurality of interdigitated capacitor electrodes.

[0012] Objects, advantages and novel features, and further scope of applicability of the present invention will be set forth in part in the detailed description to follow, taken in conjunction with the accompanying drawings, and in part will become apparent to those skilled in the art upon examination of the following, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings, which are incorporated into and form a part of the specification, illustrate one or more embodiments of the present invention and, together with the description, serve to explain the principles of the invention. The drawings are only for the purpose of illustrating one or more preferred embodiments of the invention and are not to be construed as limiting the invention. In the drawings:

[0014] FIG. 1 is a cross-section view of an interdigitated capacitor apparatus of the invention, formed according to the method of the present invention (arrows indicate electric field vectors);

[0015] FIG. 2 is a cross-section view of an interdigitated capacitor with floating plate formed according to the method of the present invention (arrows indicate electric field vectors); and

[0016] FIG. 3 is a cross-section view of a parallel-plate capacitor formed according to the present invention (arrows indicate electric field vectors).

DESCRIPTION OF THE PREFERRED EMBODIMENTS (BEST MODES FOR CARRYING OUT THE INVENTION)

[0017] The present invention is a novel integrated passive (capacitor, resistor and inductor) design and construction process involving definition of electrically functional materials. The primary advantage of the technology is the capability to form or insert multiple electrically functional components within the same plane. Connection of passive to active components is made using standard circuit patterns. In contrast, traditional integrated passives are fabricated in a multi-layer construction with each plane serving a single function. Connection of the passives to the surface mounted active components is achieved through circuit patterning and vias that serve as conductive paths between individual layers.

[0018] The present invention is illustrated herein for capacitors. As understood by one of ordinary skill in the art, the invention can be appropriately modified for resistors and inductors, through substitutions of component compositions, as generally known in the art. As in conventional designs, the capacitor design of the present invention includes opposing conductive electrodes separated by a dielectric. Distinct from conventional designs, the capacitor design of the present invention includes definition or patterning of the dielectric. The dielectric layer is formed in specific areas on one or both electrode surfaces. In the case of an interdigitated electrode pattern 10, the dielectric 12 is deposited on both electrodes 14,14′ (see FIG. 1) on a substrate 16 (e.g., alumina). A floating plate electrode 18 can be added, which increases the electric field and capacitance (see FIG. 2). In the case of a parallel plate electrode pattern, the dielectric is placed between two parallel plate electrodes 20,20′ (see FIG. 3).

[0019] The preferred process sequence for fabrication of a parallel plate capacitor incorporating the integrated passive design of the present invention is described below. Similar processes are used for resistors and inductors.

[0020] 1. A bottom electrode pattern is formed on an electrical substrate, e.g., alumina, using conventional plating, photoresist and/or etching processes.

[0021] 2. A photo or ultraviolet sensitive dielectric layer is coated onto the entire substrate using conventional film forming processes such as spin or dip coating.

[0022] 3. The dielectric layer is preferentially exposed to ultraviolet radiation to induce curing or polymerization of the dielectric coating.

[0023] 4. The unexposed dielectric coating is removed from the electrical substrate through solvent washing. (Specific areas of the dielectric coating remain over the bottom electrode pattern.)

[0024] 5. A top electrode patterned is formed above the bottom electrode pattern on top of the dielectric coating.

[0025] 6. Connection to the top and bottom capacitor planes is made through circuit patterns formed with the bottom and top electrodes.

[0026] Note that definition of the electrically functional materials is not limited to photo patterning. Physical masking or other processes can also be used for preferential deposition.

[0027] Although the invention has been described in detail with particular reference to these preferred embodiments, other embodiments can achieve the same results. Variations and modifications of the present invention will be obvious to those skilled in the art and it is intended to cover in the appended claims all such modifications and equivalents. The entire disclosures of all references, applications, patents, and publications cited above are hereby incorporated by reference.

Claims

1. A method of forming integrated circuitry in a single plane, the circuitry comprising a plurality of passive components selected from the group consisting of capacitors, resistors, and inductors, the method comprising the steps of: forming on a substrate a first pattern of conductive material and a first set of passive component elements; and depositing a patterned dielectric layer onto the substrate; wherein the first pattern of conductive material provides electrical connectivity to the first set of passive component elements.

2. The method of claim 1 wherein in the forming step the substrate comprises alumina.

3. The method of claim 1 wherein in the forming step the first set of passive component elements comprises interdigitated capacitor electrodes.

4. The method of claim 3 additionally comprising the step of forming a floating plane over the dielectric layer.

5. The method of claim 1 wherein in the forming step the first set of passive component elements comprises a first set of electrodes of a set of parallel plate capacitors.

6. The method of claim 5 additionally comprising the step of forming a second pattern of conductive material and a second set of passive component elements wherein the second pattern of conductive material provides electrical connectivity to the second set of passive component elements.

7. The method of claim 6 wherein the second set of passive component elements comprises a second set of electrodes of a set of parallel plate capacitors paired with the first set of electrodes.

8. The method of claim 1 additionally comprising the step of forming a second pattern of conductive material and a second set of passive component elements wherein the second pattern of conductive material provides electrical connectivity to the second set of passive component elements.

9. An integrated circuit in a single plane formed by the process of claim 1.

10. The circuit of claim 9 comprising a plurality of interdigitated capacitor electrodes.