Patent Application
20250132223
Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon.
The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. In some device, multiple dies are stacked vertically to reduce the footprint of a device package and permit dies with different processing technologies to be interconnected. As the sizes of active devices on a die shrink, the heat dissipation for the increasingly compact active devices is managed by attaching a lid over the stacked dies. The lid protects the dies and provides a path to conduct heat away from the dies.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. As used herein, “directly over” refers to a vertical alignment of features such that when an overlying feature that is directly over an underlying feature, a vertical axis passes through both features.
On the over hand, “above” refers to a relative height of two features, such that when an upper feature is above a lower feature, the upper feature is at a greater relative height than the lower feature. An upper feature above a lower feature may be or may not be directly over the lower feature. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “directly over”, “over”, “overlying”, “above”, “upper”, “top”, “under”, “underlying”, “beneath”, “below”, “lower”, “bottom”, “side”, “positive slope” and “negative slope” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
All numbers in this description indicating amounts, ratios of materials, physical properties of materials, and/or use are to be understood as modified by the word “about,” except as otherwise explicitly indicated. When modifying a numerical value in the specification or claims, “about” denotes an interval of accuracy, familiar and acceptable to a person skilled in the art. In general, such interval of accuracy is ±ten percent. Thus, “about ten” means nine to eleven.
Unless otherwise identified, in certain embodiments herein, a “material layer” is a layer that includes at least 50 wt. % of the identified material, for example at least 60 wt. % of the identified material, or at least 75 wt. % of the identified material, or at least 90 wt. % of the identified material; and a layer that is a “material” includes at least 50 wt. % of the identified material, for example at least 60 wt. % of the identified material, at least 75 wt. % of the identified material, at least 90 wt. % of the identified material, or at least 99 wt. % of the identified material. For example, certain embodiments, each of a titanium nitride layer and a layer that is titanium nitride is a layer that is at least 50 wt. %, at least 60 wt. %, at least 75 wt. %, titanium nitride, at least 90 wt. %, titanium nitride, or at least 99 wt. % titanium nitride.
For the sake of brevity, well-known techniques related to semiconductor device fabrication may not be described in detail herein. Moreover, the various tasks and processes described herein may be incorporated into a more comprehensive procedure or process having additional functionality not described in detail herein. In particular, various processes in the fabrication of semiconductor devices are well-known and so, in the interest of brevity, many processes will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details. As will be readily apparent to those skilled in the art upon a complete reading of the disclosure, the structures disclosed herein may be employed with a variety of technologies, and may be incorporated into a variety of semiconductor devices and products. Further, it is noted that semiconductor device structures include a varying number of components and that single components shown in the illustrations may be representative of multiple components.
Embodiments will be described with respect to a specific context, bonding lids, heat sinks covers, casing or the like to wafers, dies, substrates or other structures. Other embodiments may also be applied, however, to the bonding of substrates, packages, structures or devices or combinations of any type of integrated circuit device or component.
Cooling devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed in the present disclosure. The cooling devices are implementable in portable electronic equipment, such as cellular phones, smart phones, tablets, notebooks, and other applications. The cooling devices are implementable on packaged semiconductor devices that may comprise one substrate attached to another substrate, wherein each substrate may be a die, wafer, printed circuit board, packaging substrate, or the like. The cooling devices thereby allow for cooling of die-to-die, wafer-to-die, wafer-to-wafer, die or wafer to printed circuit board or packaging substrate types of packaging, or the like.
Embodiment herein may enhance TIM coverage and reduce TIM stress. Further, embodiments herein may provide a low stress trench and composite design for trench and dam to reduce metal TIM stress and enhance TIM coverage. Embodiments may be provided for use in High-Performance Computing (HPC) packages.
The embodiments of the present disclosure are described with reference to
Described herein are embodiments in which processing of the TIM is improved. For example, a metal TIM may melt during thermal annealing. Herein, structures and features provide for directing flow of melted TIM portions to desired locations or in desired directions and limiting flow of melted TIM portions to undesired locations or in undesired directions. For example, embodiments herein may provide a trench in the underside of the lid. The trench provides an open space or region to receive flow of melted TIM portions in a vertical direction and to reduce stress on the TIM. In some embodiments, the lid is provided with downward-extending protrusions that surround the TIM in a longitudinal direction and block or inhibit flow of melted portions of the TIM in the longitudinal direction. In some embodiments, a dam structure or structures surround the TIM in a lateral direction and block or inhibit flow of melted portions of the TIM in the lateral direction.
As shown, TIM 200 lies over a substrate 300 having a topside 301 and a periphery 310. As further shown, an adhesive 350 is disposed on the topside 301 of the substrate 300 along the periphery 310.
In
The base portion 404 of the first portion 411 of the dam structure 400 lies adjacent to the first end 211 of TIM 200 continuously from the first edge 221 to the second edge 222. The base portion 404 of the second portion 412 of the dam structure 400 lies adjacent to the second end 212 of TIM 200 continuously from the first edge 221 to the second edge 222.
A first gap 431 in the dam structure 400 is defined between the first end 401 of the first portion 411 and the first end 401 of the second portion 412. A second gap 432 in the dam structure 400 is defined between the second end 402 of the first portion 411 and the second end 402 of the second portion 412.
As shown, the device structure 100 may be a packaged semiconductor device. For example, the packaged semiconductor device 100 includes an integrated circuit die 110 that has been packaged. In some embodiments, the die 110 may be a system-on-chip (SOC) or include one or more dies, such as one or more systems-on-chips.
The packaged semiconductor device 100 includes an interconnect structure 112 coupled to the integrated circuit die 110, and a molding material 114 disposed around the integrated circuit die 110 and over the interconnect structure 112. The packaged semiconductor device 100 comprises fan-out structures in some embodiments. For example, conductive wiring of the interconnect structure 112 may be spaced apart farther than conductive wiring of the integrated circuit die 110 is spaced. Likewise, the footprint of contact pads of the interconnect structure 112 may be larger than the footprint of contacts (not shown) of the integrated circuit die 110. The packaged semiconductor device 100 comprises an integrated fan-out (InFO) device or a WLP device in some embodiments. The packaged semiconductor device 100 may also comprise other types of packages.
The integrated circuit die 110 may comprise a substrate having electrical circuitry formed within or thereon. The substrate may comprise, for example, doped or undoped bulk silicon or an active layer of a semiconductor-on-insulator (SOI) substrate. The electrical circuitry of the substrate of the integrated circuit die 110 may be any type of circuitry suitable for a particular application. The integrated circuit die 110 may comprise a logic, memory, processor, or other type of device. As other examples, electrical circuitry formed within or on the substrate of the integrated circuit die 110 may include various N-type metal-oxide semiconductor (NMOS) and/or P-type metal-oxide semiconductor (PMOS) devices, such as transistors, capacitors, resistors, diodes, photo-diodes, fuses, and the like, that are interconnected to perform one or more functions. The functions may include memory structures, logic structures, processing structures, sensors, amplifiers, power distribution, input/output circuitry, and/or the like. One of ordinary skill in the art will appreciate that the above examples are provided for illustrative purposes to further explain applications of some illustrative embodiments and are not meant to limit the disclosure in any manner. Other circuitry may be used as appropriate for a given application. The integrated circuit die 110 typically has been fabricated by forming a plurality of the integrated circuit dies 110 on a semiconductor wafer, and singulating the individual integrated circuit dies 110 along scribe lines.
A packaging process for the integrated circuit die 110 in some embodiments comprises providing a carrier (not shown), and attaching the integrated circuit die 110 to the carrier. The carrier may comprise a wafer, tape, or other type of support, substrate, or device that may be used for the packaging process as a platform for packaging one or more integrated circuit dies 110. The carrier is later removed after packaging a plurality of the integrated circuit dies 110 in some embodiments, for example.
In some embodiments, through-vias (not shown in
A plurality of the integrated circuit dies 110 is coupled to the carrier between some of the plurality of through-vias in some embodiments. The plurality of integrated circuit dies 110 is coupled to the carrier using a die attach film (DAF) (not shown) disposed on a bottom surface of the integrated circuit dies 110. The plurality of integrated circuit dies 110 may be placed on the carrier using a pick-and-place machine or manually, for example. In some embodiments, a plurality of the integrated circuit dies 110 is coupled to the carrier and is packaged simultaneously. The integrated circuit die 110 or two or more integrated circuit dies 110 are later singulated along scribe lines (i.e., of the package or interconnect structure 112) to form a plurality of packaged semiconductor devices 100.
The molding material 114 is then formed over the carrier, over the integrated circuit die 110 and the through-vias, in embodiments wherein the through-vias are included. The molding material 114 may comprise a molding compound comprised of an insulating material, such as an epoxy, a filler material, a stress release agent (SRA), an adhesion promoter, other materials, or combinations thereof, as examples. The molding material 114 may comprise a liquid or gel when applied so that it flows between a plurality of integrated circuit dies 110 being simultaneously packaged and around the through-vias, in some embodiments. The molding material 114 is then cured or allowed to dry so that it forms into a solid. A molding compound clamp may be applied during a curing process and a plasma treatment process of the molding material 114 in some embodiments. In some embodiments, as deposited, the molding material 114 extends over top surfaces of the plurality of integrated circuit dies 110 and the through-vias, and after the molding material 114 is applied, a top portion of the molding material 114 is removed using a planarization process, such as a chemical mechanical polish (CMP) process, a grinding process, an etch process, or combinations thereof, as examples. Other methods may also be used to planarize the molding material 114. A top portion of the integrated circuit dies 110 and/or through-vias may also be removed during the planarization process for the molding material 114. In some embodiments, an amount of the molding material 114 applied may be controlled so that top surfaces of the integrated circuit die 110 and through-vias are exposed. Other methods may also be used to form the molding material 114.
The interconnect structure 112 may then be formed over the planarized molding material 114, the integrated circuit dies 110, and the through-vias. The interconnect structure 112 comprises an RDL or PPI in some embodiments. The interconnect structure 112 may include one, two, or several conductive line layers and via layers. Some of the conductive lines of the interconnect structure 112 are coupled to contact pads (not shown) of the integrated circuit die 110. The conductive features or wiring of the interconnect structure may comprise copper, a copper alloy, or other metals formed by plating processes, lithography processes, and/or other methods formed within one or more insulating material layers, in some embodiments.
The carrier wafer is then removed. In some embodiments, a plurality of the packaged semiconductor devices 100 is then singulated to form the packaged semiconductor device 100 shown in
In some embodiments, the interconnect structure 112 comprises a first interconnect structure formed on a first side of the integrated circuit die 110, and a second interconnect structure (not shown) is formed in addition to the first interconnect structure 112 on a second side of the integrated circuit die 110, the second side being opposite the first side, before singulating a plurality of the packaged semiconductor devices 100. For example, the previously described carrier may comprise a first carrier, and after the formation of the first interconnect structure 112, a second carrier may be attached to the first interconnect structure. The first carrier is removed, and the second interconnect structure is formed over the second side of the integrated circuit die 110, the through-vias, and the molding material 114. The second carrier is then removed, and the packaged semiconductor devices 100 are then singulated. The first interconnect structure 112 and the second interconnect structure may provide electrical connections in a horizontal direction for a plurality of packaged semiconductor devices 100 in some embodiments, for example. The second interconnect structure may comprise back-side routing, and the first interconnect structure 112 comprises front-side routing, or vice versa, e.g., relative to the integrated circuit die 110, for the packaged semiconductor devices 100 in some embodiments.
The methods of packaging semiconductor devices using one or more carriers described herein is merely an example: the integrated circuit dies 110 may be packaged using different methods or orders of methods of a packaging process.
In some embodiments, the packaged semiconductor device 100 is coupled to a substrate or printed circuit board (PCB) 300 by a plurality of connectors 104, as shown in
In some embodiments, the interconnect structure 112 of the packaged semiconductor device 100 is coupled to the substrate or PCB 300 using the plurality of connectors 104, as illustrated in
An underfill material 106 may be applied between the connectors 104 and between the interconnect structure 112 and the substrate or PCB 300. The underfill material 106 may comprise a similar material as described for the molding material 114, for example. The underfill material 106 may be dispensed along one or more sides of the interconnect structure 112 along edge connectors 104, for example, and the underfill material 106 flows beneath the packaged semiconductor device 100 to the other side(s). The underfill material 106 is then cured or allowed to cure. In some embodiments, the underfill material 106 is not included.
In
As shown in
The TIM 200 may comprise a thickness of about 20 μm to about 150 μm, as examples. The TIM 200 may also comprise other materials and dimensions. The TIM 200 may be applied by dispensing the TIM 200 onto the top surface of the integrated circuit die 110 and molding material 114. The dispensing process may be conducted using automatic dispenser equipment which may control the TIM 200 dispensing volume and patterns, such as serpentine, spiral, or other patterns, in order to achieve full coverage and a desired TIM 200 bond line thickness. The TIM 200 may also be applied using other methods.
As further shown in
As shown, the lid 500 has a central portion 530 and includes a periphery 510 with an annular footing 520 that extends vertically downward, i.e., in the Z-direction, from the central portion 530 to a bottom edge 521. The bottom edge 521 of the footing 520 is contacted to and adhered to adhesive 350. The footing 520 defines an interior volume 525 enclosed by the lid 500. As shown, the die 110 and TIM 200 are received in the interior volume 525.
As further shown in
In some embodiments, the underside 539 of the central portion 530 of the lid 500 is formed with a trench 580. Further, an insert 590 is located in, and only partially fills the trench 580. In some embodiments, the insert 590 is a polymer material. For example, the insert 590 may be a polymer TIM.
In
In some embodiments, a ratio of the lateral distance W4 to the lateral underfill width W2 (W4/W2) is less than or equal to 1.
In some embodiments, a ratio of the lateral dam width W3 to the lateral distance W4 (W3/W4) is less than or equal to 1.
The cross-sectional view of
In some embodiments, each dam portion 411, 412 is formed by a polymer TIM.
The connectors 104, underfill material 106, interconnect structure 112, integrated circuit die 110 may be collectively referred to as a workpiece 101 that is located over the substrate 300.
As shown, the trench 580 includes an upper portion 581 and a lower portion 582. The upper portion 581 extends vertically downward, in the Z-direction, from an upper trench surface 589 along substantially planar sidewalls 583. The lower portion 582 includes arcuate sidewalls 584. For example, each arcuate sidewall 584 may be formed with a radius R1. In some embodiments, radius R1 may be from 0.025 to 0.6 mm.
Further, the sidewalls 583 in the upper portion 581 of the trench 580 may be laterally distanced from one another by a distance W5 in the X-direction. A vertical centerline 585 is defined as being equidistant between the sidewalls 583.
The upper trench surface 589 may be located at a vertical distance H2 in the Z-direction from the top surface 538. In other words, the lid 500 has a vertical thickness H2 over the trench 580. The vertical thickness H2 is greater than zero and is less than that vertical thickness H1.
As shown in
The trench 580 has a total depth equal to the sum of H3 and H4, i.e., the vertical distance from the upper trench surface 589 to the underside 539. In embodiments, H3+H4 is less than H1.
A width W7 may include the inter-die portion of the molding material 114 and the scribe line and/or embedded seal ring 118 of each die 110.
In the illustrated embodiment, trench 580 may be located directly over the die-to-die gap 113. In some embodiments the lateral distance, in the X-direction, between the centerline 585 of the trench 580 and the centerline 115 of the die-to-die gap 113 is from zero to 0.5 mm.
In some embodiments, the lateral distance W6 of the die-to-die gap 113 is less than the trench width W5. In some embodiments, the trench width W5 is less than or equal to the width W7.
Further, the protrusion 600, specifically protrusion 602, extends vertically downward in the Z-direction from the underside 531 of the lid 500 into the gap 432. The protrusion 600 terminates at a lowest surface 699. As shown, the protrusion 600 has a lateral width W9 in the X-direction from first end 641 to second end 642.
Cross-referencing
In
The cross-sectional view of
A vertical distance H5 in the Z-direction is defined between the lowest surface 699 of the protrusion 600 and the uppermost surface 698 of the underfill material 106.
Further, the protrusion 600 has a vertical length H6 in the Z-direction from the underside 531 to the lowest surface 699.
As shown, the footing 520 extends vertically downward in the Z-direction for a vertical distance H7 from the underside 531 to bottom edge 521. The bottom edge 521 of the footing 520 is contacted to and adhered to adhesive 350. Cross-referencing
In some embodiments, the vertical protrusion length H6 is greater than zero and less than the vertical footing length H7.
In some embodiments, vertical distance H5 is greater than zero and less than the vertical footing length H7.
As shown, each protrusion 601, 602 extends downward from the underside 531 to lowest surface 699. Lowest surface 699 is at a vertical distance H8 in the Z-direction from the topside 301 of the substrate 300.
In some embodiments, vertical distance H8 is greater than zero and less than the vertical footing length H7.
Each protrusion 601, 602 has a longitudinal length L2 in the Y-direction from first or outer edge 651 to second or inner edge 652. Longitudinal length L2 is greater than zero. Further, the inner edge 652 of each protrusion 601, 602 is distanced from a respective edge 221, 222 of TIM 200 by a longitudinal distance L3 in the Y-direction.
In some embodiments, the ratio of longitudinal distance L3 to lateral underfill width W2 (L3/W2) is less than or equal to 1.
Further, during the thermal anneal process, all or of portions of TIM 200 may melt. As shown, a vertically-extending portion 299 of TIM 200 may flow into the trench 580 while a base portion 298 of the TIM 200 remains outside the trench 580. At the same time, the dam structure 400 prevents flow of melted portions of TIM 200 laterally in the X-direction.
As described herein, embodiments provide for lids such as cooling structures that mitigate stress on underlying structures during thermal anneal processes. Further, such lids may include locations, such as trenches, that provide open space to receive flow of melted material, such as in a vertical direction. As a result, flow of melted material may be redirected away from non-desired directions. Also, such lids may be provided with downward-extending protrusions that limit the flow of melted material in longitudinal directions. Also, embodiments herein provide non-metal, such as polymeric TIM, dam structures that limit the flow of melted material in lateral directions.
In one embodiment, a device includes a workpiece; a thermal interface material (TIM) disposed over the workpiece; and a lid disposed over the workpiece, wherein the lid has an underside formed with a trench, and wherein a vertically extending portion of the TIM extends into the trench and a base portion of the TIM is located outside of the trench.
In some embodiments of the device, the TIM extends longitudinally from a first edge to a second edge; the lid includes a first protrusion extending downward the underside of the lid, wherein the first protrusion is longitudinally adjacent to the first edge; and the lid includes a second protrusion extending downward from the underside of the lid, wherein the second protrusion is longitudinally adjacent to the second edge.
In some embodiments of the device, the TIM extends laterally from a first end to a second end; and the device further includes a first portion of a dam structure laterally adjacent to the first end of the TIM and a second portion of a dam structure laterally adjacent to the second end of the TIM.
In some embodiments of the device, a first gap is located between the first portion and the second portion of the dam structure adjacent to the first edge of the TIM; a second gap is located between the first portion and the second portion of the dam structure adjacent to the second edge of the TIM; the first protrusion extends downward into the first gap; and the second protrusion extends downward into the second gap.
In some embodiments of the device, the TIM is metal and the dam structure is a polymer.
In some embodiments, the workpiece is an integrated circuit die.
In another embodiment, a device includes a system-on-chip (SOC); a substrate, wherein the SOC is mounted to the substrate; a lid disposed over the SOC; a thermal interface material (TIM) disposed between the SOC and the lid, wherein the TIM extends laterally from a first end to a second end; and a dam structure laterally adjacent to the first end of the TIM and to the second end of the TIM.
In some embodiments of the device, the lid has an underside; the substrate has a topside; and the dam structure extends vertically from the topside of the substrate to the underside of the lid.
In some embodiments of the device, the TIM is metal.
In some embodiments of the device, the dam structure is a polymer.
In some embodiments of the device, the TIM extends longitudinally from a first edge to a second edge; the dam structure includes a first portion laterally adjacent to the first end of the TIM; the dam structure includes a second portion laterally adjacent to the second end of the TIM; a first gap is located between the first portion and the second portion of the dam structure adjacent to the first edge of the TIM; a second gap is located between the first portion and the second portion of the dam structure adjacent to the second edge of the TIM; the lid includes a first protrusion extending downward into the first gap from an underside of the lid; and the lid includes a second protrusion extending downward into the second gap from the underside of the lid.
In some embodiments of the device, the lid has an underside; a trench is formed in the underside of the lid over the workpiece; and a vertically extending portion of the TIM extends into the trench.
In some embodiments of the device, a polymer insert material is located in the trench over the vertically extending portion.
In some embodiments of the device, the TIM directly contacts the SOC and an underside of the lid.
In another embodiment, a method includes locating a workpiece over a package carrier; disposing a thermal interface material (TIM) over the workpiece; positioning a lid over the workpiece, wherein the lid has an underside formed with a trench, and wherein the lid has an annular footing; adhering the footing to the package carrier; and performing a thermal anneal process, wherein during the thermal anneal process a portion of the TIM melts and flows into the trench.
In some embodiments of the method, after disposing the TIM over the workpiece, the TIM extends longitudinally from a first edge to a second edge; the lid includes a first protrusion and a second protrusion extending downward the underside of the lid; after adhering the footing to the package carrier, the first protrusion is longitudinally adjacent to the first edge and the second protrusion is longitudinally adjacent to the second edge; and during the thermal anneal process, the first protrusion and the second protrusion block longitudinal flow of melted portions of the TIM.
In some embodiments, the method further includes applying a vacuum to draw bubbles out of the TIM during the thermal anneal process.
In some embodiments of the method, after disposing the TIM over the workpiece, the TIM extends laterally from a first end to a second end; the method further includes forming a dam structure over the package carrier; after disposing the TIM over the workpiece, the dam structure is laterally adjacent to the first end of the TIM and to the second end of the TIM; and during the thermal anneal process, the dam structure blocks lateral flow of melted portions of the TIM.
In some embodiments, the method further includes, before positioning the lid over the workpiece, partially filling the trench with a polymer insert.
In some embodiments of the method, the workpiece includes a first system-on-chip (SOC) and a second system-on-chip (SOC) separated by a gap; and positioning the lid over the workpiece includes positioning the trench directly over the gap.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
