BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross-section of a known insulated metal substrate (IMS).
FIG. 2 shows the IMS of FIG. 1 before the application of the top copper layer, with the structure in the form of “B-stage IMS.”
FIG. 3 shows a schematic cross-section of a die-on-leadframe assembly.
FIG. 4 shows the combination of a die on leadframe sub-assembly fixed to a B-stage IMS in accordance with one embodiment of the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
FIG. 1 shows a typical IMS substrate 10 which consists of a planar metal base plate 11 which may be of copper or aluminum of thickness of typically 0.5 to 3.0 mm. An electrically insulative but thermally conductive, curable dielectric material 12 is fixed or applied to the top of base plate 11 and has a thickness, typically of 100 to 250 μm. A conductive copper layer 13 which has a thickness up to about 300 μm is fixed to the curable layer 12. The curable layer 12 is cured to fix layer 13 to base plate 11 by the application of suitable temperatures and/or pressures. Such products are commercially available, one source being the DENKA Corporation.
This product permits the controlled patterning of copper layer 13 to create insulated semiconductor die pads and interconnecting circuit pathways to form electrical circuits with such semiconductor die and with passive electrical components which may also be mounted on the IMS substrate. Further, there is excellent heat transfer through insulation coating 12 to base plate 11 and cured dielectric 12 provides good high voltage electrical isolation between the patterned copper layer 13 and the baseplate 11. However, as stated previously, the copper layer 13 is very thin (up to 300 μm), and the thickness of the IMS layers of FIG. 1 have to be tailor-made to the particular application of the structure.
The IMS substrate of FIG. 1 is also has a so-called B-stage IMS 20 state before layer 13 is applied, as shown in FIG. 2, consisting of the baseplate 11 and the dielectric layer 12 (uncured). As will be later seen, a die on leadframe subassembly can have its bottom leadframe surface bonded to baseplate 11 (in place of layer 13 of FIG. 1) by curing film 12 of the B-stage IMS 20.
FIG. 3 schematically shows a typical die on leadframe (DOL) subassembly 29 of the type shown in U.S. Pat. No. 6,703,703. Thus, a flat, relatively thick copper sheet or other metal leadframe 30 is stamped and patterned to have, for example, die receiving pads 31, 32, 33, 34. Portions of the leadframe may be upwardly turned to provide assembly terminals 35, 36, 37, 38, for example. Semiconductor die 41, 42, 43 and 44 are mounted on and soldered to pads 31 to 34 respectively. A conductive adhesive could also be used. Die 31 to 34 may be MOSgated devices such as MOSFETs, IGBTs and the like or other semiconductor die. Further, other pads or areas, not shown, may carry diodes or passive components needed to form the desired circuit to be contained in the DOL subassembly 29.
An insulation frame 50 which may be an insulation plastic or ceramic or any other insulation material then is fixed as shown around the leadframe body.
In use, the subassembly 29 is mounted on a suitable mount at the bottom surface of leadframe 3, but must be electrically insulated from such a mount if it is conductive. This is frequently difficult and can reduce the efficiency of the DOL circuits in such an application. Further, it would be difficult to use fluid cooling with such an assembly.
FIG. 4 shows a preferred embodiment of the invention in which a DOL assembly 60, which is similar to DOL assembly 29, and in which similar components have the same reference number, has the bottom of leadframe 30 fixed to base plate 11 by the curing of dielectric layer 12 by the use of the conventional temperature and/or pressure process used to secure copper layer 13 to the base plate 11 in FIG. 1.
In another embodiment of the invention, the B-stage IMS can be replaced by a metal base plate having a curable epoxy layer on its top surface. The epoxy will preferable be filled with small ceramic spheres to permit the bottom of leadframe to be spaced by a gap of predetermined thickness, for example, 100 to 250 μm. Alternatively, the techniques disclosed in copending application Ser. No. 11/619,742, filed Jan. 4, 2007, entitled SUBSTRATE AND METHOD FOR MOUNTING SILICON DEVICE in the name of Henning Hauenstein (IR-3178), the full contents of which are incorporated herein by reference, may be used.
In still another embodiment of the invention, the die 41, 44 and the wire bonds for their interconnection may be made after the patterned leadframe is secured to the base plate 11 through the B-stage dielectric 12 or another thin epoxy coating.
The novel structure of FIG. 4 and its alternatives above has the following benefits:
a) Improved electrical and thermal properties:
- i) Optimized heat-spreading out of the die 41, 44 into the thick leadframe 30 before the heat wave enters the less thermally conductive adhesive 12.
- ii) High Voltage Electric isolation (well defined over isolation layer 12 thickness).
- iii) Optimization between electric isolation (a thicker layer 12) and thermal resistance (a thinner layer 12) can be selected according to application needs.
- iv) Mountability on a heat-sink (even liquid/active cooled) provides further cooling power.
- v) Increased current/power capability due to low thermal resistance.
b) Improved manufacturing and handling properties:
- i) Leadframe 30 can be customized and changed independently from the B-stage IMS 20 which can be produced as a standard/platform part in large volume;
- ii) Die 41, 44 are more easily soldered to the leadframe before mounting the leadframe 30 on the B-stage IMS 20 and the leadframe doesn't need to be moved through the module manufacturing line. That is, e.g. soldering of the die to the pure leadframe 30 is easier then heating up a complete isolated substrate 11 with isolation layer 12 since the bottom part of the pure leadframe 30 has less heat capacity and a better thermal contact to the solder oven.
- iii) The DOL modules 29 or 60 are fully tested prior to mounting on a B-stage IMS plate 20.
c) Low manufacturing and test costs due to:
- i) Cost effective large volume production of B-stage IMS 20 is possible since no customization is necessary on this element. Customization is done on the leadframe 29, 60 only, which will be attached to the B-stage IMS 20.
- ii) Design and layout changes only have an influence on the leadframe 30 and not on the B-stage IMS part 20.
- iii) Since the DOL module 29, 60 is a fully tested part prior the mounting to IMS 20, a high end of line yield can be achieved.
- iv) Cost optimized module can be produced with the electric isolation as an option. Thus, standard modules can be developed which can be equipped with the electric isolation (B-stage IMS) after finishing the electric assembly leading to volume bundling, manufacturing standardization and production line sharing (reduced tooling and equipment costs).
Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein.
Patent Application
20070257343
