Claims
- 1. A method for forming a dimensionally stable core for a chip package, said method comprising the steps of:
a) forming a metal core with clearances therein; b) placing a dielectric layer concurrently on top and bottom surfaces of the metal core, said dielectric layer having top and bottom surfaces, respectively; and c) placing a metal cap layer concurrently on the top surface of a top dielectric layer and the bottom surface of a bottom dielectric layer.
- 2. The method according to claim 1, further comprising the steps of:
d) laminating the metal core, the dielectric layers and the metal cap layer on each side of the metal core.
- 3. The method according to claim 1, further comprising the steps of:
e) drilling vias through the dielectric layer the metal cap layer and the metal core.
- 4. The method according to claim 1, further comprising the steps of:
f) metallizing the vias by forming a metal layer on the sides of the vias and extending onto the metal cap layer and the dielectric layer.
- 5. The method according to claim 1, further comprising the steps of:
g) repeating steps b) through f) from 2 to 100 times.
- 6. A method according to claim 1, wherein in the metal core is copper.
- 7. A method according to claim 1, wherein the metal cap layer is a copper cap layer.
- 8. A method according to claim 1, wherein in said step b) the dielectric is a thermosetting prepreg.
- 9. A method according to claim 8, wherein the thermosetting prepreg is a non-woven material containing a cyanate ester resin in a polytetrafluoroethylene matrix.
- 10. A method according to claim 9, wherein in said step b) the dielectric layer is a sheet having a sufficient thickness to completely fill the clearances in the copper core.
- 11. A method according to claim 5, wherein said laminating step d) comprises the steps of:
i) applying pressure to the dielectric and metal cap layers at approximately 300-350 psi; ii) applying temperature at a ramp rate of 5-7° C. per minute until reaching a temperature of 177° C.; iii) holding the temperature of 177° C. for approximately 30 minutes; iv) raising the temperature to 220° C.-225° C. and holding at this temperature for approximately 60 minutes; and v) slowly cooling the chip package while maintaining the pressure.
- 12. A method according to claim 11, wherein said step e) comprises drilling through vias and blind vias.
- 13. A method according to claim 12, wherein in said step e), the vias are drilled using a laser.
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a divisional of application Ser. No. 08/747,169 filed Nov. 8, 1996.
Divisions (1)
|
Number |
Date |
Country |
Parent |
08747169 |
Nov 1996 |
US |
Child |
09136201 |
Aug 1998 |
US |