Claims
- 1. A method of forming dielectric material for conductive lines of an integrated circuit, the method comprising:
forming a first lower, organic resist layer above a substrate; forming a first upper, silicon-containing resist layer above the first lower layer, wherein the first lower layer and the first upper layer correspond to a first layered resist; patterning the first upper layer using a first etchant selective to the first upper layer with respect to the first lower layer to thereby form a patterned first upper layer; patterning the first lower layer using the patterned first upper layer as a hard mask using a second etchant selective to the first lower layer with respect to the first upper layer; forming a second lower, organic resist layer above the first upper, silicon-containing resist layer; forming a second upper, silicon-containing resist layer above the second lower layer, wherein the second lower layer and the second upper layer correspond to a second layered resist; patterning the second upper layer using the first etchant selective to the second upper layer with respect to the second lower layer to thereby form a patterned second upper layer; and patterning the second lower layer using the patterned second upper layer as a hard mask using the second etchant selective to the second lower layer with respect to the second upper layer.
- 2. The method according to claim 1, further comprising:
removing the second upper layer.
- 3. The method according to claim 2, wherein the second upper layer is removed by a stripping process.
- 4. The method according to claim 2, wherein the second upper layer is removed by a polishing process.
- 5. The method according to claim 1, further comprising:
wherein the patterning the first upper layer and the first lower layer steps forms an aperture for a via.
- 6. The method according to claim 5, wherein the patterning the second upper layer and the patterning the second lower layer step form an aperture for a conductive line.
- 7. A method of forming dielectric material for conductive lines of an integrated circuit, the method comprising:
depositing a first layered photoresist above a substrate, the first layered photoresist including a first lower layer and a first upper layer; patterning the first upper layer to thereby form a patterned first upper layer; patterning the first lower layer using the patterned first upper layer as a hard mask; depositing a second layered photoresist above the first layer photoresist, the second layered photoresist including a second lower layer and a second upper layer; patterning the second upper layer using the first etchant selective to the second upper layer with respect to the second lower layer to thereby form a patterned second upper layer; and patterning the second lower layer using the patterned second upper layer as a hard mask.
- 8. The method according to claim 7, further comprising:
removing the first upper layer.
- 9. The method according to claim 8, wherein the upper layer is removed by a stripping process.
- 10. The method according to claim 8, wherein the upper layer is removed by a polishing process.
- 11. The method according to claim 7, further comprising:
forming a first conductive layer beneath the first lower layer; and wherein the patterning of the first lower layer comprises forming at least one via.
- 12. The method according to claim 11, wherein the patterning the second lower layer comprises:
forming at least one trench for a conductive line.
- 13. An integrated circuit, comprising:
an interconnect structure including a first surface and a second surface, the interconnect structure including a first dielectric layer and a second dielectric layer, wherein the first dielectric layer is at least part of a first layered photoresist and the second dielectric layer is at least part of a second layered photoresist.
- 14. The integrated circuit of claim 13, wherein the interconnect structure includes a thin oxide-containing layer between the first dielectric layer and the second dielectric layer.
- 15. The integrated circuit of claim 14, wherein the oxide-containing layer is an imaging layer containing silicon.
- 16. The integrated circuit of claim 13, further comprising:
a conductive via extending through the second dielectric layer.
- 17. The integrated circuit of claim 16, further comprising:
a conductive line extending through the first dielectric layer and electrically coupled to the via, the conductive line having a significantly greater area than the via.
- 18. The integrated circuit of claim 16, wherein the interconnect structure includes a middle layer between the first dielectric layer and the second dielectric layer, the contact extending through the middle layer, the conductive line not extending through the middle layer.
- 19. The integrated circuit of claim 18, wherein the via and the trench conductor include copper.
- 20. The integrated circuit of claim 13, wherein the first dielectric layer is a low-k dielectric layer.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] The present application is a continuation-in-part of U.S. patent application Ser. No. 09/716,217 (Attorney Docket No. 039153/0379) entitled “Imaging Layer as Hard Mask for Organic Low-K Materials” filed by Subramanium et al. on Nov. 21, 2000 and assigned to the assignee of the present application.
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
09716217 |
Nov 2000 |
US |
Child |
09884834 |
Jun 2001 |
US |