A novel electrolytic plating method suitable for filling non-through holes with metal is disclosed. The electrolytic plating method uses a plating solution containing additives such as a surfactant, a brightening agent and a smoothing agent and includes pulse plating for controlling adsorption and desorption of tie additives on the surface and in the non-through holes of substrate and subsequent DC plating for filling up the non-through holes with metal.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows cross-sections of blind via holes in a printed circuit board plated in Example 1.
FIG. 2 shows cross-sections of blind via holes in a printed circuit board plated in Example 2.
Claims
1. An electrolytic plating method using the plating solution containing additives such as surfactants, brightening agents and smoothing agents, characterized by a plating process comprising a pulse plating to control adsorption and desorption of the additives and a subsequent DC plating to fill up non-thorough holes.
2. An electrolytic plating method according to claim 1, wherein the thickness of plating formed by the pulse plating is not larger than 15 μm.
3. An electrolytic plating method according to claim 1, wherein the plating solution contains as an additive at least a component which exhibits the acceleration of metal deposition of plating.
4. An electrolytic plating method according to claim 1, wherein an insoluble electrode is used as a counter electrode relative to the substrate to be plated.
5. An electrolytic plating method according to claim 1, wherein the metal deposited as plating is copper.
6. A printed circuit board having at least one non-through hole electrolytically plated by the method according to claim 1.
7. A semiconductor wafer plated electrolytically by the method described in claim 1.
Patent Application
20080023218
