Patent Application
20160146878
The present invention relates to a substrate for providing early warning of degradation in a semiconductor device comprising an actual device and a solder joint and a dummy device closely placed to the actual device on the substrate; a dummy device thereof, method for manufacturing the dummy device; an inner solder joint part.
In electronic products including semiconductor devices, reliability and availability of the electronic products have been key issues because unexpected failure in actual use application can create huge financial cost and life-threatening consequence to end-users. If the sign of the occurrence of a failure can be detected before the failure occurs, it is possible to take measures such as perform maintenance in advance. For the dominant failure, this method also makes the product recovery easier and faster due to the known root cause of failure and increases the availability as consequence. Therefore, it has been desired an early warning and accurate prediction system of joint failure which can makes the possibility to take measure and perform maintenance in advance and a dummy device detecting the sign of the occurrence of a failure before the damage breaks out to cause the failure can be an effective failure prediction method.
In electronic products such as power device, the joint portions between semiconductor chip and substrate are damaged gradually by the application of external loads such as vibration and pressure. It has been a problem that loads resulting from heat generation and temperature fluctuations damage the joint because when temperature fluctuates, the difference between the thermal expansion coefficients of semiconductor chip and substrate makes the joint absorbs this difference of deformation amounts.
In semiconductor device, the degree of the solder joint damage of electronic device due to temperature fluctuation could be monitored by an adhered aluminum film on the corresponding substrate since there is correlation between the damage of solder joint and the delamination of adhered aluminum film measured with the change of resistance (Japanese Patent Publication 2010-62190).
The joint damage in ball grid array (BGA) could be predicted by the change in electrical resistance value due to the disconnection of the wire connected to the corner electrode pad in which the break strength the wire is lower than break strength of the bump join (Japanese Patent Application 2011-532853).
The joint damage caused by Kirkendall void and electromigration could be predicted by a structure comprising a conductor sandwiched with other conductor in which flowing current across the sandwich structure makes electrical failure (Japanese Patent Publication 2010-209199).
Lifetime of electronic component mounted on a circuit board could be predicted on the basis of the generated failure in the residual diagnosing device that has solder joint with the smaller heat conductivity than that of the actual component (Japanese Patent Publication 2011-252842).
These different types of lifetime prediction, however, have the method in which the relation of the actual device and a device for detecting the sign of the occurrence of a failure should be firstly determined. Furthermore, these different methods were only applicable under a certain limited condition, so the lifetime prediction becomes less accurate under various application conditions because of its large variation. Therefore, it has been desired an adaptive dummy device which is applicable to various application conditions to detect the sign of the occurrence of a failure before the damage breaks out to cause the failure.
The object of the present invention is solved by the following means.
(1) A substrate for providing early warning of degradation in a semiconductor device comprising: an actual device comprising a semiconductor component and a solder joint; and a dummy device closely placed to the actual device on the substrate and connected electrically in parallel circuit to the actual device, comprising a dummy semiconductor component and a solder joint comprising an outer solder joint part and an inner solder joint part, wherein the outer solder joint part has same characteristic to the solder joint of the actual device and the inner solder joint part accelerates the crack growth faster than the outer solder joint, and percentage area of outer solder joint part is smaller than the predetermined failure criterion of delamination percentage in actual device corresponding to the threshold value of electrical change.
(2) The substrate according to (1), further comprising one or more dummy device(s) closely placed to around of the actual device, connected electrically in parallel circuit to the other dummy device(s) and the actual device.
(3) A dummy device according to (1), wherein the inner solder joint part comprises the formation selected from a group consisting of brittle precipitation, brittle intermetallic compound and the formation of voids and weak strength solder joint at the interface.
(4) The dummy device according to (3), wherein the brittle precipitation and/or brittle intermetallic compound in the inner solder joint part is formed by using a barrier layer on the substrate, wherein the barrier layer for inner solder joint part is made of an electroless Ni (or Ni with high impurity content such as NiP) and the barrier layer for outer solder joint part is made of an electrolytic Ni.
(5) The dummy device according to (3), wherein the formation of voids is the extensive formation of Kirkendall voids.
(6) Method for manufacturing the dummy device according to (5),
(7) Method for manufacturing the dummy device according to (6), wherein the substrate surface is a dummy semiconductor chip surface.
(8) Method for manufacturing the dummy device according to (3), wherein the formation of voids and or weak strength solder joint at the interface is performed by the poor solder wettability on the substrate surface or dummy semiconductor chip surface for the inner solder joint part during the reflow process.
(9) Method for manufacturing the dummy device according to (8), wherein the gold coating thickness of substrate surface for the inner solder joint part is equal to or less than 30% of thickness of the substrate surface for the outer solder joint part.
(10) Method for manufacturing the dummy device according to (8), wherein the gold coating thickness of a semiconductor chip surface for the inner solder joint part is equal to or less than 30% of the gold coating thickness of semiconductor chip surface for the outer solder joint part.
(11) Method for manufacturing the dummy device according to (8), wherein an oxide layer with the thickness equal to or more than 1 nm is formed on the one side and/or both sides of the solder film surface corresponding to the inner solder joint part by O2 plasma, and wherein the solder film surface corresponding to the outer solder joint part is covered with a mask to prevent the oxide layer from being formed on the outer solder joint part of solder film.
(12) Method for manufacturing the dummy device according to (3), wherein the voids in the inner solder joint part are formed as trapped air during the reflow soldering process by using the discontinuous structure in the middle part of the solder film.
(13) Method for manufacturing the dummy device according to (12), wherein solder film is patterned with some holes in the middle part or solder film.
(14) Method for manufacturing the dummy device according to (12), wherein solder film is patterned with an open area or a big hole filled with some solder balls in the middle part of solder film.
(15) An inner solder joint part according to (1) comprising the formation selected from a group consisting of brittle precipitation, brittle intermetallic compound and the formation of voids.
(16) The inner solder joint part according to (15), wherein the brittle precipitation and/or brittle intermetallic compound is formed by a barrier layer on the substrate, wherein the barrier layer for inner solder joint part is made of an electroless Ni and the barrier layer for outer solder joint part is made of an electrolytic Ni.
(17) The inner solder joint part according to (15), wherein the formation of voids is the extensive formation of Kirkendall voids.
(18) The inner solder joint part according to (17), wherein the extensive formation of Kirkendall voids is provided by using the substrate surface and/or the semiconductor chip surface comprising the thickness of the barrier layer for the inner solder joint part is equal to or less than 80% the thickness of the barrier layer for the outer solder joint part.
(19) The inner solder joint part according to (15), wherein the formation of voids and/or weak strength solder joint at the interface are formed by the poor solder wettability on the substrate surface and/or the semiconductor chip surface for the inner solder joint part during the reflow process.
(20) The inner solder joint part according to (19), wherein the gold coating thickness of surface for the inner solder joint part is equal to or less than 30% of the gold coating thickness of the surface for the outer solder joint part.
(21) The inner solder joint part according to (19), wherein the solder film with an oxide layer with the thickness equal to or more than 1 nm is formed on the one side and/or both sides of the solder film surface corresponding to the inner solder joint part by O2 plasma, wherein the solder film surface corresponding to the outer solder joint part is covered with a mask to prevent the oxide layer from being formed on the solder film surface corresponding to the outer solder joint part.
(22) The inner solder joint part according to (15) comprising voids, wherein the voids are formed as trapped air during the reflow process by using the solder film with the discontinuous structure in the middle part of solder film.
(23) The inner solder joint part according to (22), wherein the discontinuous structured solder film is patterned with some holes in the middle part or solder film.
(24) The inner solder joint part according to (22), wherein the discontinuous structured solder film is patterned with an open area or a big hole filled with some solder balls in the middle part of solder film.
The present invention can accurately and early predict lifetime and warn degradation in a semiconductor device. The present invention also can warn and predict early warning of solder joint failure in actual use application including unpredicted and unanticipated failure which occurs due to different usage environments. The present invention also can predict more accurate the joint failure with adjustable predicting time. Adjacent actual and dummy device(s) of the present invention can reduce effect of variation and makes high precision of prognostics. By changing an area ratio of an outer solder joint part/an inner solder joint part in dummy device, the lifetime prediction in the present invention can be adjustable to any predetermined lifetime criteria. The early warning of a dummy device can eliminates the unpredicted failure of an actual device in actual use application.
The present invention relates to a substrate for providing early warning of degradation in a semiconductor device and manufacturing methods thereof; a dummy device and manufacturing methods thereof, an inner solder joint part of the solder joint of the dummy device and manufacturing methods thereof. One object of the present invention is to provide method and a dummy device to determine early warning of solder joint failure in actual use application including unpredicted and unanticipated failure which occurs due to different usage environments. Another object of the present invention is to provide methods and dummy devices to predict more accurate joint failure with adjustable predicting time. Each of the present inventions is described in detail as below.
The present invention relates to a substrate for providing early warning of degradation in a semiconductor device comprising: an actual device comprising a semiconductor component and a solder joint; and a dummy device closely placed to the actual device on the substrate comprising a dummy semiconductor component and a solder joint comprising an outer solder joint part and an inner solder joint part, wherein the outer solder joint part has same characteristic to the solder joint of the actual device and the inner solder joint part accelerates the crack growth faster than the outer solder joint, and percentage area of the damaged outer solder joint part is smaller than the predetermined failure criterion of delamination percentage in the actual device.
One object of the substrate of the present invention is to determine early warning of solder joint failure in actual use application including unpredicted and unanticipated failure which occurs due to different usage environments. Another object of the present invention is to provide methods and dummy devices to predict more accurate the joint failure with adjustable predicting time.
An actual device used as a functional device contributing to the system performance comprises a semiconductor component and a solder joint, for example, electronic device, preferably, a semiconductor device. A dummy device used as a nonfunctional device without contribution to the system performance is described in detail below.
The detection of the joint failure is performed by the temperature cycling test and the percentage of the damaged joint area is measured. The damage means crack or crack growth. The temperature cycling test is an accelerated test consisting of repeated alternate exposures to high and low temperature extremes at relatively high rates of temperature change. At first, the crack growth in the joint layer of the dummy device and the actual device undergoes the same way because the characteristic of the outer solder joint part of the dummy device is same as that of the solder joint layer of the actual device. When the cracks proceeds into the inner solder joint part of the dummy device, the crack growth is more accelerated than that in the actual device and the dummy device reaches the failure criterion before the actual device reaches the failure criterion. By the acceleration of crack growth in the dummy device, the dummy device reaches the failure criterion before the actual device reaches the failure criterion; whereby the accurate lifetime of the actual device is predicted.
One embodiment on an electrical circuit of the substrate of the present invention is shown in
The “dummy device” means a nonfunctional device for detecting the sign of the occurrence of a failure before the damage breaks out to cause the failure. The dummy device is closely placed to the actual device on the substrate and is connected electrically in parallel circuit with the actual device. The dummy device comprises a dummy semiconductor component and a solder joint comprising a joint layer consisting of an outer solder joint part and an inner solder joint part. The outer solder joint part has basically the same characteristic to the solder joint of the actual device and the inner solder joint part is more sensitive to the load than the outer solder joint part and accelerates the crack growth faster than the outer solder joint.
The dummy devices are configured to detect the imminent electrical failure of the actual device when the electrical change of dummy devices exceeds orderly a predetermined threshold value ahead of the actual device wherein the dummy devices have increasing fragility of the inner solder joint part and or increasing smaller percentage areas of the outer solder joint part.
In the initial lifecycle environment, the dummy device undergoes the same way as actual device in which crack initiates from the edges and grows across the joint until certain time before the predetermined failure criterion, growth of crack in the joint of the dummy device is accelerated when it enters the inner joint part and the dummy device fails earlier before the actual device and alarms the imminent failure of the actual device.
As shown in
The percentage area of the outer solder joint part is smaller than the predetermined failure criterion of delamination percentage in the actual device. As shown in
Delamination of the older joint in the device impairs heat transfer from the semiconductor chip to the substrate and consequently causes the increased thermal resistance, a measure of how fast heat can be dissipated from the semiconductor. Since the increased thermal resistance restricts performance of the device, it is commonly used to define the device lifetime. As thermal resistance increases, temperature of the device increases as consequence. Thus, the increase of thermal resistance due to the delamination of the solder joint can be detected electrically by the change of temperature-dependent device parameter such as the device voltage. At predetermined thermal resistance as criterion of device lifetime or index of thermal resistance, the corresponding delamination of the solder joint is defined to the threshold value of voltage change.
As shown in
In the present invention, warning of actual device failure may be performed by the following system. For example, when the electrical signal of the dummy device is monitored and compared with the failure criterion or index of thermal resistance, once the electrical signal of the dummy device reaches the threshold value of voltage change, such as “delta VDS” or the change of drain-to-source voltage in power MOSFET devices, an alarm is activated and informs the needs to perform maintenance action.
The dummy device is also called as a canary device which is a detector whose name is derived from a canary once used for detecting poison gas in coal mines. In the use of the canary device, a detecting device (canary device) is disposed at a point carrying a larger load than on a joint to be measured and then a failure is caused to occur earlier before the actual device and alarms the imminent failure of actual device. Thus, the imminent failure of the actual device can be predicted.
The substrate of the present invention may comprise two or more dummy devices as shown in
The dummy device of the present invention comprises a dummy semiconductor component and a solder joint comprising an outer solder joint part and an inner solder joint part. The inner solder joint part is more fragile than the outer solder joint part, it means, the inner solder joint part accelerates the crack growth faster than the outer solder joint. The inner solder joint part is fragile due to the existence of at least one selected from the group consisting of brittle precipitation, brittle intermetallic compound, the formation of voids and weak strength solder joint at the interface.
Brittle precipitation and/or brittle intermetallic compound included in the inner solder joint part cause fragility and limit the mechanical strength of the inner solder joint part. The brittle precipitation and/or brittle intermetallic compound are originated by the impurity in the substrate coating such as in an electroless Ni barrier layer wherein it contains phosphorous (P) as impurity. This phosphorus impurity diffuses to the inner solder joint part and creates P-rich precipitation and/or P-rich intermetallic compound which are brittle. The outer solder joint part also has the barrier layer, but it is an electrolytic barrier layer, for example an electrolytic Ni.
The inner solder joint part may be fragile due to the formation of voids therein. Preferable formation of voids includes Kirkendall voids, but not limited to the above. Kirkendall voids means voids formed due to the imbalance in the diffusion rates of metal atoms across an interface of two dissimilar materials. A barrier layer is placed on a substrate surface to prevent the diffusion of solder component to the substrate. Thinner barrier layer, the extensive Kirkendall voids are formed at the interface. Extensive Kirkendall voids in the inner solder joint part relative to the outer solder joint part are formed when the thickness of a barrier layer for the inner solder joint part on the substrate surface is thinner than the thickness of a barrier layer for the outer solder joint part upon the exposure to the high temperature above 150° C. The substrate surface may be a semiconductor chip surface. In this case, the chip may also has the thinner barrier layer for the inner solder joint part on the chip surface relative to the barrier layer for the outer solder joint part on the chip substrate.
The voids in the inner solder joint part may be formed when solder wettability on the substrate surface or the semiconductor chip surface for the inner solder joint part is poor during reflow process, wherein a melted solder improperly wets the surface of a substrate and/or a chip. Poor solder wettability also create weak strength of the solder joint at the joint interface instead of voids. Formation of an oxide layer on the surface of the substrate and/or the chip inhibits the wetting of a melted solder. The use of gold coating on the surface of the substrate and/or the semiconductor surface prevents oxygen from the surface and protects it from oxidation. The poor solder wettability on the substrate surface for the inner solder joint part relative to the outer solder joint part may be obtained by using the gold coating on substrate surface having the thickness for the inner solder joint part equal to or less than 30% of thickness of the gold coating for the outer solder joint part.
The substrate surface may be a semiconductor chip surface, wherein the poor solder wettability on the chip surface for the inner solder joint part relative to the outer solder joint part may be obtained by using the gold coating on chip surface having the thickness for the inner solder joint part equal to or less than 30% of thickness of the gold coating for the outer solder joint part.
The poor solder wettability may be obtained by oxidizing the solder film surface for the inner solder joint part by O2 plasma. The solder film refers to the initial solder material in the film form before the reflow process. Oxidation on the solder film for the inner solder joint part can be performed on one or both sides of the solder film. The resulted oxide layer may have the thickness equal to or more than 1 nm. Then, voids are occurred in the inner solder joint part due to the poor solder wettability. In this case, the solder film surface for the outer solder joint part is not oxidized. To prevent the oxide layer from being formed on the outer solder joint part of the solder film, the surface for the outer solder joint part is covered with a removable mask.
The voids in the inner solder joint part may be formed as trapped air by using the solder film with the discontinuous structure in the middle part. The discontinuous structure may be a solder film patterned with some holes in the middle part of the solder film (
The dummy device comprising the formation of voids in inner solder joint part is manufactured by the following steps:
In the above method, the substrate may be a metalized substrate. The substrate surface of which the thickness of the barrier layer for the inner solder joint part is thinner than the thickness of the barrier layer for the outer solder joint part, may be a semiconductor chip surface.
In the present invention, the voids in the inner solder joint part may be formed when the solder wettability on the substrate surface or the semiconductor chip surface for the inner solder joint part is poor during the reflow process. The poor solder wettability on the substrate surface for the inner solder joint part relative to the outer solder joint part is formed by using the gold coating on the substrate surface having the thickness for the inner solder joint part equal or less than 30% of thickness of gold coating on the substrate surface and the semiconductor chip surface for the outer solder joint part.
In the above method, the gold coating thickness of the semiconductor chip surface for the inner solder joint part may be equal to or less than 30% of the gold finish thickness of semiconductor chip surface for the barrier layer for the outer solder joint part.
The poor solder wettability may be obtained by oxidizing the surface for the inner solder joint part of a solder film by O2 plasma. Oxidation on the solder film for the inner joint part can be performed on one or both sides of the solder film. The resulted oxide layer may have the thickness equal to or more than 1 nm. Then, voids are formed in the inner solder joint part due to poor solder wettability. In this case, the surface of the solder film for the outer solder joint part is not oxidized and during the oxidization, the surface for the outer solder joint part of the solder film is covered with a mask to prevent the oxide layer from being formed on the solder film for the outer solder joint part.
As shown in
The present invention is not limited to the above embodiments, but can be modified variously without departing from the scope of the present invention.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2013/004081 | 7/1/2013 | WO | 00 |
