This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2013-036232, filed on Feb. 26, 2013 and prior Japanese Patent Application No. 2013-190756, filed on Sep. 13, 2013, the entire contents of which are incorporated herein by reference.
The present invention relates to a structure that connects an electronic component to two lead frames, which are spaced apart from each other, with a conductive joining member so that the electronic component bridges the lead frames.
Japanese Laid-Open Patent Publication No. 2007-234737 discloses a technique used in a chip capacitor connection structure that forms a thin stress reduction portion in each lead frame. The thin stress reduction portion reduces the stress generated in a conductive joining member.
The stress generated in the conductive joining member is concentrated between the chip capacitor and the lead frame. The thickness of the conductive joining member located between the chip capacitor and the lead frame greatly affects the connection reliability. When the conductor joining member is thin, the connection reliability decreases even when using the thin stress reduction portion.
One aspect of the present invention is a connection structure for an electronic component. The electronic component bridges two lead frames that are spaced apart from each other, and the electronic component is connected to the two lead frames by a conductive joining member. The connection structure includes two electrodes arranged on at least portions of a lower surface of the electronic component. The two electrodes respectively face the two lead frames. A receiving surface is included in each of the two lead frames immediately below the corresponding electrode. The receiving surface extends from a supporting portion, which supports the electronic component, toward the other one of the lead frames and away from the electronic component. The conductive joining member is located between the receiving surface of each of the two lead frames and the corresponding one of the electrodes.
A further aspect of the present invention is a method for connecting an electronic component to two lead frames, which are spaced apart from each other on a substrate, with a conductive joining member. The electronic component bridges the lead frames and includes two electrodes arranged on at least portions of a lower surface of the electronic component, and each of the two lead frames includes a receiving surface that extends away from the electronic component when the electronic component is set on the lead frames. The method includes arranging the two lead frames spaced apart from each other on the substrate so that the receiving surfaces and the substrate are located on opposite sides of the lead frames, arranging the conductive joining member on each of the two lead frames, bridging the electronic component over the two lead frames when the two electrodes of the electronic component are each in contact with the conductive joining member, and melting the conductive joining member so that the conductive joining member is located between each of the two electrodes of the electronic component and the receiving surface of the corresponding one of the lead frames.
Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
The invention, together with objects and advantages thereof, may best be understood by reference to the following description of the presently preferred embodiments together with the accompanying drawings in which:
One embodiment of an electronic component connection structure will now be described.
As shown in
Referring to
Referring to
An electronic component connection process that obtains the connection structure will now be described.
Referring to
Referring to
In a main connection process, the pellets of the solder 5 are melted so that the melted solder 5 is partially located between the electrodes 41 of the chip capacitor 4 and the receiving surfaces 21 of the lead frames 2 and 3. This obtains the connection structure for the chip capacitor 4 shown in
The operation of the electronic component connection structure will now be described.
In contrast, in the present example, the receiving surface 21 is formed in each of the lead frames 2 and 3, and the solder 5 is located and received between the receiving surfaces 21 and the electrodes 41 of the chip capacitor 4. The stress generated in the solder 5 is concentrated between the chip capacitor 4 and the lead frames 2 and 3. However, the solder 5, which is located between the chip capacitor 4 and the lead frames 2 and 3, is thicker than the comparative example. This disperses and reduces the stress. Further, the increased amount of the solder 5 increases the strength.
The present embodiment has the advantages described below.
(1) The solder 5 is located and received between each electrode 41b of the chip capacitor 4 and the receiving surface 21 of the corresponding one of the lead frames 2 and 3. This disperses and reduces the stress concentrated between the chip capacitor 4 and the lead frames 2 and 3. Accordingly, the connection reliability may be improved.
(2) The solder 5 is located immediately below the two corners 42 of each electrode portion 41b where the stress is largest. The thickness of the solder 5 is increased at this location thereby limiting cracking.
(3) The receiving surface 21 of each of the lead frames 2 and 3 extends from the supporting portion, which supports the chip capacitor 4, via a portion located immediately below the two corners 42 of the electrode portion 41b, and toward the other one of the lead frames 2 and 3. The distance between the two supporting portions is less than the length of the chip capacitor 4. In this manner, the narrowed distance between the two lead frames 2 and 3 facilitates the mounting of the chip capacitor 4.
(4) The two lead frames 2 and 3 are first arranged on the substrate 1 spaced apart from each other. Then, the pellets of the two solders 5 are arranged on the lead frames 2 and 3 so that the lead frames 2 and 3 are located at the lower side of the solders 5. Subsequently, the chip capacitor 4 is arranged on an upper side of the solders 5. Thus, the melted solder 5 is easily received in the receiving surfaces 21. Accordingly, advantages (1) and (2) are easily achieved.
(5) The receiving surfaces 21 of the two lead frames 2 and 3 are symmetrically formed in correspondence with the four corners 42 of the chip capacitor 4. This equally reduces stress.
It should be apparent to those skilled in the art that the present invention may be embodied in many other specific forms without departing from the spirit or scope of the invention. Particularly, it should be understood that the present invention may be embodied in the following forms.
Referring to
The receiving surface 21 of each of the lead frames 2 and 3 may extend from the supporting portion, which supports the chip capacitor 4, to immediately below the two corners 42. Alternatively, under the condition that the solder 5 between the receiving surface 21 and the electrode 41 has sufficient thickness, the receiving surface 21 of the lead frames 2 and 3 may extend from the supporting portion to just before the two corners 42.
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The electronic component is not limited to a chip capacitor 4.
The conductive joining member is not limited to the solder 5.
The present examples and embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalence of the appended claims.
Number | Date | Country | Kind |
---|---|---|---|
2013-036232 | Feb 2013 | JP | national |
2013-190756 | Sep 2013 | JP | national |