Patent Application
20080217183
In forming semiconductor chips, various processing steps are performed on a semiconductor wafer to obtain completed semiconductor dies from the wafer. Oftentimes, metal features such as copper (Cu) bumps are formed near the end of processing. Such bumps act as interconnects that can be used to couple completed die on the semiconductor wafer to a package and thus act as die-package interconnects. In other semiconductor devices metal features such as through silicon vias (TSVs) may be present that can be used as interconnects between multiple dies within a semiconductor package, i.e., die-die interconnects.
Typically such metal features are formed via an electroplating process to build up the features to the desired heights. These features can be tens of microns in height. However, electroplating can leave relatively rough surfaces and furthermore, variations across a wafer may cause significant inconsistencies in height between individual features. It is commonplace for electroplated Cu bumps to have bump height variations of over 10 microns. While conventional chemical mechanical polishing (CMP) methods can reduce this height variation, significant costs are incurred and potential damage can occur.
Embodiments of the present invention may use low-current electropolishing to reduce height differentials between individual metal features formed on a semiconductor wafer. Such features may be, for example controlled collapse connection (C4) bumps such as C4 flip-chip bumps, through silicon vias (TSVs) or the like. In this way, a substantially planar bump surface may be realized across a wafer, providing improved uniformity to meet assembly tolerances when used as interconnects to a package or other die.
In some embodiments, a conventional electroplating apparatus may be used for electropolishing (with a reversed current polarity and a different electrolyte to enable removal of material). In some embodiments, a current density ranging between 2 and 10 milliamperes per square centimeter (ma/cm2) may be applied to the electrodes. Electropolishing may occur using various electrolytic solutions. For example, in one embodiment a solution including phosphoric acid, e.g., concentrated or full strength phosphoric acid may be used with additional components having sequestering properties with respect to the metal to be removed. The electrolytic solution may have a viscosity of between approximately 10 to 40 centipoise. Note that the amount of metal to be removed may depend on various factors including the applied current density, electrolyte viscosity, polishing time and temperature and so forth.
Referring now to
Above barrier layer 20 may be formed a metal stack 30, which may act as a seed layer for additional metal features to be formed thereon. In one embodiment, metal stack 30 may be a copper layer, for example, formed electrolessly. Above stack layer 30, a mask layer such as a photoresist layer 40 may be formed and patterned to provide a plurality of openings that expose portions of stack 30.
Then, a metal feature may be formed, e.g., via electroplating. Specifically, as shown in
Electropolishing of plated copper deposits may be accomplished in process called electrochemical dissolution. In this process, current polarity is the opposite to that of electroplating. Accordingly, the wafer may be at least partially immersed (i.e., the device side or fab side of a wafer including completed microelectric devices) in an electrolyte (such as described above), with an anode electrode coupled to the wafer and a cathode electrode present in the electrolyte. Thus the plated deposit facing anode is in an electrical field that pulls away metal/ions from the deposit toward the cathode. On a microscopic level, some plated and neutral particles or crystals oxidize to become ions in a solution and leave the plated surface. This first phase of electropolishing thus loosens up the plated structure and releases more solid particles from the plated deposit into the solution. These solid particles in the electrical field are transported to an insoluble anode. With that, the underlying electropolishing phenomenon is controlled by two steps: electrochemical reaction of metal oxidation and transport of metallic particles away from the plated part. Naturally, the electrochemical dissolution needs a conducting solution and chemical environment that even chemically may facilitate the dissolution. This can be accomplished using an electrolyte of concentrated phosphoric acid with some compound(s) having sequestering properties with respect to plated metal. As examples, in case of copper the additional compounds may include citric acid, ethylenediaminetetraacetic acid (EDTA), or both. Further, in the solution may be present compounds that increase the overpotential of oxygen formation preventing solution decomposition before metal dissolution. Polyethylene glycol (PEG) type compounds of high molecular weight may be present in the electrolyte to inhibit oxygen formation and wet the deposit.
The final effect of electropolishing depends on chemistries used and current level. With the same solution, at low currents only small solid particles are removed from the surface. Such low currents may be between 2 and 4 ma/cm2. This phase may occur for between approximately 0.5 to 5 minutes. At mid and high currents (e.g., between approximately 4 and 10 ma/cm2), deposit thickness can be dramatically reduced at much faster than plating rates. This phase may occur for between approximately 1 to 10 minutes, with the time varying based on desired thickness reduction. This can be followed by a low current step to control deposit roughness.
In other embodiments, a mask layer may be removed prior to electropolishing. Referring now to
Thus in various embodiments, electropolishing of metal bump features (for both C4 flip-chip and TSV's) can be accomplished using either or both the options described below depending on the application. In the first embodiment, the C4 patterned resist is kept intact post C4 Cu electroplating. The wafers are transferred to an electropolishing bath and an anodic current is applied to the wafer. In one embodiment, electrical contact to the wafer may be made through an exposed portion of a barrier layer at an edge of the wafer. Electropolishing thus planarizes the surface of the bumps and reduces the bump height difference between the Cu bump features induced from the electroplating process.
In the second embodiment described above, electropolishing of the bump features occurs on all exposed conductive regions unlike the first embodiment where only the surface is exposed and is electropolished. In this embodiment, the C4 patterned resist may be stripped post C4 Cu electroplating. The wafers are transferred to an electropolishing bath and anodic current is applied as described above. Since there is no mask layer to protect the conductive barrier layer of the stack, these layers may also be etched away during the electropolishing. The electrical current then may conduct through a non-Cu stack layer, causing a change in the potential and thus a change in the electropolishing rate.
In various embodiments, electropolishing can be achieved in the same type of toolsets and similar chemistries as employed for electroplating, in contrast to CMP methods which need additional toolsets and slurries, adding cost to the process. In some embodiments, electropolishing can be applied to planarize mixed C4 bump diameter and mixed C4 pitch designs to meet flip-chip assembly tolerances. In some embodiments, electropolished features may offer better control of metal removal and thus help achieve better uniformity through higher polishing rates, scratch and residue free polishing, lower particle generation and lower waste streams than conventional CMP-based methods. Further, electropolishing is stress free compared to CMP-based methods and thus may be more beneficial for technologies which employ low-dielectric constant (k) inter-layer dielectric (ILD) architectures.
Referring now to Table 1, provided are example results of processing in accordance with an embodiment of the present invention. As shown in Table 1, improved bump height variation (i.e., reduced variation, as shown by the standard deviation values) occurs after electropolishing performed as described herein.
While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.
