This subject matter is generally related integrated circuit (IC) wafer processing.
Wafer-level packaging techniques can include packaging, testing, and performing burn-in operations prior to singulation of the wafer into individual IC chips. During singulation, a dicing machine saws the wafer along scribe lines to separate the individual IC chips. Once an IC chip has been singulated, the IC chip can be mounted on a printed circuit board (PCB).
A typical IC chip uses metal bond pads rather than wires or pins for mounting. The bond pads can be etched or printed onto the wafer, typically along the edges of the package on the face or circuit side of the IC chip. In some implementations, Input/Output (I/O) pads are electrically connected to the bond pads of the IC chip. A redistribution layer (RDL) includes metal lines that can relocate the signals provided by the bond pads to desired locations within the IC chip. Solder bumps can be attached to the I/O pads to facilitate assembly onto PCBs.
Conventional solder bump fabrication techniques involve vacuum deposition, photolithographic, and wet chemical etching processes to form an under bump metal (UBM) layer onto which solder paste or solder plating processes can be used to form the solder bumps.
Vacuum deposition processes and equipment are expensive to purchase, facilitate and maintain. Moreover, wafer bumping with thin-film UBM processes can be costly. Photomask sets are required to define the UBM geometries and locations and, once designed and tooled, cannot be changed. Similarly, the plating equipment, facilitation, maintenance and bath chemistry maintenance involved in electroless plating processes can be costly. Additionally, electroless plating processes are often sensitive to variations in the metal bond pad metallurgy (e.g., aluminum) which can cause plating deposition issues. Therefore, an etching evaluation step is typically performed on each new product at a cost to the customer.
Another shortfall related to the electroless plating UBM process is that the UBM metal can plate onto the backside of the wafer. As a result, the wafer backside may need to be coated with a plating resist and then stripped post UBM deposition. The coating and stripping steps add cost and process lead time.
Both the thin-film UBM process and the electroless plating UBM deposition process typically require wafer thicknesses in excess of 20 mils to prevent wafer breakage during processing. A post-bumping wafer grind step, in many cases, is therefore needed to reduce the wafer depth to the final silicon thickness product requirement. In some circumstances, the final wafer thickness is limited by the solder-bumping process (e.g., about 7 mils) due to the grinding process constraints.
A low cost method of forming solder bumps on an IC wafer includes depositing solder directly onto stud bumps formed on bond pads of the IC wafer. In one implementation, stud bumps are formed on the IC wafer by performing wire bonding (e.g., ball or wedge bonding) onto bond pads of the wafer. Photodefinable solder mask material is applied to the wafer and cured. The photodefinable solder mask material is exposed to form open solder mask areas at the metal bond pad areas. Solder paste is applied into the open solder mask areas. Reflowing the solder paste on the wafer forms solder bumps that wet to the stud bumps. The solder mask is then stripped from the wafer.
In another implementation, stud bumps are formed on a wafer by performing wire bonding onto bond pads, applying solder paste onto the stud bumps and reflowing the solder past to form solder bumps which wet to the stud bumps. Optionally, a polymer or other protective layer can be applied to the wafer to protect exposed bond pads.
In another implementation, stud bumps are formed on a wafer by performing wire bonding onto bond pads and passing the wafer through a wave-soldering machine to form solder bumps on the stud bumps.
The simplicity of the disclosed processes provide many advantages, including a lowering of overall product cost when compared with conventional deposited and electroless plated UBM processes. Some examples of cost savings include but are not limited to: a) lower equipment costs and facilitation costs when compared to vacuum deposition equipments, wet-etch lines and plating lines; b) no plating or etching chemical analysis and disposal costs; c) no UBM mask design and mask fabrications costs; d) no repassivation layer costs to “re-shape” the passivation opening; e) no “etch-text” costs as necessary in the electroless UBM process; f) no “full-cassette” charges as necessary in the electroless UBM process; and g) no wafer backside protection layer costs as necessary in the electroless UBM process.
The disclosed processes also provide more flexible changes. Since a wire bonder is used to form the stud bumps on an IC wafer, any changes (e.g., bump pattern, delete bump locations) involve simple changes in wire bonding software which is relatively easy and fast. If using conventional vacuum deposition masks, a new mask set has to be designed and fabricated which can be costly and is often associated with a long lead time.
The disclosed processes also provide higher reliability. The stud bump, which acts as the UBM has a thickness in the range of about 50 microns. The vacuum deposited UBM has a thickness in the 2 micron range and the electro plated UBM thickness can go up to about the 5 micron range. Theoretically, the stud stump UBM has the longest UBM consumption life.
The disclosed processes provide a thin bumped-wafer product. Currently, both vacuum deposited or electroless plated UBM processes require wafer thicknesses in the 20 mil range to prevent breakage during bumping process. If the final product requirement requires thinner wafer thickness, a post-bumping wafer back-grind step can be performed. Due to the presence of solder bumps on the wafer, the current industry bumped-wafer, back-grind capability is at about 7 mils. The wire bonding process can perform bonding on wafers of low thickness. This allows the wafers to be back-grinded to lower than about 7 mils (e.g., about 4 mils), and then processed through a wire bonder to form the stud bump UBM. Wafer thicknesses of lower than about 4 mils can be fabricated.
Solder bumps 110 are small spheres of solder (solder balls) that can be bonded to contact areas or metal (e.g., aluminum) bond pads 106 formed on a face (circuit side) of IC chip 102 during wafer fabrication, and subsequently face-down bonded with substrate 104. The length of electrical connections between IC chip 102 and substrate 104 can be minimized by: (a) forming solder bumps 110 on bond pads 106; (b) flipping IC chip 102 face-down; (c) aligning solder bumps 110 with bond pads 108 on substrate 104; and (d) reflowing solder balls 110 in a furnace to establish bonding between IC chip 102 and substrate 104. This method can provide electrical connections with minute parasitic inductances and capacitances. IC package 100 can be used in a variety of technologies, such as 3D-VLSI technology.
A process to form low cost sold bumps 110 on IC wafers will now be described in reference to
After forming wire ball bonds on metal bond pads 204, the wires can be cut directly above the ball bonds, leaving metal stud bumps 202. In one example, an electronic flame-off (EFO) can be set to cut the wires directly above the ball bonds to produce stud bumps 202. The size of stud bumps 202 depends, in part, upon the gauge of wire used. For example, the thickness of the stud bumps 202 can be in a range of about 50 microns depending upon the gauge of the wire. In comparison, a typical vacuum-deposited UBM may have a thickness of up to about 2 microns and a typical electroless plated UBM may have a thickness of up to about 5 microns. Theoretically, stud bumps 202 provide a larger surface for a solder ball to adhere to and have a longer consumption life than conventional UBM techniques.
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If the desired bump pattern changes at a future time (e.g., deletion of one or more bumps, relocation of bumps), then the wire-bonding processes can be easily changed to allow solder bumps 210 to be relocated. Thus using the wire ball-bonding process to form stud bumps 202 allows for quick and inexpensive changes to semiconductor manufacturing processes as opposed to conventional UBM methods.
A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made. For example, steps of one or more processes may be combined, deleted, modified, or supplemented to form further processes. As yet another example, the process steps depicted in the figures do not require the particular order shown to achieve desirable results. In addition, other steps may be provided, or steps may be eliminated, from the described processes, and other materials may be added to, or removed from, the described processes. Accordingly, other implementations are within the scope of the following claims.