BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1(
a)-(g) are schematic diagrams showing the conventional process for fabricating the trench power MOSFET;
FIG. 2 is a schematic diagram showing partial structure of trench power MOSFET disclosed in a published patent application of US 2003/0168695A1;
FIGS. 3(
a)-(m) are schematic diagrams showing the process for fabricating the trench power semiconductor device according to a preferred embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
The present invention will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for purpose of illustration and description only; it is not intended to be exhaustive or to be limited to the precise form disclosed.
Please refer to FIGS. 3(a)-(m), which are schematic diagrams showing the process for fabricating the trench power semiconductor device according to a preferred embodiment of the present invention. In this embodiment, the trench power semiconductor device is preferably a trench power metal-oxide-semiconductor field effect transistor (trench power MOSFET) but not limited thereto, and the process comprises the following steps. Firstly, a substrate 311 is provided and a pad oxide layer 312, a first dielectric layer 313, and a mask oxide layer 314 are formed on the substrate 311 in order as shown in FIG. 3(a). In this embodiment, the substrate 311, the first dielectric layer 313, and the mask oxide layer 314 are preferably a silica substrate, a silicon nitride mask (mask SiN), and a Tetra Ethyl Ortho Silicate (TEOS), respectively, wherein the first dielectric layer 313 and the mask oxide layer 314 are preferably formed by chemical vapor deposition (CVD), but not limited thereto. The pad oxide layer 312 serves as a buffer to reduce the stress among the substrate 311, the first dielectric layer 313 and the mask oxide layer 314.
As shown in FIG. 3(b), photolithography and etching procedure are preformed subsequently to remove portion of the mask oxide layer 314, so as to define the trench opening 315 and expose portion of the first dielectric layer 313. The mask oxide layer 314 is provided as a mask to remove portion of the first dielectric layer 313, portion of the pad oxide layer 312, and portion of the substrate 311 via etching procedure such as isotropic etching in order to form a trench structure 316 (as shown in FIG. 3(c)). The mask oxide layer 314 is then removed and a sacrifice oxide layer (not shown) is formed through oxidation, such as thermal oxidation. The sacrifice oxide layer is removed afterwards. As shown in FIG. 3(d), a method such as thermal oxidation is performed to form a gate oxide layer 317 at the inner sidewall of the trench structure 316. Because the operation properties of the trench power MOSFET is affected by the thickness of the gate oxide layer 317, the thickness of the gate oxide layer 317 is controlled and regulated according to the requirement. After the formation of the gate oxide layer 317, a polysilicon layer 318 is deposited on the surface of the first dielectric layer 313 and fully deposited into the interior of trench structure 316, in other words, the trench structure 316 is covered by the polysilicon layer 318 as shown in FIG. 3(d).
As shown in FIG. 3(e), etching procedure such as dry etching is preferably applied to remove portion of the polysilicon layer 318 for forming the gate 3181 of the trench power MOSFET. Later, as shown in FIG. 3(f), the first dielectric layer 313 is removed to form the gate 3181 with a height higher than the trench structure 316 or the surface of the pad oxide layer 312. Body implantation procedure and body drive-in procedure are then processed onto the substrate 311 to form a body structure 319 within the substrate 311.
After body implantation and body drive-in procedures, a photoresist layer 320 is formed on the body structure 319 to define source photoresist by photolithography. Afterwards, source implantation procedure and source drive-in procedure are conducted to form a source 321 and then remove the photoresist layer 320. In this embodiment, the source 321 is preferably formed between the body structure 319 and the gate oxide layer 317.
Subsequently, deposition such as chemical vapor deposition is preferably applied to form an insulation layer 322 on top of the above-mentioned structure; meanwhile, an oxide layer 323 is naturally formed between the insulation layer 322 and the gate 3181 composed of polysilicon (as shown in FIG. 3(h)). Etching procedure such as dry etching is preferably utilized subsequently to remove portion of the insulation layer 322, portion of the pad oxide layer 312 and portion of the oxide layer 323, so as to form a sidewall structure 324 at two laterals of the gate 3181 protruded from the surface of the trench structure 316 and to expose portion of the source 321 and portion of the substrate 311, as shown in FIG. 3(i).
As shown in FIG. 3(j), salicidation procedure is conducted onto the above-mentioned structure to simultaneously form the first conductive layer 325 and 326 at the surface of the gate 3181 and portion structure of the source 321 and the substrate 311. In this embodiment, the first conductive layer 325 and 326 is preferably a low conductivity material, such as titanium silicide layer. Because the resistance of the titanium silicide layer is ⅕ of that of the polysilicon of the gate 3181, and the relationship between each gate 3181 shows in a parallel connection manner (not shown), the purpose for decreasing the net resistance of the gate 3181 can be achieved by the disposition of the titanium silicide layer. In this embodiment, due to the additional formation of the first dielectric layer 313 between the pad oxide layer 312 and the mask oxide layer 314, the gate 3181 with height higher than the surface of the pad oxide layer 312 can be obtained after the removal of the first dielectric layer 313. In addition, the isolation between the source 321 and the first conductive layer 325 on the surface of the gate 3181 can be further enhanced through the sidewall structure 324. Therefore, when the proposed trench power MOSFET of the present invention is processed at high frequency; the disposition of the first conductive layer 325 will not cause the poor isolation of the gate oxide layer 317 and thus short circuit between the gate 3181 and the source 321 can be further prevented.
As shown in FIG. 3(k), a second dielectric layer 327 is then formed on the above-mentioned structure by chemical vapor deposition, followed by forming a photoresist 330 on top of the second dielectric layer 327, and defining the contact region opening 331 by microlithography. In this embodiment, the second dielectric layer 327 preferably comprises two dielectric layers with different materials, wherein the applied layers are preferably non-doped-silicate-glass layer 328 (NSG layer) and borophospho-silicate-glass layer 329 (BPSG layer), but not limited thereto.
Afterwards, as shown in FIG. 3(l), portion of the second dielectric layer 327, portion of the first conductive layer 326, portion of the source 321, and portion of the body structure 319 are removed through the corresponding contact region opening 331, hence the source structure 3211 and the contact region 332 are defined, followed by the removal of the photoresist 330.
After the completion of the foregoing described procedures, implantation procedure is performed to form the contact plus structure 333 within the body structure 319 through the contact region 332, wherein the surface of the contact plus structure 333 is exposed through the contact region 332, as shown in FIG. 3(l). Moreover, a procedure such as sputtering process is preferably used to form the second conductive layer 334 on the surface of the structure shown in FIG. 3(l). In this embodiment, the second conductive layer 334 is preferably a titanium nitride layer (TiN layer), but not limited thereto. Later on, the contact metal layer 335 is deposited on the second conductive layer 334, wherein the contact metal layer 335 is preferably an aluminum-silicon-copper layer (AlSiCu layer), but not limited thereto. Furthermore, a protective layer 336 is formed on the contact metal layer 335 and photolithography and etching procedures are used to define the layouts (not shown) eventually, the trench power MOSFET as depicted in FIG. 3(m) is fabricated.
The trench power MOSFET according to a preferred embodiment of the present invention is shown in FIG. 3(m). The structure of transistor comprises: the substrate 311, the trench structure 316 (as shown in FIG. 3(c)), the pad oxide layer 312, the gate oxide layer 317, the gate 3181, the body structure 319, the oxide layer 323, the sidewall structure 324, the first conductive layer 325 and 326, the second dielectric layer 327, the contact plus structure 333, the second conductive layer 334, the source structure 3211, the contact metal layer 335, and the protective layer 336, but not limited thereto. The trench structure 316 is formed in the substrate 311, the gate oxide layer 317 is formed at the inner sidewall of the trench structure 316, and the gate 3181 is formed within the interior of the trench structure 316 and protruded from the surface of the trench structure 316. In addition, the sidewall structure 324 is formed at the laterals of the gate 3181 that protruded from the surface of the trench structure 316. The first conductive layer 325 and 326 is formed at the surface of the gate 3181 and the surface of partial source structure 3211. As regards the source structure 3211, it is formed within the substrate 311 and nearby the gate oxide layer 317.
In some embodiments, the gate 3181 is preferably a polysilicon layer, and the first conductive layer 325 and 326 is preferably a titanium silicide layer, but not limited thereto. In addition, the trench power MOSFET of the present invention further comprises a body structure 319 formed within substrate 311. Furthermore, the trench power MOSFET of the present invention can also comprise a dielectric layer 327 formed on the first conductive layer 325 and 326 and the sidewall structure 324.
In some other embodiments, the trench power MOSFET of the present invention can further comprise a contact plus structure 333 formed on the substrate 311 and a second conductive layer 334 formed on the dielectric layer 327 and the contact plus structure 333, but not limited thereto. Moreover, the trench power MOSFET of the present invention can also comprise a contact metal layer 335 and a protective layer 366 formed on the top of the second conductive layer 334, wherein the second conductive layer 334 is preferably but not limited to a titanium nitride layer (TiN layer).
In summary, the purpose of the present embodiment is to form an alternative first dielectric layer 313 between the pad oxide layer 312 and the mask oxide layer 314. Hence a gate 3181 with a height higher than the surface of the pad oxide layer 312 can be obtained after the removal of the first dielectric layer 313, and the source structure 3211 and the first conductive layer 325 formed at the surface of the gate 3181 can be isolated through the sidewall structure 324. When the trench power MOSFET of the present invention is processed at high frequency, the net resistance of the gate 3181 can be reduced by the first conductive layer 325, and thus the electrical properties of the trench power MOSFET can be elevated. Furthermore, through the isolation of the sidewall structure 324, the poor isolation of the gate oxide layer 317 with the disposition of the first conductive layer 325 can be avoided; therefore the voltage applied to the gate 3181 will not conduct to the source structure 3211 directly, and thus the possibility of short circuit between the gate 3181 and the source structure 3211 can also be prevented. In addition, the first conductive layer 326 formed at the source structure 3211 can also increase the contact area of source structure 3211.
While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.
Patent Application
20080035989
