Patent Application
20250031426
Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon.
The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. However, as the minimum features sizes are reduced, additional problems arise that should be addressed.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting.
For the sake of brevity, known techniques related to semiconductor device fabrication may not be described in detail herein. Moreover, the various tasks and processes described herein may be incorporated into a more comprehensive procedure or process having additional functionality not described in detail herein. In particular, various processes in the fabrication of semiconductor devices are well-known and so, in the interest of brevity, many processes will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details. As will be readily apparent to those skilled in the art upon a complete reading of the disclosure, the structures disclosed herein may be employed with a variety of technologies, and may be incorporated into a variety of semiconductor devices and products. Further, it is noted that semiconductor device structures include a varying number of components and that single components shown in the illustrations may be representative of multiple components.
Furthermore, spatially relative terms, such as “over”, “overlying”, “above”, “upper”, “top”, “under”, “underlying”, “below”, “lower”, “bottom”, and the like, may be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. When a spatially relative term, such as those listed above, is used to describe a first element with respect to a second element, the first element may be directly on the other element, or intervening elements or layers may be present. When an element or layer is referred to as being “on” another element or layer, it is directly on and in contact with the other element or layer.
In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
During semiconductor fabrication, topography of the device after chemical-mechanical planarization (CMP) is a key factor for determining integrated circuit performance and for determining manufacturing difficulty. Topography requirements may depend on layer (i.e., OD, PO, CPODE, CMG, and the like), layout (SRAM, RO, VBD, and the like), overlay mark, and other factors. Described herein are methods for manufacturing semiconductor devices with improved topography.
As described herein, a lower gate height generally leads to better integrated circuit performance, i.e., lower capacitance. However, lower gate heights may make manufacturing more difficult. Specifically, CMP processes may be prone to over-polishing. Herein, devices of various gate heights are distributed across a semiconductor die to improve device performance and device reliability.
Although two fins 105 are illustrated in
According to some embodiments, the first layers 205 may be formed using a first semiconductor material with a first lattice constant, such as SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, combinations of these, or the like. In some embodiments, a first layer 205 of the first semiconductor material (e.g., SiGe) is epitaxially grown on the substrate 201 using a deposition technique such as epitaxial growth, vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE), although other deposition processes, such as chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer CVD (ALCVD), ultrahigh vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), a combination thereof, or the like, may also be utilized. In some embodiments, the first layer 205 is formed to first thicknesses Th1 of between about 3 nm and about 10 nm. However, any suitable thickness may be utilized while remaining within the scope of the embodiments.
Once the first layer 205 has been formed over the substrate 201, a second layer 207 may be formed over the first layer 205. According to some embodiments, the second layers 207 may be formed using a second semiconductor material such as Si, SiGe, Ge, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, combinations of these, or the like with a second lattice constant that is different from the first lattice constant of the first layer 205. In a particular embodiment in which the first layer 205 is silicon germanium, the second layer 207 is a material such as silicon. However, any suitable combination of materials may be utilized for the first layers 205 and the second layers 207.
In some embodiments, the second layer 207 is epitaxially grown on the first layer 205 using a deposition technique similar to that used to form the first layer 205. However, the second layer 207 may use any of the deposition techniques suitable for forming the first layer 205, as set forth above or any other suitable technique. According to some embodiments, the second layer 207 is formed to a similar thickness to that of the first layer 205. However, the second layer 207 may also be formed to a thickness that is different from the first layer 205. According to some embodiments, the second layer 207 may be formed to a second thickness Th2 of between about 5 nm and about 15 nm. However, any suitable thickness may be used.
Once the second layer 207 has been formed over the first layer 205, the deposition process is repeated to form the remaining material layers in the series of alternating materials of the first layers 205 and the second layers 207 until a desired topmost layer of the multi-layer stack 203 has been formed. According to the present embodiment, the first layers 205 may be formed to a same or similar first thickness and the second layers 207 may be formed to the same or similar second thickness. However, the first layers 205 may have different thicknesses from one another and/or the second layers 207 may have different thicknesses from one another and any combination of thicknesses may be used for the first layers 205 and the second layers 207. According to the present embodiment, the topmost layer of the multi-layer stack 203 is formed as a second layer 207; however, in other embodiments, the topmost layer of the multi-layer stack 203 may be formed as a first layer 205. Additionally, although embodiments are disclosed herein comprising three of the first layers 205 and three of the second layers 207, the multi-layer stack 203 may have any suitable number of layers (e.g., nanosheets). For example, the multi-layer stack 203 may comprise multiple nanosheets in a range between 2 to 10 nanosheets. In some embodiments, the multi-layer stack 203 may comprise equal numbers of the first layers 205 to the second layers 207; however, in other embodiments, the number of the first layers 205 may be different from the number of the second layers 207. According to some embodiments, the multi-layer stack 203 may be formed to a first height H1 of between about 12 nm and about 100 nm. However, any suitable height may be used.
Additionally, while a single mask process has been described, this is intended to be illustrative and is not intended to be limiting, as the gate all around (GAA) device structures may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure.
In an embodiment the isolation regions 209 are formed as shallow trench isolation regions by depositing a dielectric material in the trenches. According to some embodiments, the dielectric material used to form the isolation regions 209 may be a material such as an oxide material (e.g., a flowable oxide), high-density plasma (HDP) oxide, or the like. The dielectric material may be formed, after an optional cleaning and lining of the trenches, using either a chemical vapor deposition (CVD) method (e.g., the HARP process), a high density plasma CVD method, or other suitable method of formation to fill or overfill the regions around the fins 105. In some embodiments, a post placement anneal process (e.g., oxide densification) is performed to densify the material of the isolation regions 209 and to reduce its wet etch rate. A chemical mechanical polishing (CMP), an etch, a combination of these, or the like may be performed to remove any excess material of the isolation regions 209.
Once the dielectric material has been deposited to fill or overfill the regions around the fins 105, the dielectric material may then be recessed away from the surface of the fins 105 to form the isolation regions 209. The recessing may be performed to expose at least a portion of the sidewalls of the fins 105 adjacent to the top surface of the fins 105. The dielectric material may be recessed using a wet etch by dipping the top surface of the fins 105 into an etchant selective to the material of the dielectric material, although other methods, such as a reactive ion etch, a dry etch, chemical oxide removal, or dry chemical clean may be used.
Turning to
In some embodiments, the dummy gate electrode 303 comprises a conductive material and may be selected from a group comprising of polysilicon, W, Al, Cu, AlCu, W, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations of these, or the like. The dummy gate electrode 303 may be deposited by chemical vapor deposition (CVD), sputter deposition, or other techniques known and used in the art for depositing conductive materials. The thickness of the dummy gate electrode 303 may be in the range of about 5 Å to about 500 Å. The top surface of the dummy gate electrode 303 may have a non-planar top surface, and may be planarized prior to patterning of the dummy gate electrode 303 or gate etch. Ions may or may not be introduced into the dummy gate electrode 303 at this point. Ions may be introduced, for example, by ion implantation techniques.
Once the dummy gate electrode 303 has been formed, the dummy gate dielectric 211 and the dummy gate electrode 303 may be patterned. In an embodiment the patterning may be performed by initially forming a first hard mask 305 over the dummy gate electrode 303 and forming the second hard mask 307 over the first hard mask 305.
According to some embodiments, the first hard mask 305 comprises a dielectric material such as silicon nitride (SiN), oxide (OX), silicon oxide (SiO), titanium nitride (TiN), silicon oxynitride (SiON), combinations of these, or the like. The first hard mask 305 may be formed using a process such as chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, or the like. However, any other suitable material and method of formation may be utilized. The first hard mask 305 may be formed to a thickness of between about 20 Å and about 3000 Å, such as about 20 Å.
The second hard mask 307 comprises a separate dielectric material from the material of the first hard mask 305. The second hard mask 307 may comprise any of the materials and use any of the processes suitable for forming the first hard mask 305 and may be formed to a same or similar thickness as the first hard mask 305. In embodiments where the first hard mask 305 comprises silicon nitride (SiN), the second hard mask 307 may be e.g., an oxide (OX). However, any suitable dielectric materials, processes and thicknesses may be used to form the second hard mask.
Once the first hard mask 305 and the second hard mask 307 have been formed, the first hard mask 305 and the second hard mask 307 may be patterned. In an embodiment the first hard mask 305 and the second hard mask 307 may be patterned by initially placing a photoresist (not individually illustrated) over the first hard mask 305 and the second hard mask 307 and exposing the photoresist to a patterned energy source (e.g., light) in order to initiate a chemical reaction that modifies the physical properties of the exposed portions of the first photoresist. The first photoresist may then be developed by applying a first developer (also not individually illustrated) in order to utilize the modified physical properties between the exposed region and the unexposed region to selectively remove either the exposed region or the unexposed region.
Once the photoresist has been patterned, the photoresist may be used as a mask in order to pattern the underlying first hard mask 305 and the second hard mask 307. In an embodiment the first hard mask 305 and the second hard mask 307 may be patterned using, e.g., one or more reactive ion etching (RIE) processes with the photoresist as a mask. The patterning process may be continued until the dummy gate electrode 303 is exposed beneath the first hard mask 305.
Once the first hard mask 305 and the second hard mask 307 have been patterned, the photoresist may be removed utilizing, e.g., an ashing process, whereby a temperature of the photoresist is raised until the photoresist experiences a thermal decomposition and may be easily removed using one or more cleaning process. However, any other suitable removal process may be utilized.
Once the first hard mask 305 and the second hard mask 307 have been patterned, the dummy gate electrode 303 and the dummy gate dielectric 211 may be patterned in order to form a series of dummy gate stacks 301. In an embodiment the dummy gate electrode 303 and the dummy gate dielectric 211 are patterned using an anisotropic etching process, such as a reactive ion etch, although any suitable process may be utilized.
Once formed, the spacer material may be etched in order to shape the top spacers 309 on the dummy gate stacks 301 and the fins 105 to expose the tops of the dummy gate stacks 301 and fins 105. According to some embodiments, the spacer material may be etched using an anisotropic etching process (e.g., a dry etching process) such as a reactive ion etching (RIE) process, an isotropic etching process (e.g., a wet etching process), combination thereof, or the like. In some embodiments, the spacer material formed over the fins 105 in source/drain regions may be recessed during the etching process and/or during a subsequent etching process such that portions along the sidewalls of the fins 105 in those source/drain regions are exposed.
However, while embodiments are described using a single spacer material, this is intended to be illustrative and is not intended to be limiting. Rather, any number of spacer materials and any combinations of deposition and removal processes may be used, and all such processes are fully intended to be included within the scope of the embodiments.
In an embodiment, the first openings 401 may be formed to have a first width W1 of between about 10 nm and about 40 nm, such as about 20 nm. Additionally, the first openings 401 may be formed to extend into the substrate 201 a first depth D1 of between about 3 nm and about 40 nm, such as about 10 nm. However, any suitable dimensions may be utilized.
In an embodiment the wet etching process may be a dip process, a spray process, a spin-on process, or the like and may be performed using any suitable process temperatures (e.g., between about 400° C. and about 600° C.) and any suitable process times (e.g., between about 100 seconds and about 1000 seconds, such as about 300 seconds). However, any suitable process conditions and parameters may be utilized. The etching process may be continued such that recesses with facet limited surfaces are formed in each of the first layers 205 to any desired distance from the sidewall of the first openings 401.
Additionally, the selectivity of the etchant may be chosen. According to some embodiments, the etching process may also be performed to remove portions of the second layers 207 and the substrate 201 such that a size of the recesses extends vertically in the direction of the sidewall of the first openings 401 to any suitable height (described further below).
However, a wet etching process is not the only process that may be utilized to recess the first layers 205. For example, in another embodiment the recessing of the first layers 205 may be performed with an isotropic dry etching process or a combination of a dry etching process and a wet etching process. Any suitable process of recessing the first layers 205 may be utilized, and all such processes are fully intended to be included within the scope of the embodiments.
Once the recesses are formed in each of the first layers 205, a spacer material is formed over the multi-layer structure 103. In some embodiments, the spacer material can be different from the material of the top spacers 309 and can be a dielectric material comprising silicon such as silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), although any suitable material such as low-k materials with a k-value less than about 4.0, or even an air gap, or combination thereof may also be utilized. The spacer material may be deposited using a deposition process such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition to a thickness of between about 2 nm and about 10 nm, such as about 5 nm. However, any suitable thickness or deposition process may be utilized.
By depositing the spacer material over the 103, the spacer material will line the sidewalls of the first openings 401 and will also fill in the recesses in the first layers 205. Once the recesses have been filled with the spacer material, a removal process is then performed to remove any excess spacer material from the first openings 401, while leaving behind the inner spacers 403. In an embodiment, the removal of the excess spacer material may be performed using an etching process such as, e.g., an anisotropic, dry etching process such as a reactive ion etching process. However, any suitable etching process, which removes the excess spacer material from the first openings 401 while leaving behind the inner spacers 403, may be utilized.
By filling the recesses with the spacer material and removing the excess spacer material from the first openings 401, the inner spacers 403 will take on the shape of the recesses. Additionally, while an embodiment forming the inner spacers 403 to faceted shapes is described, this is intended to be illustrative and is not intended to be limited. Rather, any suitable shape, such as a concave shape or a convex shape, or even the inner spacers 403 being recessed may be utilized. All such shapes are fully intended to be included within the scope of the embodiments. According to some embodiments, the inner spacers 403 may be formed to a second width W2 of between about 2 nm and about 10 nm, such as about 5 nm and a second height H2 of between about 5 nm and about 20 nm, such as about 10 nm. Furthermore, the inner spacers 403 may be spaced apart by a first spacing S1 of between about 3 nm and about 10 nm, such as about 5 nm. However, any suitable widths, heights, and distances may be utilized.
Once the inner spacers 403 have been formed, the bottom spacers 501 are formed at the bottom of the first openings 401 using a semiconductor material, such as silicon germanium (SiGe), although other suitable materials such as those suitable for forming the first layers 205 may also be utilized. According to some embodiments, the bottom spacers 501 are formed using SiGe and are epitaxially grown at the bottom of the first openings 401 using a deposition technique such as epitaxial growth, vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE). However, any other deposition process suitable for forming the first layers 205 may also be used.
Once deposited, an oxidation process may be performed to increase a density, and/or a dielectric constant of the bottom spacers 501. As such, the bottom spacers 501 may be formed as silicon germanium oxide (e.g., SiGeOx, SiGeON, SiGeOCN, or the like). After the oxidation process, an etching process (e.g., wet etch) may be performed to remove any oxide formed along sidewalls of the first openings 401 and/or to recess the bottom spacers 501 to a desired height. According to some embodiments, the bottom spacers 501 are formed to a third height H3 of between about 3 nm and about 30 nm, such as about 20 nm. However, any suitable height may be used.
Once the bottom spacers 501 have been formed to the desired height, a post placement anneal process may be performed to remove the germanium (Ge) from the material of the bottom spacers 501. According to some embodiments, the anneal process may comprise one or more anneal processes (e.g., a steam anneal, a high temperature anneal, combinations, or the like) can be performed in a furnace or in a rapid thermal processing (RTP) chamber. According to some embodiments, the post placement anneal process comprises a dry anneal using, for example, nitrogen (N2) at a process temperature in a range from between about 500° C. and about 700° C., such as about 600° C. for a duration of between about 30 minutes and about 180 minutes, such as about 60 min. However, any suitable oxygen sources, process temperatures, and process times may be utilized. Once the post placement anneal process has completed, the germanium has been removed and the bottom spacers 501 are transformed into a dielectric material such as, silicon nitride (SiN), oxide (OX), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), or the like).
In some other embodiments, the bottom spacers 501 may be formed by depositing a second spacer material such as SiON using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), or the like. However, any suitable spacer material and deposition process may be used such as those materials and processes suitable for forming the top spacers 309. According to some embodiments, the second spacer material is different from the material of the top spacers 309 and the inner spacers 403 and is deposited to fill and/or overfill the first openings 401.
Once deposited, the second spacer material may be etched in order to recess the bottom spacers 501 to the desired third height H3 and to expose the sidewalls in the first openings 401 above the bottom spacers 501. According to some embodiments, the second spacer material may be etched using an anisotropic etching process (e.g., a dry etching process) such as a reactive ion etching (RIE) process, an isotropic etching process (e.g., a wet etching process), combination thereof, or the like. The etchants used to recess the bottom spacers 501 are selective to the second spacer material without significantly removing the materials of the top spacers 309, the second layers 207, and the inner spacers 403.
Once the bottom spacers 501 have been formed, the source/drain regions 503 may be formed over the bottom spacers 501. The source/drain regions 503 may be formed using a growth process such as a selective epitaxial process with a semiconductor material suitable for the device desired to be formed. For example, in an embodiment in which the source/drain regions 503 are utilized to form an NMOS device, the source/drain regions 503 may be a semiconductor material such as silicon, silicon phosphorous, silicon carbon phosphorous, combinations, of these, or the like.
The epitaxial growth process may use precursors such as silane, dichlorosilane, germane, and the like, and may continue for between about 5 minutes and about 120 minutes, such as about 30 minutes. According to some embodiments, the source/drain regions 503 are formed to a fourth height H4 of between about 30 nm and about 90 nm, such as about 50 nm. However, any suitable heights and/or suitable depths may be used.
Once the source/drain regions 503 are formed, dopants may be implanted into the source/drain regions 503 by implanting appropriate dopants to complement the dopants within the remainder of the first device region. For example, n-type dopants such as phosphorous (P), carbon (C), arsenic (As), silicon (Si), antimony (Sb), or the like, and combinations thereof (e.g., SiP, SiC, SiPC, SiAs, Si, Sb, etc.) may be implanted to form NMOSFET devices. These dopants may be implanted using the dummy gate stacks 301 and the top spacers 309 as masks.
In another embodiment, the dopants of the source/drain regions 503 may be placed during the growth of the source/drain regions 503. For example, phosphorous may be placed in situ as the source/drain regions 503 are being formed. Any suitable process for placing the dopants within the source/drain regions 503 may be utilized, and all such processes are fully intended to be included within the scope of the embodiments. Furthermore, an anneal process may be performed to activate the dopants within the source/drain regions 503. During the anneal process, dopants of the source/drain regions 503 may laterally diffuse into the second layers 207 at the interfaces between the second layers 207 and the source/drain regions 503. As such, lightly doped drain (LDD) regions may be formed within the second layers 207.
The contact etch stop layer 601 is formed over the structure illustrated in
The interlayer dielectric layer 603 may comprise a material such as silicon dioxide, a low-k dielectric material (e.g., a material having a dielectric constant lower than silicon dioxide), such as silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), organosilicate glasses (OSG), SiOxCy, Spin-On-Glass, Spin-On-Polymers, silicon carbon material, a compound thereof, a composite thereof, the like, or a combination thereof, although any suitable dielectrics may be used. The interlayer dielectric layer 603 may be formed using a process such as plasma enhanced chemical vapor deposition (PECVD), although other processes, such as low pressure chemical vapor deposition (LPCVD), may also be used.
Once formed, the interlayer dielectric layer 603 and the contact etch stop layer 601 may be planarized with the dummy gate electrode 303 and top spacers 309 using a planarization process such as chemical mechanical planarization (CMP). However, any suitable planarization process may be utilized. Furthermore, the first hard mask 305 and the second hard mask 307 may be removed during the planarization process. According to some embodiments, one or more etching processes and/or the chemical mechanical planarization (CMP) may be utilized to remove the first hard mask 305 and the second hard mask 307. As such, the dummy gate electrode 303 is exposed after the removal of the first hard mask 305.
Once exposed, the dummy gate electrode 303 may be removed in order to expose the underlying dummy gate dielectric 211. In an embodiment the dummy gate electrode 303 is removed using, e.g., one or more wet or dry etching process that utilizes etchants that are selective to the material of the dummy gate electrode 303. However, any suitable removal process may be utilized.
Once the dummy gate dielectric 211 has been exposed, the dummy gate dielectric 211 may be removed. In an embodiment the dummy gate dielectric 211 may be removed using, e.g., a wet etching process, although any suitable etching process may be utilized.
For example, in an embodiment, an etchant such as a high temperature HCl may be used to selectively remove the material of the first layers 205 (e.g., SiGe) without substantively removing the material of the substrate 201 and/or the material of the second layers 207 (e.g., Si). Additionally, the wet etching process may be performed at a temperature of between about 400° C. and about 600° C., such as about 560° C., and for a time of between about 100 seconds and about 600 seconds, such as about 300 seconds. However, any suitable etchant, process parameters, and time can be utilized.
By removing the material of the first layers 205, the sides of the second layers 207 (relabeled nanostructures 701 in
In some embodiments, the wire release step may include an optional step for the partial removal of the material of the second layers 207 (e.g., by over etching) during removal of the first layers 205. As such, the thicknesses of the nanostructures 701 are formed to have reduced thicknesses as compared to the original thickness of the second layers 207. As such, the nanostructures 701 may have third thicknesses Th3 that are less than the thicknesses of the original second layers 207 (e.g., second thicknesses Th2). Furthermore, during such a partial removal, the top spacers 309, the inner spacers 403 may serve to protect adjacent material of the second layers 207 from being removed. As such, the thicknesses of the nanostructures 701 at distal end portions of the nanostructures 701 are protected during the wire release step and are not further reduced.
Additionally, although
The capping layer may be formed adjacent to the gate dielectric 703 and may be formed from a metallic material such as TaN, Ti, TiAlN, TiAl, Pt, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, oxynitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, combinations of these, or the like. The metallic material may be deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, or the like, although any suitable deposition process may be used.
The barrier layer may be formed adjacent the capping layer, and may be formed of a material different from the capping layer. For example, the barrier layer may be formed of a material such as one or more layers of a metallic material such as TiN, TaN, Ti, TiAlN, TiAl, Pt, TaC, TaCN, TaSiN, Mn, Zr, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, oxynitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, combinations of these, or the like. The barrier layer may be deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, or the like, although any suitable deposition process may be used.
The n-metal work function layer may be formed adjacent to the barrier layer. In an embodiment the n-metal work function layer is a material such as W, Cu, AlCu, TiAlC, TiAlN, TiAl, Pt, Ti, TiN, Ta, TaN, Co, Ni, Ag, Al, TaAl, TaAlC, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. For example, the first n-metal work function layer may be deposited utilizing an atomic layer deposition (ALD) process, CVD process, or the like. However, any suitable materials and processes may be utilized to form the n-metal work function layer.
The p-metal work function layer may be formed adjacent to the n-metal work function layer. In an embodiment, the first p-metal work function layer may be formed from a metallic material such as W, Al, Cu, TiN, Ti, TiAlN, TiAl, Pt, Ta, TaN, Co, Ni, TaC, TaCN, TaSiN, TaSi2, NiSi2, Mn, Zr, ZrSi2, TaN, Ru, AlCu, Mo, MoSi2, WN, other metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, oxynitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, combinations of these, or the like. Additionally, the p-metal work function layer may be deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, or the like, although any suitable deposition process may be used.
Once the p-metal work function layer has been formed, the fill material is deposited to fill a remainder of the opening. In an embodiment the fill material may be a material such as tungsten, Al, Cu, AlCu, W, Ti, TiAlN, TiAl, Pt, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations of these, or the like, and may be formed using a deposition process such as plating, chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations of these, or the like. However, any suitable material may be utilized.
Once the openings left behind by the removal of the dummy gate electrode 303 have been filled, the materials of the gate electrode 107 and the gate dielectric 703 may be planarized in order to remove any material that is outside of the openings left behind by the removal of the dummy gate electrode 303. In a particular embodiment the removal may be performed using a planarization process such as chemical mechanical polishing, although any suitable planarization and removal process may be utilized. According to some embodiments, the gate electrodes may be formed to a fifth length L5 of between about 8 nm and about 30 nm. However, any suitable length may be used.
Once formed, the gate electrodes 107 may be recessed below the planarized surfaces of the interlayer dielectric layer 603. According to some embodiments, the gate electrodes 107 may be recessed using an etching process such as a wet etch, a dry etch, combinations, or the like. Once recessed, the height of the gate electrodes 107 above a topmost one of the nanostructure 701 is a fifth height H5. According to some embodiments, the fifth height H5 is between about 8 nm and about 30 nm. However, any suitable height may be used.
The gate caps 801 may be formed by initially depositing a dielectric material over the gate electrodes 107 to fill and/or overfill the recesses. In some embodiments, the gate caps 801 are formed using a dielectric material such as a silicon nitride (SiN), oxide (OX), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), or the like. According to some embodiments, the gate caps 801 are formed using a metal oxide of materials such as zirconium (Zr), hafnium (Hf), aluminum (Al), or the like. Furthermore, the gate caps 801 may be formed using a suitable deposition process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), combinations of these, or the like. However, any suitable materials and deposition processes may be utilized. Once deposited, the gate caps 801 may be planarized with the interlayer dielectric layer 603 using a planarization process such as a chemical mechanical polishing process. Once planarized, the gate caps 801 have a sixth height H6 of between about 10 nm and about 30 nm. However, any suitable height may be used.
Once patterned, the masking layer 903 is used as an etching mask to etch the underlying materials to form the second openings 901 (e.g., trenches, recesses, channels or the like). In the etching process, the materials of the gate caps 801 and the gate electrodes 107 are etched using an anisotropic etching process, and may stop on the top surface of the gate dielectric 703 or the top surface of the isolation regions 209. The second openings 901 may be formed between adjacent ones of the fins 105 and may be formed to cut through one or more gate electrodes 107. According to some embodiments, two of the second openings 901 are formed to cut through two adjacent ones of the gate electrodes 107 and are located on opposite sides of one of the fins 105, as shown in
The cut-metal gate structures 109 divide the two gate electrodes 107 which are relatively long into a plurality of gate electrodes 107 which are relatively short and isolate the plurality of gate electrodes 107 from one another. Furthermore, the excess dielectric material of the cut-metal gate structures 109 outside of the second openings 901 may be retained and used as a masking layer in the Continuous Poly On Diffusion Edge (CPODE) process. As such, the cut-metal gate structures 109 are highlighted with a dashed line in
Once the cut-metal gate structures 109 have been formed, a photo resist may be formed over the excess dielectric material and openings may be formed in the photo resist in a desired location of the CPODE structure 111 to be formed. The opening in the photo resist is formed to reveal a portion of the gate cap 801 between the two cut-metal gate structures 109. Furthermore, edge portions of the cut-metal gate structures 109 may also be exposed through the openings in the photo resist in order to provide some process margin for the CPODE structure 111. According to some embodiments, the width of the exposed edge portions may be a fourth width W4 of between about 3 nm and about 25 nm, such as about 5 nm. However, any suitable width may be used.
The photo resist is then used as an etching mask to etch the excess dielectric material, edge portions of the cut-metal gate structures 109, the gate cap 801, and the gate electrode 107, so that the third opening 1003 (e.g., trenches, recesses, channels or the like) is formed in the desired location of the CPODE structure 111. According to some embodiments, the etching process may stop on the gate dielectric 703. As a result, the gate dielectric 703 and the nanostructures 701 remain at the bottom of the third opening 1003. According to some embodiments, the etching process used to form the third opening 1003 may be an isotropic etching process (e.g., a wet etching process) using etchants that stop on the gate dielectric 703. However, other suitable etching process including anisotropic etching processes (e.g., a dry etching processes or reactive ion etching (RIE) processes), combinations of isotropic and anisotropic etches, or the like may also be used. According to some embodiments, the third opening 1003 is formed to a fifth width W5 of between about 20 nm and about 200 nm, such as about 70 nm. However, any suitable width may be used.
Once the nanostructures 701 and a portion of the fin 105 protruding above the isolation regions 209 are exposed, a further etching process may be used to remove the materials of the nanostructures 701 and to form the recess within the fin 105. According to some embodiments, an etching process such as a wet etch, a dry etch, combinations, or the like may be used to remove these materials without substantially removing the materials of the top spacers 309, the inner spacers 403, and the isolation regions 209 the third opening 1003. According to an embodiment, the portion of the fin 105 protruding above the isolation regions 209 may be recessed a second depth D2 of between about 2 nm and about 20 nm, such as about 10 nm. However, any suitable depth may be used. According to some embodiments, a first ratio R1 of the second depth D2 to the third height H3 of the bottom spacer 501 may be between about 0.05:1 and about 1:1. Once the nanostructures 701 have been removed and the portion of the fin 105 protruding above the isolation regions 209 has been recessed, the photo resist may be removed, for example, via an ashing process.
Once formed, the excess material of the CPODE structure 111 outside of the third opening 1003 may be removed by a chemical mechanical planarization (CMP) process. According to some embodiments, the chemical mechanical planarization (CMP) process may be continued to planarize the surfaces of the CPODE structure 111 with the gate electrode 107 and the interlayer dielectric layer 603. Once planarized, the CPODE structure 111 over the fin 105 has a seventh height H7 of between about 55 nm and about 140 nm, such as about 70 nm. However, any suitable height may be used. The gate caps 801 have an eighth height H8 of between about 10 nm and about 30 nm, such as about 15 nm. However, any suitable height may be used. Furthermore, the cut-metal gate structures 109 have a ninth height H9 of between about 50 nm and about 120 nm, such as about 60 nm. However, any suitable height may be used.
The method for fabricating the semiconductor device may continue, such as with forming source/drain contacts to the source/drain regions, forming a second ILD layer, forming source/drain vias and gate vias, through the second ILD layer to provide electrical connectivity to the source/drain regions and gate electrodes, in accordance with some embodiments.
Methods herein provide for gate height distribution optimization. Post CMP topography is one of the key factors that determines the IC performance and manufacture difficulty. Topography requirements depend on layer (i.e., OD/PO/CPODE/CMG, etc.), layout (SRAM/RO/VBD, etc.), lithography, overlay mark and so on. An optimized topography distribution may meet all topography requirements to achieve the best performance/yield.
For example, for the gate height, i.e., the final gate height after the CMP process for polishing the CPODE structure 111 over the fin 105, lower gate height leads to better IC performance (lower capacitance), but it also make manufacturing harder (i.e., CMP prone to overpolish). An optimized gate height distribution balances performance and reliability.
Referring to
Further, In
In each case, the gate 807 extends from a lowest surface 806, such as at an interface with the layer 207 or fin 105, to an uppermost surface 808, which may be formed by the post-CPODE CMP process. As shown, the lowest surface 806 and uppermost surface 808 are separated by gate height H14.
The gate height H14 may vary depending on the device gate length. Further, devices having different gate lengths are fabricated on a semiconductor die. For example, the die may include devices having gate lengths of 3 nanometers (nm), 9 nanometers (nm), 55 nanometers (nm), and 135 nanometers (nm).
Further,
In various embodiments, the minimum height of devices having a particular gate length are located in such devices in the corners 1605 of the die 1600.
In certain embodiments, a semiconductor die 1600 has a total number of devices having a gate length of 3 nanometers. Of the total number of devices having a gate length of 3 nanometers, more than 95% have a gate height H14 of from 10 to 14 nanometers (nm). For example, of the total number of devices having a gate length of 3 nanometers, more than 96%, more than 97%, more than 98%, more than 98.5%, more than 98.8%, more than 98.9%, more than 99%, more than 99.1%, or 99.15% have a gate height H14 of from 10 to 14 nanometers (nm). Further, of the total number of devices having a gate length of 3 nanometers, less than 99.9%, less than 99.8%, less than 99.7%, less than 99.6%, less than 99.5%, less than 99.4%, less than 99.3%, less than 99.2%, or 99.15% have a gate height H14 of from 10 to 14 nanometers (nm).
Further, of the total number of devices having a gate length of 3 nanometers, more than 0.2% have a gate height H14 of greater than 14 nanometers (nm). For example, of the total number of devices having a gate length of 3 nanometers, more than 0.3%, more than 0.4%, more than 0.5%, more than 0.55%, more than 0.6%, or 0.65% have a gate height H14 of greater than 14 nanometers (nm). Further, of the total number of devices having a gate length of 3 nanometers, less than 1%, less than 0.9%, less than 0.8%, less than 0.75%, less than 0.7%, or 0.65% have a gate height H14 of greater than 14 nanometers (nm).
In some embodiments, of the total number of devices having a gate length of 3 nanometers, the maximum gate height H14 is at least 16 nm, at least 16.5 nm, at least 17 nm, at least 17.5 nm, at least 18 nm, at least 18.1 nm, at least 18.2 nm, at least 18.3 nm, or at least 18.4 nm. In some embodiments, of the total number of devices having a gate length of 3 nanometers, the maximum gate height H14 is no more than 21 nm, no more than 20.5 nm, no more than 20 nm, no more than 19.5 nm, no more than 19 nm, no more than 18.9 nm, no more than 18.8 nm, no more than 18.7 nm, no more than 18.6 nm, no more than 18.5 nm, or no more than 18.4 nm. In certain embodiments, of the total number of devices having a gate length of 3 nanometers, the maximum gate height H14 is 18.4 nm.
Further, of the total number of devices having a gate length of 3 nanometers, more than 0.05% have a gate height H14 of less than 10 nanometers (nm). For example, of the total number of devices having a gate length of 3 nanometers, more than 0.1%, more than 0.12%, more than 0.14%, more than 0.16%, more than 0.18%, or 0.2% have a gate height H14 of less than 10 nanometers (nm). Further, of the total number of devices having a gate length of 3 nanometers, less than 1%, less than 0.8%, less than 0.6%, less than 0.5%, less than 0.4%, less than 0.35%, less than 0.3%, less than 0.25%, or 0.2% have a gate height H14 of less than 10 nanometers (nm).
In some embodiments, of the total number of devices having a gate length of 3 nanometers, the minimum gate height H14 is at least 4 nm, at least 4.5 nm, at least 5 nm, at least 5.2 nm, at least 5.4 nm, at least 5.6 nm, at least 5.8 nm, at least 6 nm, or at least 6.2 nm. In some embodiments, of the total number of devices having a gate length of 3 nanometers, the minimum gate height H14 is no more than 10 nm, no more than 9 nm, no more than 8.5 nm, no more than 8 nm, no more than 7.5 nm, no more than 7 nm, no more than 6.8 nm, no more than 6.6 nm, no more than 6.4 nm, or no more than 6.2 nm. In certain embodiments, of the total number of devices having a gate length of 3 nanometers, the minimum gate height H14 is 6.2 nm.
In certain embodiments, a semiconductor die 1600 has a total number of devices having a gate length of 9 nanometers. Of the total number of devices having a gate length of 9 nanometers, more than 90% have a gate height H14 of from 10 to 13 nanometers (nm). For example, of the total number of devices having a gate length of 9 nanometers, more than 91%, more than 92%, more than 93%, more than 94%, more than 94.2%, more than 94.4%, more than 94.5%, more than 94.6%, or 94.7% have a gate height H14 of from 10 to 13 nanometers (nm). Further, of the total number of devices having a gate length of 9 nanometers, less than 99%, less than 98%, less than 97%, less than 96%, less than 95%, less than 94.9%, less than 94.8%, or 94.7% have a gate height H14 of from 10 to 13 nanometers (nm).
Further, of the total number of devices having a gate length of 9 nanometers, more than 2% have a gate height H14 of greater than 13 nanometers (nm). For example, of the total number of devices having a gate length of 9 nanometers, more than 2.5%, more than 3%, more than 3.2%, more than 3.4%, more than 3.6%, or 3.8% have a gate height H14 of greater than 13 nanometers (nm). Further, of the total number of devices having a gate length of 9 nanometers, less than 6%, less than 5.5%, less than 5%, less than 4.8%, less than 4.6%, less than 4.4%, less than 4.2%, less than 4.1%, less than 4%, less than 3.9%, or 3.8% have a gate height H14 of greater than 13 nanometers (nm).
In some embodiments, of the total number of devices having a gate length of 9 nanometers, the maximum gate height H14 is at least 16 nm, at least 16.5 nm, at least 17 nm, at least 17.1 nm, at least 17.2 nm, at least 17.3 nm, or at least 17.4 nm. In some embodiments, of the total number of devices having a gate length of 9 nanometers, the maximum gate height H14 is no more than 21 nm, no more than 20 nm, no more than 19 nm, no more than 18.5 nm, no more than 18 nm, no more than 17.9 nm, no more than 17.8 nm, no more than 17.7 nm, no more than 17.6 nm, no more than 17.5 nm, or no more than 17.4 nm. In certain embodiments, of the total number of devices having a gate length of 9 nanometers, the maximum gate height H14 is 17.4 nm.
Further, of the total number of devices having a gate length of 9 nanometers, more than 0.5% have a gate height H14 of less than 10 nanometers (nm). For example, of the total number of devices having a gate length of 9 nanometers, more than 0.75%, more than 1%, more than 1.1%, more than 1.2%, more than 1.3%, more than 1.4%, or 1.5% have a gate height H14 of less than 10 nanometers (nm). Further, of the total number of devices having a gate length of 9 nanometers, less than 3%, less than 2.75%, less than 2.5%, less than 2.25%, less than 2%, less than 1.9%, less than 1.8%, less than 1.7%, less than 1.6%, or 1.5% have a gate height H14 of less than 10 nanometers (nm).
In some embodiments, of the total number of devices having a gate length of 9 nanometers, the minimum gate height H14 is at least 4 nm, at least 5 nm, at least 6 nm, at least 6.5 nm, at least 7 nm, at least 7.5 nm, at least 7.6 nm, at least 7.7 nm, at least 7.8 nm, at least 7.9 nm, at least 8 nm, or at least 8.1 nm. In some embodiments, of the total number of devices having a gate length of 9 nanometers, the minimum gate height H14 is no more than 10 nm, no more than 9.5 nm, no more than 9 nm, no more than 8.9 nm, no more than 8.8 nm, no more than 8.7 nm, no more than 8.6 nm, no more than 8.5 nm, no more than 8.4 nm, no more than 8.3 nm, no more than 8.2 nm, or no more than 8.1 nm. In certain embodiments, of the total number of devices having a gate length of 9 nanometers, the minimum gate height H14 is 8.1 nm.
In certain embodiments, a semiconductor die 1600 has a total number of devices having a gate length of 55 nanometers. Of the total number of devices having a gate length of 55 nanometers, more than 90% have a gate height H14 of from 14 to 19 nanometers (nm). For example, of the total number of devices having a gate length of 55 nanometers, more than 90.5%, more than 91%, more than 91.5%, more than 92%, more than 92.2%, more than 92.4%, more than 92.6%, more than 92.8%, more than 92.9%, or 93% have a gate height H14 of from 14 to 19 nanometers (nm). Further, of the total number of devices having a gate length of 55 nanometers, less than 99%, less than 98%, less than 97%, less than 96%, less than 95%, less than 94.5%, less than 94%, less than 93.75%, less than 93.5%, less than 93.25%, or 93% have a gate height H14 of from 14 to 19 nanometers (nm).
Further, of the total number of devices having a gate length of 55 nanometers, more than 2% have a gate height H14 of greater than 19 nanometers (nm). For example, of the total number of devices having a gate length of 55 nanometers, more than 2.5%, more than 2.75%, more than 3%, more than 3.1%, more than 3.2%, more than 3.3%, more than 3.4%, or 3.5% have a gate height H14 of greater than 19 nanometers (nm). Further, of the total number of devices having a gate length of 55 nanometers, less than 6%, less than 5%, less than 4.5%, less than 4%, less than 3.9%, less than 3.8%, less than 3.7%, less than 3.6%, or 3.5% have a gate height H14 of greater than 19 nanometers (nm).
In some embodiments, of the total number of devices having a gate length of 55 nanometers, the maximum gate height H14 is at least 16 nm, at least 17 nm, at least 18 nm, at least 19 nm, at least 19.5 nm, at least 20 nm, at least 20.5 nm, at least 21 nm, at least 21.1 nm, at least 21.2 nm, at least 21.3 nm, at least 21.4 nm, at least 21.5 nm, or at least 21.6 nm. In some embodiments, of the total number of devices having a gate length of 55 nanometers, the maximum gate height H14 is no more than 24 nm, no more than 23 nm, no more than 22.5 nm, no more than 22 nm, no more than 21.9 nm, no more than 21.8 nm, no more than 21.7 nm, or no more than 21.6 nm. In certain embodiments, of the total number of devices having a gate length of 55 nanometers, the maximum gate height H14 is 21.6 nm.
Further, of the total number of devices having a gate length of 55 nanometers, more than 1% have a gate height H14 of less than 14 nanometers (nm). For example, of the total number of devices having a gate length of 55 nanometers, more than 1.5%, more than 2%, more than 2.5%, more than 3%, more than 3.5%, more than 3.75%, more than 4%, more than 4.25%, or 4.5% have a gate height H14 of less than 14 nanometers (nm). Further, of the total number of devices having a gate length of 55 nanometers, less than 8%, less than 7%, less than 6%, less than 5.5%, less than 5%, less than 4.9%, less than 4.8%, less than 4.7%, less than 4.6%, or 4.5% have a gate height H14 of less than 14 nanometers (nm).
In some embodiments, of the total number of devices having a gate length of 55 nanometers, the minimum gate height H14 is at least 6 nm, at least 7 nm, at least 8 nm, at least 9 nm, at least 9.5 nm, at least 10 nm, at least 10.5 nm, at least 10.6 nm, at least 10.7 nm, at least 10.8 nm, at least 10.9 nm, at least 11 nm, or at least 11.1 nm. In some embodiments, of the total number of devices having a gate length of 55 nanometers, the minimum gate height H14 is no more than 15 nm, no more than 14 nm, no more than 13 nm, no more than 12.5 nm, no more than 12 nm, no more than 11.9 nm, no more than 11.8 nm, no more than 11.7 nm, no more than 11.6 nm, no more than 11.5 nm, no more than 11.4 nm, no more than 11.3 nm, no more than 11.2 nm, or no more than 11.1 nm. In certain embodiments, of the total number of devices having a gate length of 55 nanometers, the minimum gate height H14 is 11.1 nm.
In certain embodiments, a semiconductor die 1600 has a total number of devices having a gate length of 135 nanometers. Of the total number of devices having a gate length of 135 nanometers, more than 85% have a gate height H14 of from 16 to 19 nanometers (nm). For example, of the total number of devices having a gate length of 135 nanometers, more than 88%, more than 89%, more than 90%, more than 90.5%, more than 91%, more than 91.2%, more than 91.4%, more than 91.5%, more than 91.6%, more than 91.7%, or 91.8% have a gate height H14 of from 16 to 19 nanometers (nm). Further, of the total number of devices having a gate length of 135 nanometers, less than 98%, less than 96%, less than 94%, less than 93%, less than 93.5%, less than 93%, less than 92.5%, less than 92.4%, less than 92.3%, less than 92.2%, less than 92.1%, less than 92%, less than 91.9%, or 91.8% have a gate height H14 of from 16 to 19 nanometers (nm).
Further, of the total number of devices having a gate length of 135 nanometers, more than 2% have a gate height H14 of greater than 19 nanometers (nm). For example, of the total number of devices having a gate length of 135 nanometers, more than 2.5%, more than 2.75%, more than 3%, more than 3.1%, more than 3.2%, more than 3.3%, more than 3.4%, or 3.5% have a gate height H14 of greater than 19 nanometers (nm). Further, of the total number of devices having a gate length of 135 nanometers, less than 6%, less than 5%, less than 4.5%, less than 4%, less than 3.9%, less than 3.8%, less than 3.7%, less than 3.6%, or 3.5% have a gate height H14 of greater than 19 nanometers (nm).
In some embodiments, of the total number of devices having a gate length of 135 nanometers, the maximum gate height H14 is at least 16 nm, at least 17 nm, at least 18 nm, at least 19 nm, at least 19.5 nm, at least 20 nm, at least 20.1 nm, at least 20.2 nm, at least 20.3 nm, at least 20.4 nm, or at least 20.5 nm. In some embodiments, of the total number of devices having a gate length of 135 nanometers, the maximum gate height H14 is no more than 24 nm, no more than 23 nm, no more than 22.5 nm, no more than 22 nm, no more than 21.5 nm, no more than 21 nm, no more than 20.9 nm, no more than 20.8 nm, no more than 20.7 nm, no more than 20.6 nm, or no more than 20.5 nm. In certain embodiments, of the total number of devices having a gate length of 135 nanometers, the maximum gate height H14 is 20.5 nm.
Further, of the total number of devices having a gate length of 135 nanometers, more than 3% have a gate height H14 of less than 16 nanometers (nm). For example, of the total number of devices having a gate length of 135 nanometers, more than 3.5%, more than 4%, more than 4.5%, more than 5%, more than 5.1%, more than 5.2%, more than 5.3%, more than 5.4%, more than 5.5%, more than 5.6%, or 5.7% have a gate height H14 of less than 16 nanometers (nm). Further, of the total number of devices having a gate length of 135 nanometers, less than 10%, less than 9%, less than 8%, less than 7%, less than 6.5%, less than 6%, less than 5.9%, less than 5.8%, or 5.7% have a gate height H14 of less than 16 nanometers (nm).
In some embodiments, of the total number of devices having a gate length of 135 nanometers, the minimum gate height H14 is at least 6 nm, at least 7 nm, at least 8 nm, at least 9 nm, at least 10 nm, at least 11 nm, at least 11.5 nm, at least 12 nm, at least 12.5 nm, at least 12.6 nm, at least 12.7 nm, at least 12.8 nm, at least 12.9 nm, at least 13 nm, or at least 13.1 nm. In some embodiments, of the total number of devices having a gate length of 135 nanometers, the minimum gate height H14 is no more than 15 nm, no more than 14.5 nm, no more than 14 nm, no more than 13.5 nm, no more than 13.4 nm, no more than 13.3 nm, no more than 13.2 nm, or no more than 13.1 nm. In certain embodiments, of the total number of devices having a gate length of 135 nanometers, the minimum gate height H14 is 13.1 nm.
A maximum gate height differential between devices of different gate lengths may be obtained by finding the maximum difference between respective maximum gate heights and minimum gate heights. For example, for devices having a gate length of 3 nanometers, the maximum gate height is 18.4 nm and the minimum is 6.2 nm. For devices having a gate length of 9 nanometers, the maximum gate height is 17.4 nm and the minimum is 8.1 nm. The difference between 18.4 nm and 8.1 nm is 10.3 nm, and the difference between 17.4 nm and 6.2 nm is 11.2 nm. Thus, the maximum difference in gate height between devices having a gate length of 3 nanometers and devices having a gate length of 9 nanometers is 11.2 nm.
Accordingly, it may be seen that the maximum difference in gate height between devices having a gate length of 3 nanometers and devices having a gate length of 55 nanometers is 15.4 nm; the maximum difference in gate height between devices having a gate length of 3 nanometers and devices having a gate length of 135 nanometers is 14.3 nm; the maximum difference in gate height between devices having a gate length of 9 nanometers and devices having a gate length of 55 nanometers is 13.5 nm; the maximum difference in gate height between devices having a gate length of 9 nanometers and devices having a gate length of 135 nanometers is 12.4 nm; and the maximum difference in gate height between devices having a gate length of 55 nanometers and devices having a gate length of 135 nanometers is 9.4 nm.
As described herein, semiconductor dies are designed and provided with an optimized distribution of gate heights for performance and yield.
In an embodiment, a method for manufacturing semiconductor devices on a die includes forming semiconductor devices with a gate length of 3 nanometers (nm) and having metal gates, wherein over 99% of the semiconductor devices with the gate length of 3 nanometers (nm) have a gate height of from 10 to 14 nanometers (nm).
In certain embodiments of the method, the semiconductor devices with the gate length of 3 nanometers (nm) that are located in a corner of the die have a minimum gate height of 6.2 nanometers (nm).
In certain embodiments of the method, the semiconductor devices with the gate length of 3 nanometers (nm) have a maximum gate height of 18.4 nanometers (nm).
In certain embodiments, the method further includes forming semiconductor devices with a gate length of 9 nanometers (nm) and having metal gates, wherein over 90% of the semiconductor devices with the gate length of 9 nanometers (nm) have a gate height of from 10 to 13 nanometers (nm).
In certain embodiments of the method, the semiconductor devices with the gate length of 9 nanometers (nm) that are located in a corner of the die have a minimum gate height of 8.1 nanometers (nm).
In certain embodiments of the method, the semiconductor devices with the gate length of 9 nanometers (nm) have a maximum gate height of 17.4 nanometers (nm).
In certain embodiments, the method further includes forming semiconductor devices with a gate length of 55 nanometers (nm) and having metal gates, wherein over 90% of the semiconductor devices with the gate length of 55 nanometers (nm) have a gate height of from 14 to 19 nanometers (nm).
In certain embodiments of the method, the semiconductor devices with the gate length of 55 nanometers (nm) that are located in a corner of the die have a minimum gate height of 11.1 nanometers (nm).
In certain embodiments of the method, the semiconductor devices with the gate length of 55 nanometers (nm) have a maximum gate height of 21.6 nanometers (nm).
In certain embodiments, the method further includes forming semiconductor devices with a gate length of 135 nanometers (nm) and having metal gates, wherein over 90% of the semiconductor devices with the gate length of 135 nanometers (nm) have a gate height of from 16 to 19 nanometers (nm).
In certain embodiments of the method, the semiconductor devices with the gate length of 135 nanometers (nm) that are located in a corner of the die have a minimum gate height of 13.1 nanometers (nm).
In certain embodiments of the method, the semiconductor devices with the gate length of 135 nanometers (nm) have a maximum gate height of 20.5 nanometers (nm).
In certain embodiments of the method, the gate height of less than 1% of the semiconductor devices with the gate length of 3 nanometers (nm) is greater than 14 nanometers (nm).
In certain embodiments of the method, the gate height of less than 0.5% of the semiconductor devices with the gate length of 3 nanometers (nm) is less than 10 nanometers (nm).
In another embodiment, a method for manufacturing semiconductor devices on a die includes forming semiconductor devices with a gate length of 3 nanometers (nm) and having metal gates, wherein over 99% of the semiconductor devices with the gate length of 3 nanometers (nm) have a gate height of from 10 to 14 nanometers (nm); forming semiconductor devices with a gate length of 9 nanometers (nm) and having metal gates, wherein over 90% of the semiconductor devices with the gate length of 9 nanometers (nm) have a gate height of from 10 to 13 nanometers (nm); forming semiconductor devices with a gate length of 55 nanometers (nm) and having metal gates, wherein over 90% of the semiconductor devices with the gate length of 55 nanometers (nm) have a gate height of from 14 to 19 nanometers (nm); and forming semiconductor devices with a gate length of 135 nanometers (nm) and having metal gates, wherein over 90% of the semiconductor devices with the gate length of 135 nanometers (nm) have a gate height of from 16 to 19 nanometers (nm).
In certain embodiments of the method, the semiconductor devices with the gate length of 3 nanometers (nm) have a minimum gate height of 6.2 nanometers (nm) and a maximum gate height of 18.4 nanometers (nm);
In certain embodiments of the method, the semiconductor devices with the gate length of 9 nanometers (nm) have a minimum gate height of 8.1 nanometers (nm) and a maximum gate height of 17.4 nanometers (nm); the semiconductor devices with the gate length of 55 nanometers (nm) have a minimum gate height of 11.1 nanometers (nm) and a maximum gate height of 21.6 nanometers (nm); and the semiconductor devices with the gate length of 135 nanometers (nm) have a minimum gate height of 13.1 nanometers (nm) and a maximum gate height of 20.5 nanometers (nm).
In another embodiment, a semiconductor die includes semiconductor devices with a gate length of 3 nanometers (nm) having a minimum gate height of 6.2 nanometers (nm) and a maximum gate height of 18.4 nanometers (nm); semiconductor devices with a gate length of 9 nanometers (nm) having a minimum gate height of 8.1 nanometers (nm) and a maximum gate height of 17.4 nanometers (nm); semiconductor devices with a gate length of 55 nanometers (nm) having a minimum gate height of 11.1 nanometers (nm) and a maximum gate height of 21.6 nanometers (nm); and semiconductor devices with a gate length of 135 nanometers (nm) having a minimum gate height of 13.1 nanometers (nm) and a maximum gate height of 20.5 nanometers (nm).
In certain embodiments of the semiconductor die, the gate height of over 99% of the semiconductor devices with the gate length of 3 nanometers (nm) is from 10 to 14 nanometers (nm); the gate height of over 90% of the semiconductor devices with the gate length of 9 nanometers (nm) is from 10 to 13 nanometers (nm); the gate height of over 90% of the semiconductor devices with a gate length of 55 nanometers (nm) is from 14 to 19 nanometers (nm); and the gate height of over 90% of the semiconductor devices with the gate length of 135 nanometers (nm) is from 16 to 19 nanometers (nm).
In certain embodiments of the semiconductor die, the gate height of 99.15% of the semiconductor devices with the gate length of 3 nanometers (nm) is from 10 to 14 nanometers (nm); the gate height of 94.7% of the semiconductor devices with the gate length of 9 nanometers (nm) is from 10 to 13 nanometers (nm); the gate height of 93% of the semiconductor devices with a gate length of 55 nanometers (nm) is from 14 to 19 nanometers (nm); and the gate height of 91.8% of the semiconductor devices with the gate length of 135 nanometers (nm) is from 16 to 19 nanometers (nm).
In certain embodiments of the semiconductor die, a maximum difference in gate height between the semiconductor devices with the gate length of 3 nanometers (nm) and the semiconductor devices with the gate length of 9 nanometers (nm) is 11.2 nanometers (nm); a maximum difference in gate height between the semiconductor devices with the gate length of 3 nanometers (nm) and the semiconductor devices with the gate length of 55 nanometers (nm) is 15.4 nanometers (nm); a maximum difference in gate height between the semiconductor devices with the gate length of 3 nanometers (nm) and the semiconductor devices with the gate length of 135 nanometers (nm) is 14.3 nanometers (nm); a maximum difference in gate height between the semiconductor devices with the gate length of 9 nanometers (nm) and the semiconductor devices with the gate length of 55 nanometers (nm) is 13.5 nanometers (nm); a maximum difference in gate height between the semiconductor devices with the gate length of 9 nanometers (nm) and the semiconductor devices with the gate length of 135 nanometers (nm) is 12.4 nanometers (nm); and a maximum difference in gate height between the semiconductor devices with the gate length of 55 nanometers (nm) and the semiconductor devices with the gate length of 135 nanometers (nm) is 9.4 nanometers (nm).
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present.
