Patent Application
20090026587
The present invention relates generally to semiconductor devices, and, more particularly, to dielectric layers for such devices having a low overall dielectric constant, good adhesion to the semiconductor substrate, and good resistance to cracking due to thermal cycling, and to processes for making such dielectric layers.
Insulating dielectric layers, commonly referred to as inter-level dielectrics (ILD's), are used to separate conductor and semiconductor layers within semiconductor devices. Recently, dielectric materials having low dielectric constants, k, known as “low-k dielectrics,” have become popular because they create less capacitance between and around the conductors and are more easily applied than conventional silicon oxide dielectrics, which have higher dielectric constants. Recent progress in low-k dielectrics, for example using Chemical Vapor Deposition (“CVD”) techniques, offers more affordable and attractive dielectric options to the advanced interconnect technologies. CVD is a process for depositing a thin film of material onto a substrate by reacting the constituent elements in gaseous phase; CVD processes are used to produce thin, single-crystal films called epitaxial films. By employing CVD low-k dielectrics with a dielectric constant of about 2.7 at the wiring level, the total capacitance and RC delay can be significantly reduced.
One common problem encountered when using low-k dielectrics is poor adhesion, however, between the low-k dielectrics and the underlying substrate. Conventional methods typically form low-k dielectric films through either spin-on processes or through Plasma Enhanced Chemical Vapor Deposition (PECVD) of organosilane gases, to produce dielectrics such as amorphous hydrogenated carbon doped oxide (a-SiCO:H) or other carbon-containing dielectrics such as are known in the art. Such dielectrics often have poor adhesion to substrates such as silicon dioxide, silicon nitride, silicon carbide, silicon, tungsten, aluminum, and copper. Because of this low structural adhesion, low-k dielectric layers often delaminate from the underlying substrate, which leads to a failure of interconnect processes.
One conventional method to improve adhesion between low-k dielectric layers and underlying substrates is the use of an adhesion promoter. An adhesion promoter is often used for spin-on dielectric (SOD) low-k dielectrics rather than for PECVD processes, however, which requires the use of a precursor such as methylsilane (1MS) trimethylsilane (3MS), tetramethylsilane (4MS), tetramethylcyclotetrasiloxane (TMCTS), and/or orthomethylcyclotetrasiloxane (OMCTS). Such low-k dielectric films have, in general, a hydrophobic surface with high wetting angles with water. This characteristic causes these films to have a very poor adhesion with substrate layers.
Hybrid stacks of dielectric material have also been used in making semiconductor devices, in which the ILD comprises two or more discrete films of different dielectric materials. Such hybrid schemes usually employ a low-k material at the trench level, and a strong and thermally compatible material (lower thermal expansion) at the via level, typically having a higher dielectric constant than the material used at the trench level. The incorporation of two or more discrete dielectric films in this manner increases the number of steps required in the process of forming the ILD, and the resulting device may suffer from adhesion problems between the films.
Therefore, there is a need for structures and methods that provide ILD's with low overall k and that provide good adhesion between the ILD and the substrate, as well as resistance to internal adhesion failure of the ILD.
To meet this and other needs, and in view of its purposes, the present invention provides, in one aspect, a dielectric layer disposed on a substrate surface. The dielectric layer has a top surface. The dielectric layer comprises a first dielectric gradient region in which a dielectric constant k decreases continuously from a maximum value to a minimum value with distance from the substrate surface.
In another aspect, the invention provides a process of making a dielectric layer disposed on a substrate surface. The process comprises applying to the substrate, via chemical vapor deposition, a continuously varying composition of chemical vapor deposition precursors to form a first dielectric gradient region in which a dielectric constant k decreases continuously from a maximum value to a minimum value with distance from the substrate surface.
In a further aspect, the invention provides a process of making a semiconductor device that comprises a dielectric layer disposed on a substrate surface. The process comprises applying to the substrate, via chemical vapor deposition, a continuously varying composition of chemical vapor deposition precursors to form a first dielectric gradient region in which a dielectric constant k decreases continuously from a maximum value to a minimum value with distance from the substrate surface.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.
The invention is best understood from the following detailed description when read in connection with the accompanying drawing. It is emphasized that, according to common practice, the various features of the drawing are not to scale. On the contrary, the dimensions of the various features are arbitrarily expanded or reduced for clarity. Included in the drawing are the following figures:
Referring now to the drawing, in which like reference numbers refer to like elements throughout the various figures that comprise the drawing,
Adjacent the initial dielectric region 24 is a dielectric gradient region 26, in which the dielectric constant decreases continuously with distance from substrate surface 14. Adjacent to dielectric gradient region 26 is an optional dielectric region 28, in which k has an optionally variable value less than the highest level of k in dielectric gradient region 26, followed by an optional dielectric gradient region 30 in which k increases with distance from substrate surface 14.
Adjacent dielectric gradient region 30 is an optional dielectric region 32 in which k may or may not be equal to the highest level of k in dielectric gradient region 26, and in which k may be variable. Adjacent dielectric region 32 is an optional dielectric gradient region 34 in which k decreases with distance from substrate surface 14. Dielectric region 32 and adjacent dielectric regions 30 and 34 may be present in locations other than at the interface of trench 22 and via 20, or they may be totally absent altogether. In one embodiment, however, these regions may serve as an etch stop to facilitate formation of trench 22 after formation of via 20 in a dual damascene process.
A damascene process is a process used in some aspects of semiconductor fabrication. It is a process of inlaying a metal into a predefined pattern, typically in a dielectric layer. It is typically performed by defining the desired pattern into a dielectric film; depositing metal over the entire surface by either physical vapor deposition, chemical vapor deposition, or evaporation; then polishing back the top surface in such a way that the top surface is planarized and the metal pattern is only located in the predefined regions of the dielectric layer. The damascene process has been used in manufacturing of metal wiring lines, including the bit-lines for a Dynamic Random Access Memory (“DRAM”) capacitor.
Damascene technology is a common method of fabricating interconnects. In this context, damascene refers to the steps of patterning an insulator to form recesses, filling the recesses with a metal, and then removing the excess metal above the recesses. This process can be repeated as needed to form the desired number of stacked interconnects. Typically, these damascene structures are laid out in pairs, a process referred to as dual damascene.
The term “damascene” is derived from the name of a centuries' old process used to fabricate a type of in-laid metal jewelry first seen in the city of Damascus. In the context of integrated circuits, damascene means formation of a patterned layer imbedded on and in another layer such that the top surfaces of the two layers are coplanar. Planarity is essential to the formation of fine-pitch interconnect levels because lithographic definition of fine features is achieved using high-resolution steppers having small depths of focus. The “dual damascene” process, in which conductive lines and stud via metal contacts are formed simultaneously, is described by Chow in U.S. Pat. No. 4,789,648.
Adjacent dielectric gradient region 34 is an optional dielectric region 36, in which k has an optionally constant value that is lower than the highest level of k in dielectric gradient region 26 and that may or may not be the same as the value of k in dielectric region 28. Adjacent dielectric region 36 is an optional dielectric gradient region 38 in which k increases with distance from substrate surface 14. Adjacent dielectric gradient region 38 is an optional dielectric region 40 having an optionally constant k that may or may not be equal to either of the highest level of k in dielectric gradient region 26 or the value of k in dielectric region 32. Dielectric region 40 may serve, for example, as a cap for dielectric layer 12, to seal it.
Although some of the dielectric gradient regions shown in
Typically, the instantaneous rate of decrease of k in the first dielectric gradient region 26 is between 0.025 and 0.5 per 10 nm of dielectric thickness at substantially every location throughout it. This rate provides good adhesion between dielectric layer 12 and substrate 16 as well as high resistance to internal cracking within dielectric layer 12, for example due to thermal cycling. Advantageously, other dielectric gradient regions such as 30, 34, and 38 may also have instantaneous rates of increase or decrease of k between 0.025 and 0.5 per 10 nm of dielectric thickness, for the same reasons.
In one embodiment of the invention, the instantaneous rate of increase or decrease in any or all dielectric gradient regions may be between 0.05 and 0.1 per 10 nm of dielectric thickness. Rates in such a range may provide a good balance between provision of overall low average dielectric constant throughout dielectric layer 12, and prevention of adhesion loss or cracking. Regions of optionally constant k value, such as shown at 24, 28, 32, 36, and 40 in
As is well understood in the art, the lowest practical levels of dielectric constant k are generally preferred, to reduce capacitive coupling and resultant cross talk between lines. Therefore, low dielectric constant materials will typically be used in all locations when possible. Similarly, when the use of a higher k material is required for reasons of adhesion, etch stop performance, or for other purposes, the rates of dielectric constant increase or decrease in the dielectric gradient regions will be as high as possible without creating adhesion, cracking, or other problems, so that as much as possible of the total thickness of dielectric layer 12 is of a low k material. The invention is not restricted, however, to the use of low k materials in the dielectric layer 12, nor is it restricted to the particular low k materials used as examples in this document.
The materials that constitute the dielectric regions and the dielectric gradient regions disclosed above in relation to
Any of a number of materials may be used to produce ILD's having dielectric gradient regions according to the invention. Such materials, and the processes for applying them, include for example a dielectric material provided by CVD deposition. Such materials are referred to in this document as CVD precursors.
The invention may for example utilize well-known materials such as 1MS, 3MS, 4MS, TMCTS, OMCTS, and the like, which may be used with or without oxygen and/or carbon dioxide as an oxidizer. The invention employs a continuously varying deposition process that gradually increases the concentration of such gases as dielectric material builds upon the substrate 16. This process produces a structure that has a gradient structure of increasing organic concentration, accompanied by decreasing dielectric constant k.
More specifically, in connection with the exemplary embodiment shown in
In the foregoing, the processing pressure in the reactor chamber can be any standard operating pressure and is preferably between about 1 Torr to about 10 Torr and is more preferably about 4 Torr. An RF power source with source power preferably between 300 and 1,000 watts, more preferably about 600 watts, can be used. Any frequency and combination of RF powers can be used for bias power for sputtering in a range of between 0 watts and about 500 watts. The temperature range is preferably about 250° C.-550° C. The thickness of layers 24, 26, 28, and 38 may be any design thickness, and are typically between about 10 nm and 150 nm. Therefore, the total thickness of dielectric layer 12, as shown in
Following the formation of the resulting dielectric layer 12, conventional photolithography and etching processes may be applied to generate etched regions, e.g., vias and/or trenches, for forming contacts, single damascene interconnects, dual damascene interconnects, or other types of interconnects. Such etched regions may be filled with tungsten, copper, copper alloy, aluminum, aluminum alloy, or another conductive material, as is well known to those skilled in the art. Appropriate combinations of these and other steps known in the semiconductor fabrication art can achieve a complete semiconductor device incorporating dielectric gradient regions.
The following examples are included to more clearly demonstrate the overall nature of the invention. These examples are exemplary, not restrictive, of the invention. The following abbreviations are used in the examples.
OMCTS means octamethylcyclotetrasiloxane.
SICOH means amorphous hydrogenated carbon doped silicon oxide.
“Spacing” refers to the distance between the semiconductor wafer and the plasma electrode.
HFRF and LFRF are high and low frequency radio frequencies, respectively, used for forming the plasma. Plasma is a partially ionized gas. To make plasma, a device excites a gas with high radio or microwave frequencies. The plasma then emits light, charged particles (ions and electrons), and neutral active components (atoms, excited molecules, and free radicals). These particles and components bombard substrates brought into the plasma environment.
In Examples 1 and 2, dielectric layers are deposited by PECVD techniques onto a silicon substrate, using the plasma and composition conditions shown.
In Examples 1 and 2, regions of essentially constant k are produced in each of Steps 1, 2, and 3, while regions having an increasing or decreasing gradient of k are formed during the First and Second Transitions.
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/US04/00908 | 1/14/2004 | WO | 00 | 7/7/2006 |
