Patent Application
20240088140
The present disclosure relates to semiconductor devices, and more particularly to semiconductor devices including channel regions integrated within nanosheets.
With the continuing trend towards miniaturization of integrated circuits (ICs), there is a need for transistors to have higher drive currents with increasingly smaller dimensions. The use of non-planar semiconductor devices such as, for example, nano-sheet transistors may be the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. However, vertical devices having nanosheet integrated channels into multiple regions structures have shown some susceptibility to variations in height during processing.
In one aspect, a semiconductor device is provided including fin structures composed of stacked nanosheets. In one embodiment, the semiconductor device includes a substrate having a dense array region and an isolation region, wherein the dense array region and the isolation region are separated by a trench isolation region. The semiconductor device includes plurality of first fin structures composed of stacked nanosheets is present in the dense array region separated by a single pitch, wherein each fin structure in the first plurality of fin structures has a same first nanosheet height as measured from an upper surface of the substrate in the dense array region. The semiconductor device further includes at least one second fin structure including of stacked nanosheets is present in the isolation region, wherein a number of second fin structure in the isolation region is less than a number of first fin structures in the dense array region, the at least one fin structure having a second nanosheet height that is measured from the upper surface of the substrate in the isolation region that is the same as the first nanosheet height.
In another aspect, an electrical device is provided having field effect transistors including channel regions present in fin structures of stacked nanosheets. In one embodiment, the electrical device includes a substrate having a dense array region and an isolation region, wherein the dense array region and the isolation region are separated by a trench isolation region. The electrical device includes a plurality of first field effect transistors having channel regions present in a first plurality of first fin structures of stacked nanosheets is present in the dense array region separated by a single pitch. Each first fin structure has a same first fin height as measured from an upper surface of the substrate in the dense array region. The electrical device also at least one second field effect transistor having channel regions present in at least one second fin structure that includes stacked nanosheets is present in the isolation region. The number of second fin structure in the isolation region is less than a number of first fin structures in the dense array region. The at least one second fin structure having a second fin height that is measured from the upper surface of the substrate in the isolation region that is the same as the first fin height.
In another aspect a method of providing fin structures composed of nanosheets is provided. In one embodiment, the method includes etching a stack of nanosheets with a single pitch pattern to provide a plurality of fin structures on a substrate, wherein etching of a base nanosheet in the stack of nanosheets that is in direct contact with the substrate employs an etch process that is selective to the substrate. The method may further include forming first spacers on sidewalls of the plurality of fin structures; and forming first depth trenches in the substrate using the fin structures and first spacers as a mask, wherein the spacer protect a portion of the substrate adjacent to the plurality of fin structures to provide a step profile during etch processes in forming the first depth trenches. The method can also include forming a protective liner on the plurality of fin structures; and forming a second depth trench in the substrate. In some embodiments, the etch process for forming the second depth trench defines a dense array of fin structures from the plurality of fin structures in a dense array region of the substrate and isolation fin structures from the plurality of fin structures in an isolation region of the substrate, the isolation region and dense array region being separated from one another by the second depth trench. In some embodiments, the protective liner protects the dense array of fin structures and the isolation fin structures during etch processes for forming the second depth trench to provide that the fin height for the dense array of fin structures and the isolation fin structures is the same.
These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
The disclosure will provide details in the following description of preferred embodiments with reference to the following figures wherein:
Detailed embodiments of the claimed methods, structures and computer products are disclosed herein; however, it is to be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. In addition, each of the examples given in connection with the various embodiments are intended to be illustrative, and not restrictive. Further, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the methods and structures of the present disclosure.
Reference in the specification to “one embodiment” or “an embodiment” of the present principles, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment of the present principles. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment”, as well any other variations, appearing in various places throughout the specification are not necessarily all referring to the same embodiment. For purposes of the description hereinafter, the terms “upper”, “over”, “overlying”, “lower”, “under”, “underlying”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the embodiments of the disclosure, as it is oriented in the drawing figures. The term “positioned on” means that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure, e.g. interface layer, may be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.
In one aspect, embodiments of the present disclosure describe structures and methods of forming nanosheet devices that have been processed to overcome active nanosheet height variation. The nanosheet devices are patterned into fin type geometries. In multiple region devices, e.g., devices formed on substrates including multiple active device and isolation regions, it has been determined that at least three reasons can be contributing to activate nanosheet height variation between the array device and the isolated devices. One possible reason for the active nanosheet height variation can result from differences in the quality of the oxide, e.g., silicon oxide (SiO2), in the isolation regions and the densely populated array regions. Another reason is the difference in the recess rate of oxide, e.g., silicon oxide (SiO2), between the regions of the device in which there are isolated devices, and the regions of the device in which there are dense arrays of devices. Finally, there can be depth variations that result from the subtractive processing, e.g., reactive ion etching (RIE), that provides the fins of nanosheets.
It has been determined that to provide for a more uniform height of the patterned fins of nanosheets (NS), the shallow trench isolation (STI) recess should be stopped at the bottom of the bottom dielectric isolation (BDI) layer that is underlying the nanosheet stacks. This is generally where variations in STI recessing steps have occurred. Such that, the recess to be stopped below the BDI to get a process margin in BDI recess. Under this situation, PC aspect ratio on STI are has to increase, which is vulnerable to collapse.
The methods and structures of the present disclosure are now described with reference to
In some embodiments, the plurality of first fin structure 30 in the dense array region 15 and the fin structure 30 in the isolation region 20 further comprise a gate structure 51 and source and drain regions (source/drain regions 50), as depicted in
One example of a method for forming the structure depicted in
The substrate 5 may be composed of a supporting material, such as a semiconductor material, e.g., silicon, or dielectric material, such as silicon oxide or silicon nitride.
The stack of nanosheets 10 is a multilayered structure that is present on the upper surface of the substrate 5. The term “nanosheet” denotes a substantially two dimensional structure with thickness in a scale ranging from 1 to 100 nm. The width and length dimensions of the nanosheet may be greater than the width dimensions. In the embodiment depicted in
For example the layered semiconductor materials that provide the nanosheet stack 10 can includes alternating semiconductor layers 7, 8 in the following sequence: Si1-xGex/Si1-yGey with two different Ge contents. For example, in the above chemical compositions the value of x may be more than the value of y. For example, the value of y can be approximately 30%, and the value of x can be approximately 55%.
In addition to the above example, any type IV semiconductor composition combination and/or III-V semiconductor composition combination is suitable for use with the stacks of layered semiconductor materials 7,8 that provide the nanosheets. For example, the compositions selected for the layers within the stacks of layered semiconductor materials 7, 8 can include Si, SiGe, SiGeC, SiC, single crystal Si, polysilicon, i.e., polySi, epitaxial silicon, i.e., epi-Si, amorphous Si, i.e., α:Si, germanium, gallium arsenide, gallium nitride, cadmium telluride and zinc sellenide.
The stack of the layered semiconductor materials for the nanosheets 7, 8 may be formed using a deposition process, such as epitaxial deposition. “Epitaxial growth and/or deposition” means the growth of a semiconductor material on a deposition surface of a semiconductor material, in which the semiconductor material being grown has substantially the same crystalline characteristics as the semiconductor material of the deposition surface. In some embodiments, when the chemical reactants are controlled and the system parameters set correctly, the depositing atoms arrive at the deposition surface with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface. Thus, in some examples, an epitaxial film deposited on a {100} crystal surface will take on a {100} orientation.
The thickness of each layer within the stack of the layered semiconductor materials for the nanosheets 7, 8 may range from 1 nm to 30 nm. In another embodiment, the thickness of each layer within the stack of the layered semiconductor materials 10 may range from 5 nm to 20 nm.
The methods and structures are not limited to only the example depicted in
Still referring to
For example, a pattern (not shown) is produced by applying a photoresist to the surface to be etched (e.g., the hardmask layer 8); exposing the photoresist to a pattern of radiation; and then developing the pattern into the photoresist utilizing conventional resist developer. Once the patterning of the photoresist is completed, the sections of the nanosheet stack 10 covered by the photoresist are protected while the exposed regions are removed using a selective etching process that removes the unprotected regions.
In some embodiments, in which the substrate 5 is composed of a semiconductor material, such as silicon (Si), the etch process may remove the exposed portions of the nanosheet stack 10 selectively to the substrate 5. In one example, the first layer 6 of the nanosheet stack 10 that is in direct contact with the upper surface of the semiconductor substrate 5 is silicon germanium (SiGe) having a germanium (Ge) content on the order of 55 wt. % and the substrate 5 is silicon (Si), the etch process for patterning the fins may remove the first layer 6 of the nanosheet stack 10 selectively to the substrate. For example, end point detection may be employed to sense when the etch process has etched through the first layer 6 of silicon germanium (SiGe), and to stop when the etch process has reached the semiconductor substrate of silicon (Si). The etch process may be a chemical etch, such as a wet chemical etch. In some embodiments, the etch process may be a directional etch, such as reactive ion etching (RIE). In some embodiments, by employing end point detection, and terminating the etch process when it has been detected that the upper surface of the substrate 5 has been exposed, height variations resulting from etching the substrate 5 can be eliminated. It is noted that the height H1 of the fin structures 30 formed of the patterned layer of nanosheets 10 can be set at this stage of the process flow.
The conformal dielectric layer 11 may be deposited using a conformal deposition process, such as chemical vapor deposition, such as plasma enhanced chemical vapor deposition or metal organic chemical vapor deposition. The conformal dielectric layer 11 may also be deposited using atomic layer deposition (ALD).
Following deposition of the conformal dielectric layer 11, a directional etch may be applied to recess the height of the conformal dielectric layer 11. The directional characteristic of the etch process can allow for the horizontal portions of the conformal dielectric layer 11 to be completely removed, where the vertical portions remain to provide spacers, as depicted in
In some embodiments, following formation of the protective liner 16, the method may begin the process sequence for forming the blocks masks that provide for further defining the array region 15 and the isolation region 20. The block masks 21, 22 are formed having a first portion 21 protecting a plurality of fins 30 of nanosheets 6, 7 in the dense array region 15, and having a second portion 22 protecting a single fin 30 in the isolation region 20, wherein a remainder of fins of nanosheets 6, 7 are exposed. The exposed portion of the substrate that is not protected by the block mask 71 is subsequently processed to remove the fin structures 30 from the isolation region 20, but for the fin structures 30 protected by the second portion of the block mask 21, 22.
The block mask 21, 22 may comprise soft and/or hardmask materials and can be formed using deposition, photolithography and etching. In one embodiment, the block mask 21, 22 comprises an organic planarization layer (OPL). A block mask 21, 22 comprising a OPL material may be formed by blanket depositing a layer of OPL material; providing a patterned photoresist atop the layer of OPL material; and then etching the layer of POL material to provide a block mask 21, 22.
Following the formation of the block mask 21, 22, an etch process is performed removing the exposed portion of the protective liner 16, the exposed fin structure 30, and the underlining portion of the substrate 5 to provide isolation trenches 40. In one embodiment, a directional etch process, such as reactive ion etching (RIE), may be employed to etch through the exposed portions of the protective liner 16, the fin structure 30 and the substrate 5.
Referring back to
Following removal of the protective liner 16, the dielectric cap 8 on the fin structures 30 can be removed. The dielectric cap 8 is composed of a nitride, such as silicon nitride. In some embodiments, the nitride material of the dielectric cap 8 may be removed by an etch that is selective to the underlying semiconductor material of the nanosheets 6, 7 that provide the fin 30. In some embodiments, the fin is composed of silicon germanium (SiGe) nanosheets. The nitride material of the dielectric cap may be removed selectively to the silicon germanium of the fin structures 30 using a selective etch, such as a plasma etch or wet chemical etch. Alternatively, a planarization process may remove the dielectric cap 8, such as chemical mechanical planarization.
The fin structures 30 depicted in
In some embodiments, the gate structure and source and drain regions for the device are formed using a replacement gate process flow. By “replacement” it is meant that the structure is present during processing of the semiconductor device, but is removed from the semiconductor device prior to the device being completed. As used herein, the term “replacement gate structure” denotes a sacrificial structure that dictates the geometry and location of the later formed functioning gate structure. The “functional gate structure” operates to switch the semiconductor device from an “on” to “off” state, and vice versa.
In one embodiment, a sacrificial material that provides the replacement gate structure is first formed on the channel region of the fin structures 30. Following the formation of the replacement gate structure, the source and drain regions may be formed. For example, epitaxial semiconductor material may be formed on the source and drain region portions of the nanosheets 6, 7 following the formation of the replacement gate structure.
As used herein, the term “drain” means a doped region in semiconductor device located at the end of the channel region, in which carriers are flowing out of the transistor through the drain. The term “source” is a doped region in the semiconductor device, in which majority carriers are flowing into the channel region.
In some embodiments, the epitaxial semiconductor material for the source and drain regions may be composed of silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon doped with carbon (Si:C) or the epitaxial semiconductor material 35 may be composed of a type III-V compound semiconductor, such as gallium arsenide (GaAs).
The epitaxial semiconductor material for the source and drain regions may be in situ doped to a p-type or n-type conductivity. The term “in situ” denotes that a dopant, e.g., n-type or p-type dopant, is introduced to the base semiconductor material, e.g., silicon or silicon germanium, during the formation of the base material. For example, an in situ doped epitaxial semiconductor material may introduce n-type or p-type dopants to the material being formed during the epitaxial deposition process that includes n-type or p-type source gasses. In the embodiments in which the semiconductor device being formed has p-type source and drain regions, and is referred to as a p-type semiconductor device, the doped epitaxial semiconductor material is doped with a p-type dopant to have a p-type conductivity. As used herein, “p-type” refers to the addition of impurities to an intrinsic semiconductor that creates deficiencies of valence electrons. In a type IV semiconductor, such as silicon, examples of p-type dopants, i.e., impurities, include but are not limited to, boron, aluminum, gallium and indium. As used herein, “n-type” refers to the addition of impurities that contributes free electrons to an intrinsic semiconductor. In a type IV semiconductor, such as silicon, examples of n-type dopants, i.e., impurities, include but are not limited to antimony, arsenic and phosphorous.
In some instances, following the formation of the source and drain regions, an interlevel dielectric layer is deposited. Following the deposition of the interlevel dielectrics, the replacement gate structures can be replaced with functional gate structures. The functional gate structures operates to switch the semiconductor device from an “on” to “off” state, and vice versa. The functional gate structures typically include at least one gate dielectric and at least gate conductor. The replacement gate structures are typically removed using a selective etch process that provides a gate opening to the channel portions of the fin structures.
Having described preferred embodiments of a methods and structures for height control in nanosheet devices that are disclosed herein, it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims. Having thus described aspects of the invention, with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.
