BRIEF DESCRIPTION OF DRAWINGS
FIGS. 1-4 are much enlarged, partial side elevational views, in section, representing the initial steps of making an interposer of the invention;
FIGS. 5 and 6 are much enlarged, partial side elevational views, in section, representing the steps of making a pinned interposer according to one embodiment of the invention, these steps following the steps of FIGS. 1-4 above;
FIG. 7 is a much enlarged, partial side elevational view, in section, representing an alternative embodiment of a pinned interposer of the invention;
FIGS. 8-10 are much enlarged, partial side elevational views, in section, representing the steps of making an embodiment of the invention adapted for solder ball usage, these steps following the steps of FIGS. 1-4 above;
FIGS. 11 and 12 are much enlarged, partial side elevational views, in section, representing the steps of making a version of the invention adapted for solder ball usage, according to an alternative embodiment of the invention, these steps following the steps of FIGS. 1-4 and 8 above; and
FIG. 13 is a much enlarged, partial side elevational view, in section, representing an electrical assembly which includes as part thereof an interposer according to one embodiment of the invention.
BEST MODE FOR CARRYING OUT THE INVENTION
For a better understanding of the present invention, together with other and further objects, advantages and capabilities thereof, reference is made to the following disclosure and appended claims in connection with the above-described drawings. Like figure numbers will be used from FIG. to FIG. to identify like elements in these drawings.
By the term “substrate” as used herein is meant to include structures having plurality of dielectric layers and a plurality of electrically conductive layers, at least some of both being arranged in an alternating manner, e.g., dielectric layer-conductive layer-dielectric layer-conductive layer, etc. Examples of dielectric materials usable for such substrates include fiberglass-reinforced epoxy resins (some referred to as “FR4” dielectric materials in the art, for the flame retardant rating of same), polytetrafluoroethylene (e.g., Teflon), polyimides, polyamides, cyanate resins, photo-imageable materials, and other like materials. Examples of conductor materials usable in such substrates include copper or copper alloys, but may include or comprise additional metals (e.g., nickel, aluminum, etc.) or alloys thereof. Such conductor materials are used to form layers which may serve as power, signal and/or ground layers. If as a signal layer, several conductor lines and/or pads may constitute the layer, while if used as power or ground, such layers will typically be of substantially solid construction. Combinations of signal, power and/or ground are possible in one substrate, and combinations of signal, power and/or ground are possible in one conductive layer. Examples of substrates include the aforementioned printed circuit boards (or cards) and chip carriers, when the conductive layers are “circuitized”, meaning these are capable of carrying signals (if a signal layer), power (if a power layer) or serving as ground (if a ground layer).
Conductive thru-holes are known in the substrate art, and are often referred to as “vias” if internally located (entirely within the substrate's outer confines), “blind vias” if extending a predetermined depth within the substrate from an external surface, or “plated thru-holes” (PTHs) if extending substantially through the substrate's full thickness. By the term “thru-hole” as used herein, therefore, is meant to include all three types of such substrate openings.
As understood, the term “high frequency” as used herein is meant signals of high speed. Examples of such signal frequencies attainable for the substrates produced in accordance with the teachings herein include those within the range of as high as from about 3.0 to about 10.0 gigabits per second (GPS). These examples are not meant to limit this invention, however, because frequencies outside this range, including those higher, are attainable.
By the term “electrical assembly” as used herein is meant an assembly including at least one interposer as taught herein and at least one semiconductor chip which is electrically coupled to the interposer, e.g., through use of a laminated carrier.
In FIG. 1, a substrate 15 is shown, this member including a plurality (i.e., five are shown albeit more or fewer may be utilized) of electrically conductive layers (planes) 17 therein. Each layer 17 may be a signal, power or ground, or combination of these, depending on the operational requirements for the finished product. Substrate 15 also includes a plurality of layers 19 of dielectric material of the types defined above. Layers 17 and 19 are preferably oriented in an alternating manner, as shown, albeit it is possible to provide two or more dielectric layers as one larger layer, if desired. In one embodiment, each of the five conductive layers 17 may possess a thickness of about one mil (a mil being 0.001 inch), while each of the dielectric layers may possess a thickness of from about 2.5 mils to about twenty mils. If a conductive layer is a signal layer, it will typically be comprised of individual segments (traces, or lines). The example shown in FIG. 1 (and in subsequent FIGS.) depicts such a plurality (i.e., three) of traces or lines for each of the five conductive layers. If one or more of these layers is to function as power or ground, it would most preferably be of solid and not the segmented configuration shown. Layers 17 and 19 are bonded together, preferably, using conventional lamination processing as is known in the PCB and chip carrier art.
In FIG. 2, an opening 21 is formed within substrate 15, between opposing surfaces (top and bottom), as shown. That is, the opening extends through the entire thickness of the substrate. Opening 21 may be formed using laser or mechanical drilling, various types of same being known in the PCB art and further description is not considered necessary. In one embodiment, more than one opening is preferably formed so the invention is not limited to the use of only one as shown in FIG. 2. It is possible to provide as many as 1500 such openings within a substrate having length and width dimensions of 1970 mils and 1970 mils, respectively, thereby illustrating the high density patterns of these attainable using the instant invention's teachings. The total number of such openings will thus vary, again depending on the overall size of the final product as well as the desired operational requirements thereof. In one embodiment, opening 21 may have a diameter of twenty mils and extend the full thickness of member 15, member 15 having an overall thickness within the range of from about twenty mils to about 200 mils. Opening 21 is understood to be of substantially cylindrical configuration, but this is not meant to limit the invention. Opening 21 is also shown to penetrate through a portion of each of the conductive layers 17. This also is not meant to limit the invention, as better understood from the following. That is, any number of such layers 17 may be so connected to layer 23. If more than one, each will be of the same potential.
Following opening formation (which may include cleaning of the interior walls of the substrate, again, using conventional PCB processing), opening 21 is rendered conductive by applying a metal layer 23 to the opening's interior surfaces and, as shown in FIG. 3, to the immediately adjacent exterior surfaces of substrate 15 about the open end portions of the opening. Each of these extending surface portions, if added, are also referred to in the PCB art as “lands.” The invention is not limited to such usage, however, because the internal layer 23 needs only be located on the vertical internal surfaces of opening 21. Such “lands” may be preferred, however, if the respective exterior surfaces on which these reside will also include additional circuitry, e.g., signal lines, some of which may be coupled to respective “land” segments. In one embodiment, layer 23 is copper or an alloy thereof and is applied using electroplating. Either electrolytic or electro-less plating may be used for this plating operation. Such methods, like those defined above, are also known in the PCB and chip carrier art and further description is not, therefore, deemed necessary. It is within the scope of the invention to provide metals other than copper or copper alloy. Further, added layers such as nickel and a precious metal such as gold may also be applied, as is also known in the art. In one example, layer 23 may possess a thickness of from about 0.5 mils to about 1.5 mils. Significantly, the layer 23 of opening 21 is of solid configuration and thus forms a solid “wall” at a spaced distance around the opening's central axis. Other conductive openings, if used, will provide similar “walls” at other locations.
In FIG. 4, a quantity of dielectric material 31 is bonded onto substrate 15. Such bonding may be accomplished using a conventional PCB lamination process, liquid application or vacuum lamination. Various dielectric materials may be used, with examples including solder mask material and resin-coated copper materials. Examples of solder mask materials include the Valu-SMT RTM series of materials sold by E.I. duPont de Nemours and Company, the Probimer RTM solder mask series of materials sold by the Ciba-Geigy Corporation, and the 503B-SH and MR-300RV/-300B series of solder mask materials from Asahi Chemical Research Company. A resin coated copper material usable for the invention is sold under the product name LG-F-2000G by the LG Chem Company. Material 31 fills opening 21 and forms a layer on each of the opposite surfaces of substrate 15, as shown. In one example, each outer layer may possess a thickness of from about one mil to about three mils. Material 31 is cured and/or dried, if needed, to become hardened to an extent similar as that of “C-staged” conventional dielectric materials used in many PCB products (e.g., the aforementioned “FR4” material). Material 31 may also be the same as that used for the dielectric layers 19 in member 15.
FIG. 5 is understood to be the beginning of a series of steps following those defined above with respect to FIGS. 1-4 toward making what will be referred to as a pinned interposer, meaning a substrate as shown herein in which a plurality of elongated conductive (e.g., solid copper) pins are used. These pins, understandably, extend through the entire thickness of substrate 15 and, in some cases, may project externally from one or both surfaces, depending on the electrical conductors to which these are to be coupled. More definition of this aspect of the invention is provided below. In FIG. 5, an opening 41 is formed within the hardened material 31, preferably using laser or mechanical drilling as was used for opening 21. In one embodiment, opening 31 may possess a diameter of twelve mils.
In FIG. 6, a pin 43 in inserted within opening 41 and includes an upper head portion 45 which lies substantially flush with the upper surface of the layer of material 31 and a lower projecting portion 47 which extends from beneath the substrate. Understandably, a pin 43 is located within each of the openings 21 and the single example shown in FIG. 6 is for illustration purposes only. Each pin 43 frictionally fits within the opening 41 specifically designed to accommodate it and is thus firmly held in position. Alternatively, the pin may also be adhesively secured within the opening. In one example, each pin may possess an outer diameter of about twelve mils. Each pin is also electrically isolated from the circuitry and any other conductive parts of substrate 15, including the internal layers 17. The pins as shown thus provide high-speed connections from a conductor which engage the upper head portion and a conductor which engages the projecting end 47. Examples of such conductors include solder balls (e.g., those on an electronic component such as a semiconductor chip) and plated openings (e.g., within a second substrate, not shown), respectively. Such conductors are known in the art and further definition is not deemed needed. Significantly, the outer shielding layer 23, which surrounds the pin in each opening, functions to shield the pin during high-speed signal passage therethrough. The thickness of the material 31 within the opening 21 serves to precisely space the shielding layer from the pin.
In FIG. 7, there is shown an alternative embodiment of a pinned interposer. This embodiment is substantially similar to that in FIG. 6, with the exception that the pin (43′) includes a second projecting end portion 47′, which projects from the upper surface of the substrate. Portions 47 and 47′ may project the same distance from the respective substrate surface or a different distance, depending on the conductors being inter-coupled. In one embodiment, portions 47′, being of short length, may be coupled to solder ball conductors.
The FIG. 8 embodiment is similar to the FIG. 5 embodiment, with the exception that the opening 41′ formed with dielectric material 31 is larger in diameter than opening 41. In one example, opening 41′ may possess a diameter of from about twelve mils to about sixteen mils. FIG. 8 is understood to be the beginning of a series of steps following those defined above with respect to FIGS. 1-4 toward making what will be referred to as a solder ball interposer, meaning a substrate as shown herein in which a plurality of solder balls are utilized as the conductors for which the interposer is adapted for inter-coupling.
In FIG. 9, a conductive layer 51 is formed on the interior walls of opening 41′. In one embodiment, layer 51 is copper or an alloy thereof and is applied using electroplating. Either electrolytic or electro-less plating may be used for this plating operation. Such methods, like those defined above, are also known in the PCB and chip carrier art and further description is not, therefore, necessary. It is within the scope of the invention to provide metals other than copper or copper alloy. Further, added layers such as nickel and a precious metal such as gold may also be applied, as is also known in the art. In one example, layer 51 may possess a thickness of from about 0.5 mils to about two mils. Layer 51 is also shown to extend out onto the outer surfaces of material 31 on both opposing sides of the substrate. Such extension may result in the formation of the above mentioned “lands” in addition to a projecting signal line (or dogbone structure) (i.e., 53) which may conclude in a pad structure 53′ of about the same thickness as the projecting line but preferably has a larger outer diameter (e.g., is preferably cylindrical). In FIG. 9, two such end portions on lines 53 are shown formed substantially opposite one another. This is not meant to limit the invention as the lines may extend in various directions, including opposing.
In FIG. 10, each of the pads 53′ are shown as having a solder ball 61 positioned thereon. The interposer of FIG. 10 is thus understood to be capable of interconnecting two electrical conductors in the form of such solder balls or the like which may be part of corresponding components such as semiconductor chips, PCBS, chip carriers, etc. By way of example, a chip (on a thin organic substrate) having solder ball conductors may be mounted on the interposer structure of FIG. 10 and the interposer in turn have the lower array of solder balls thereon, each coupled to a respective pad on the lower surface. This assembly may then be positioned on a PCB or chip carrier having an array of conductors (e.g., pads) thereon, and the solder of the lower solder balls re-flowed, thereby forming a solid connection to the respective lower conductors. Other possible combinations for the embodiment shown in FIG. 10 are within the abilities of one skilled in the art and do not require additional description. In one example, the solder balls on the upper part of the interposer may be 90:10 lead:tin solder (or No Lead Solder, i.e., Sn Ag Cu alloy) while those on the interposer's underside may be 63:37 tin:lead solder, these lower solder balls thus having a lower melting point than the upper counterparts. In operation, the internal conductive layer 23 serves to shield the innermost conductive layer 51 during high frequency signal passage through layer 51 (from the solder ball on the upper surface to that on the lower) just as it did for pins 43 and 43′.
FIGS. 11 and 12 represent an alternative embodiment of a solder ball interposer of the invention. The FIG. 11 embodiment is substantially the same as that of FIG. 9, including the internal conductive layer 51 with the addition of a cap or cover 71 formed over the opposed ends of the opening having layer 51 thereon. Each cap is preferably copper or copper alloy and is formed after filling the opening 41′ having conductive layer 51 thereon with either a conductive or non-conductive (electrically) material 73. In one embodiment, material 73 may be copper or silver filled resin (and, therefore, conductive) or silica-filled resin coated copper (and, therefore, non-conductive). Other materials may be used, including, e.g., conventional conductive paste. Material 73 forms a partial base for the cap layer 71, thereby facilitating placement of the caps. Material 73 is hardened prior to such cap formation/placement. In one embodiment, each cap 71 is a copper layer which may be formed from a copper foil or sheet bonded (e.g., laminated) to the substrate and then finalized in configuration using conventional photolithographic processing known in the PCB art for forming circuitry. As seen in FIGS. 11 and 12, the caps 71 also lie atop the “lands” of material 51 which extend over onto the upper and lower substrate surfaces. As such, the caps are relatively rigid and adapted for having various structures coupled thereto. In FIG. 12, one such conductor is a solder ball, each ball coupled to a respective cap 71 as shown. Each solder ball may be the same metallurgy as those defined in FIG. 10, and may form part of similar electrical components. Other combinations are of course possible, as with the FIG. 10 embodiment.
FIG. 13 represents one example of an electrical assembly 81 which may be formed using the teachings of the present invention. Assembly 81 includes the above-defined interposer such as that shown in FIG. 12 (it may be any of those depicted in the other FIGS., however), which is coupled to a substrate 83. In one example, substrate 83 may be a thin laminate film or thin organic substrate having one or more conductive layers therein and a plurality of conductive pads 85 located in a pattern on the film's underside. Only one pad 85 is shown for illustration purposes but as many as 1500 such pads may be used, depending on the operational requirements for assembly 81. In the FIG. 13 embodiment, at least one semiconductor chip 87 is positioned on the film's upper surface and coupled to pads (not shown) using, preferably, solder balls (also not shown). Such solder ball connections for chips is well-known and further detail not required. If the chip's own contact pads are of a greater density than the corresponding pad density for pads 85, suitable through-hole connections (not shown) are used to connect respective ones of the upper surface conductors to pads 85. The thin film laminate may, therefore, be of conventional laminate dielectric material with known internal conductive circuitry, all of which are conventional in the chip carrier art. The invention's interposer is thus understood to be able to couple the chip (more than one, preferably) located on the film's upper surface to a corresponding substrate (e.g., a larger PCB, now shown) directly through the conductive openings formed within the interposer, or through the pins of same if so utilized. In doing so, the conductive openings or pins are protected from the shielding of the formed internal conductive layers. As understood, assembly 81 may be coupled to the lower substrate using solder balls (not shown) if the FIG. 13 embodiment is utilized. Alternatively, pins may be inserted within receptive conductive openings (e.g., conventional through-holes) formed within the substrate. As mentioned earlier, the invention is not limited to LGA connectors. For example, assembly 81 may instead be used as a module, one example being an LGA module, which in turn may be connected to a standard LGA interposer.
Thus there has been shown and described an interposer which is able to interconnect conductive members such that high speed signals may be passed through the interposer and protected (shielded) from unwanted interference. The interposer may be utilized in a fixed embodiment (e.g., soldered to the respective conductors) or as a separable member (e.g., using pins or LGA pads). Significantly, the interposer as defined herein is capable of being manufactured using many conventional PCB and/or chip carrier manufacturing steps, thereby saving considerable time and costs over many known interposers which claim to provide high speed interconnections.
While there have been shown and described what are at present the preferred embodiments of the invention, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the scope of the invention as defined by the appended claims.
Patent Application
20070289773
