Patent Application
20090020876
This invention relates to high temperature packaging for integrated circuits and, more particularly, to diffusion bonding for high temperature semiconductor devices.
Conventional integrated circuits utilize semiconductor devices having silicon base as a substrate for a semiconductor circuit. However, silicon has a drawback of having limited ability to withstand elevated temperatures without sustaining damage, which makes the integrated circuit vulnerable to failure at temperatures between 85° C. and 125° C.
Other types of semiconductor devices may have better ability to withstand high temperatures by using a silicon carbide base instead of silicon. Although effective, the maximum operating temperature of the integrated circuit that uses the silicon carbide is still limited by the packaging of the semiconductor device. For example, the semiconductor can withstand temperatures above 250° C. (482° F.), but bonds that attach the semiconductor device to a substrate or electrical connections between the semiconductor device within the integrated circuit may be vulnerable to thermal fatigue type failure at such temperatures.
Accordingly, there is a need for a high temperature packaging solution for semiconductor devices that enables use at temperatures of about 300° C. (572° F.) or higher.
An example method of forming multiple bonds on an electronic device includes heating first bonding metals at a predetermined temperature to form a first bond comprising a first melting temperature above the predetermined temperature, and heating the first bond and second bonding metals at the predetermined temperature to form a second bond comprising a second melting temperature above the predetermined temperature.
In one example, the method is used to manufacture an electronic device having multiple electronic components that are secured to at least one substrate. To secure the electronic components and the at least one substrate together, a plurality of metal layers are included between each electronic component. The metal layers are heated and diffuse together to form a bond having a desired composition that secures the electronic component and the at least one substrate together.
The various features and advantages of this invention will become apparent to those skilled in the art from the following detailed description of the currently preferred embodiment. The drawings that accompany the detailed description can be briefly described as follows.
The first bond 20 and the second bond 22 include an alloy that secures the respective components 16 and 18 in the desired positions on the substrate 12. The composition of the alloy may be selected from any of a variety of different suitable alloys, and may include a binary system (two metals) or a system including more than two different metals. In one example, the alloy includes a hypoeutectic composition of gold and tin. In a further example, the hypoeutectic composition comprises about 4-10 atomic percent (at %) of tin and a balance of gold. The term “about” as used in this description relative to composition refers to possible variation in the compositional percentage, such as normally accepted variations or tolerances in the art.
Using the hypoeutectic composition provides the benefit of allowing a “recursive” bonding process to be used to form the first bond 20 and the second bond 22. In other systems, compositions other than hypoeutectic, such as hypereutectic, may be used to achieve recursive bonding. Referring to
The layers 32 are deposited in thicknesses that correspond to the desired composition of the first bond 20. In one example for forming an alloy of gold and tin, a gold layer 34 and a tin layer 36 are deposited in desired thicknesses. A ratio of the thickness of the gold layer 34 to the thickness of the tin layer 36 corresponds to the desired composition of gold and tin alloy in the final-formed first bond 20. Likewise, in other systems that utilize other metals or more than two types of metals, the thickness of the layers 32 corresponds to the desired composition of the selected alloy.
After deposition of the layers 32 onto the first component 16 or onto the substrate 12, the layers 32 are heated at a predetermined diffusion temperature, such as at a temperature near the eutectic temperature of the desired alloy. For example, the diffusion temperature is within about 80° C. (176° F.) of the eutectic temperature. In one example for a gold/tin system, the diffusion temperature is about 350° C. (662° F.). Heating at a diffusion temperature near the eutectic temperature causes the layers 32 to diffuse together to form the first bond 20, as shown in
Upon diffusing and cooling, the composition of the formed alloy has a melting temperature that is greater than the diffusion temperature used to form the first bond 20. The higher melting temperature provides the benefit of allowing the first bond 20 to be heated to the diffusion temperature in a subsequent step to form the second bond 22, without melting the first bond 20. Thus, a plurality of such bonds can be “recursively” formed on the substrate 12 or on multiple sections of device without harming the bonds that were previously formed.
Referring to
For example, the diffusion temperature used for gold/tin is about 350° C. (662° F.), while the melting temperature of the example hypoeutectic composition (4-10 at % Sn, remainder Au) given above is about 498° C. (928° F.), which is more than 100° C. (212° F.) greater than the diffusion temperature. As can be appreciated, the electronic device 10 may include additional processes in addition to forming the bonds 20 and 22, such as but not limited to forming other types of bonds or electrical connections, or coating the components 16 and 18 and the bonds 20 and 22 with organic or inorganic dielectric coatings.
The alloy compositions of the first bond 20 and the second bond 22 are stable above 350° C. (662° F.) up to a temperature near 498° C. (928° F.). Thus, in combination with the high temperature capability of the components 16 and 18, the electronic device 10 can withstand operating temperatures beyond the limits of silicon based semiconductors and traditional solder bonded devices.
Although a combination of features is shown in the illustrated examples, not all of them need to be combined to realize the benefits of various embodiments of this disclosure. In other words, a system designed according to an embodiment of this disclosure will not necessarily include all of the features shown in any one of the Figures or all of the portions schematically shown in the Figures. Moreover, selected features of one example embodiment may be combined with selected features of other example embodiments.
The preceding description is exemplary rather than limiting in nature. Variations and modifications to the disclosed examples may become apparent to those skilled in the art that do not necessarily depart from the essence of this disclosure. The scope of legal protection given to this disclosure can only be determined by studying the following claims.
