This application claims the benefit of priority under 35 U.S.C. §119(a) from an application entitled “Integrated circuit package and method for the same” filed in the Korean Intellectual Property Office on Mar. 26, 2007 and assigned Serial No. 2007-29440, the contents of which are hereby incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to an integrated circuit package and a method for the same. More particularly, the present invention relates to a method of attachment between an integrated circuit chip and an attachment subject and a structure using the same.
2. Description of the Related Art
An integrated circuit package is a structure having an integrated circuit chip mounted on a substrate (an attachment subject), e.g. printed circuit substrate, etc. In an integrated circuit package, various functions that constitute a system, such as a logic, a memory, and a device, etc., are integrated in a single structure.
A typical integrated circuit package includes a printed circuit board (PCB), which is typically used as a substrate. The PCB includes an insulating substrate having an electric circuit formed thereon by copper coating or copper plating, and electronic components, such as an integrated circuit chip can be mounted on the printed circuit board.
A chip mounting process is used to mount an embedded IC and/or a stacked IC, etc. onto a PCB. In order to raise the whole degree of integration of an electric device in a system level, a three dimensional mounting method for mounting a chip in a direction of a Z axis has become a popular chip mounting process that increases the usable area of the PCB and leads to improved performance. This mounting method is different from the mounting method for mounting a chip in a direction of a X-Y axis as the third dimension must be taken into consideration in both design and implementation.
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However, the epoxy material, which is used for bonding the integrated circuit chip and the printed circuit substrate with each other, has a coefficient of thermal expansion (CTE) of about 80˜140 ppm/° C. This thermal expansion coefficient shows a remarkable difference compared with a thermal expansion coefficient of ˜2.7 ppm/° C. of silicon (Si), which is mainly used for a substrate material of an integrated circuit chip. Accordingly, a high degree of mechanical stress is generated in an interface between the integrated circuit chip and the printed circuit substrate because of change of heat radiated in operation of a device or hygroscopicity thereof.
Accordingly, the present invention has been made in part to solve at least some of the above-mentioned problems occurring in the prior art, as well as provide additional advantages. The present invention provides an integrated circuit package and a method for construction, which can improve the adhesive strength between an integrated circuit chip and an attachment subject, and minimize the amount of stress in a contact interface of the integrated circuit chip and the attachment subject.
In accordance with an exemplary aspect of the present invention, there is provided an integrated circuit package including: an attachment subject; an integrated circuit chip attached to the attachment subject by an adhesive; and an interface layer disposed between the integrated circuit chip and the adhesive and preferably having a thermal expansion coefficient similar to a thermal expansion coefficient of the integrated circuit chip.
According to the present invention, the adhesives may comprise, for example, an adhesive epoxy, the integrated circuit chip may comprise, for example, a silicon chip, and the attachment subject may comprise, for example, a printed circuit substrate. Furthermore, the interface layer typically has a thermal expansion coefficient of a range of about 3˜5 ppm/° C., and the interface layer may comprise, for example, a material typically having a property of a Young's modulus of a range of about 3˜9 Gpa, a Poisson's ratio of a typical range of about 0.25˜0.4, and a glass temperature typically ranging from about 240° C. 260° C.
Also, according to the present invention, the interface layer may comprise, for example, a material including but not limited to at least one of Polyimide, Acrylinitrilebutadienestyrene (ABS), Benzocyclobutene (BCB), Polystyrene (PS), and Polymethylmethacrylate (PMMA).
In accordance with another exemplary aspect of the present invention, there is provided a method of connecting an integrated circuit chip and an attachment subject to each other while interposing an adhesive between the integrated circuit chip and the attachment subject, the method including the steps of: applying the adhesive on the attachment subject; and forming an interface layer between the integrated circuit chip and the adhesive, the interface layer preferable having a thermal expansion coefficient similar to a thermal expansion coefficient of the integrated circuit chip.
In accordance with the above-mentioned example of a method according to the present invention, the integrated circuit chip may comprise, for example, a silicon chip, the attachment subject may comprise, for example, a printed circuit substrate, and the adhesive may comprise, for example, adhesive epoxy.
Also, the interface layer preferably has a thermal expansion coefficient of a range of about 3˜55 ppm/° C.
The above and other exemplary aspects, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:
Hereinafter, exemplary and preferred embodiments of the present invention will be described with reference to the accompanying drawings. A person of ordinary skill in the art understands that the present invention is not limited to the following description and drawings, as such examples have been provided for illustrative purposes, and do not limit the invention to the examples shown and described. Further, in the following description of the present invention, a detailed description of known functions and configurations incorporated herein may be omitted when such known functions and configurations would obscure appreciation of the subject matter of the present invention by a person of ordinary skill in the art.
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The interface layer 210 may be formed in such a manner that a spin coating is formed on a real surface of the silicon chip 204, or the polymer material is directly stacked.
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Furthermore, according to the present invention, as the adhesive strength between the epoxy adhesives and the polyimide is stronger than the adhesive strength between the silicon and epoxy adhesive, the problem of delamination often reduced and/or eliminated in many cases.
As described in the above examples, in the structure wherein an integrated circuit chip and the attachment subject are connected to each other by adhesives, the present invention reduces stress and prevents a decrease of adhesive strength caused by differences of the thermal expansion coefficient, and/or differences of properties between the integrated circuit chip and adhesive, so that generation of delamination can be minimized and the interconnection lines between the interior and the exterior of the integrated circuit chip can be protected.
Furthermore, at least one advantage of the present invention is that an interface which is stable in thermal hysteresis and hygroscopicity is formed, thereby improving reliability of the integrated circuit chip and making it possible to implement a large scale package.
While the invention has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit of the invention and the scope of the appended claims. For example, the type of integrated circuit, interface, and attachment subject are not limited to the examples described herein. Also, with regard to the similarity of the properties, the range of thermal expansion coefficient of the interface layer can be a subset of the range of thermal expansion coefficient of the integrated circuit chip, or the range of thermal expansion coefficient of the integrated circuit chip can be a subset of the range of thermal expansion coefficient of said interface layer, or a range of thermal expansion coefficient of said interface layer and a range of thermal expansion coefficient of the integrated circuit chip may overlap.
Number | Date | Country | Kind |
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2007-29440 | Mar 2007 | KR | national |