Claims
- 1. A method of fabricating an integrated circuit structure having a barrier layer at contact locations, comprising the acts of:forming a doped semiconductor region at a semiconducting surface of a body; forming a dielectric film over said doped region, said dielectric film having a contact opening therethrough; after the step of forming a dielectric film, depositing a first layer comprising titanium metal in contact with the surface of the doped region and overlying the dielectric layer; exposing the structure to an oxygen-bearing atmosphere; annealing the structure to form from said first titanium metal layer a first titanium oxynitride layer overlying a titanium disilicide layer over the surface of the doped region within the contact opening; depositing a second titanium metal layer over the structure; depositing a layer of titanium nitride over the second titanium metal layer in a vacuum between about 4 mTorr and about 10 mTorr and at a substrate temperature of equal to or less than about 100° C.; exposing the structure to an oxygen-bearing atmosphere; and after the exposing step, annealing the structure to form from said second titanium metal layer a second titanium oxynitride layer overlying said first titanium oxynitride layer.
- 2. The method of claim 1, wherein the annealing steps are each performed by a rapid thermal anneal.
- 3. The method of claim 2, wherein each rapid thermal anneal step is performed in a nitrogen atmosphere.
- 4. The method of claim 1, wherein each step of exposing the structure to an oxygen-bearing atmosphere comprises:exposing the structure to air.
- 5. The method of claim 1, further comprising depositing metallization over the structure and within the contact opening.
- 6. The method of claim 5, wherein said metallization comprises aluminum.
Parent Case Info
This application is a division of application Ser. No. 08/980,468, filed Nov. 28, 1997, U.S. Pat. No. 6,191,033, which is a division of application Ser. No. 081437,870, filed May 9, 1995, abandoned, which is a division of application Ser. No. 08/235,099, filed 04/29/1994, U.S. Pat. No. 5,514,908.
US Referenced Citations (7)
Foreign Referenced Citations (1)
Number |
Date |
Country |
0 545 602-A1 |
Jun 1993 |
EP |
Non-Patent Literature Citations (2)
Entry |
Inoue, M., et al., “The Properties of Reactive Sputtered TiN Films for VLSI Metallization”, VMIC Conference, Jun. 13-14, 1988, pp. 205-206.* |
Wolf, S., et al., Silicon Processing for the VLSI Era, vol. 1, 1986, Lattice Press, pp. 56-58. |