Patent Application
20230133484
The present disclosure relates to integrated circuits, and more particularly, to interconnects.
As integrated circuit scaling continues, it is becoming increasingly difficult to scale interconnects to simultaneously satisfy interconnect density and resistance needs. In particular, while interconnect metal line widths (in the x-plane) shrink to support line density, the line heights (in the y-plane) do not shrink as much. This maintaining of line height helps dampen the significant increase in line resistance caused by the line width scaling. Such increased line resistance is due to electron scattering from roughness, and grain boundary, as well as limited grain size. However, the high aspect ratio (height-to-width) of the metal lines involves filling high aspect ratio interconnect features, whether it be filling recesses with conductive material to form the metal lines themselves or filling recesses with dielectric material to form dielectric structures between to metal lines. In any such cases, the higher the height-to-width aspect ratio of the trench to be filled, the more difficult to successfully fill that trench. To this end, there are a number of non-trivial issues associated with scaling interconnects.
As will be appreciated, the figures are not necessarily drawn to scale or intended to limit the present disclosure to the specific configurations shown. For instance, while some figures generally indicate perfectly straight lines, right angles, and smooth surfaces, an actual implementation of an integrated circuit structure may have less than perfect straight lines, tapered sidewalls, rounded corners, and some features may have surface topology or otherwise be non-smooth, given real world limitations of the processing equipment and techniques used. Likewise, while the thickness of a given first layer may appear to be similar in thickness to a second layer, in actuality that first layer may be much thinner or thicker than the second layer; same goes for other layer or feature dimensions.
An integrated circuit structure has a first layer having a recess that extends into the first layer. A second layer is within the recess and comprises a metal or a dielectric. A third layer is within the recess and between the first and second layers, the third layer including a material that resonates at microwave frequencies (e.g., 2.4 to 2.5 Gigahertz). In some cases, for example, the third layer material includes: (1) oxygen along with indium and/or zinc (e.g., indium tin oxide; indium gallium zinc oxide; indium tungsten oxide; or zinc oxide); or (2) diethylene glycol dibenzoate. In some example cases, such as where the first layer comprises a dielectric (e.g., silicon dioxide or other interlayer dielectric) and second layer comprises a metal (e.g., copper), the integrated circuit may further include a relatively thin fourth layer (e.g., barrier layer including tantalum or titanium) between the second and third layers. The third layer resonates in response to microwave annealing and allows for selective reflow and/or grain growth of the second layer. In particular, the third layer heats the second layer (and any barrier layer, if present). For metals, the thermal conduction is relatively high and hence the third layer readily heats the metal volume of the second layer; for dielectrics, the thermal conduction is lower, but the heat generated by the third layer can still cause some reflow of dielectric volume of the second layer in relatively narrow width trenches (e.g., for better gap fill in high aspect ratio trenches). Previously provisioned layers of the integrated circuit (e.g., the device layer or other layers not in contact with the third layer) do not resonant at microwave frequency range and hence there is no source to absorb microwave energy and heat-up. Numerous embodiments and variations will be appreciated in light of this disclosure.
As previously noted above, the aspect ratio of interconnect metal lines increases so does the aspect ratio of interconnect features to be filled with dielectric or metal, and filling such high aspect ratio interconnect features can be problematic. For instance, when filling such high aspect ratio trenches, pinch-off can occur at the opening of the trench being filled, which in turn prevents the lower portion of that trench from being filled (poor gap fill). One option to address this poor gap fill is to heat the deposited material by an anneal process to reflow and/or increase grain size of the deposited material. However, such an option may not be appropriate for all applications. For example, flash and laser anneal are suitable to cause an increase in grain size and reflow of the deposited material, but they are not selective anneals in that they also affect other layers in addition to the target layer. Thus, such anneals cannot be used extensively without causing damage to the integrity of the underlying or otherwise previously deposited layers. To this end, for example, the thermal budget for backend or otherwise subsequent interconnect formation is limited due to thermal sensitivity of the previously formed device layer, which includes sensitive materials and componentry such as high-k dielectrics and transistor junctions. Shorter duration anneals (e.g., micro-second and nano-second anneals) may cause less collateral damage, but the thermal energy from such short anneals is limited and thus may not be able to induce sufficient reflow and/or grain growth. Another possible option for better gap fill is to use a more complex deposition process, such as a relatively slow atomic layer deposition (ALD) process, or an iterative deposit-etch-deposit process. Such processes, however, can be relatively expensive and moreover may not be successful without an anneal-based reflow, particularly when forming interconnect features in high aspect ratio trenches.
Thus, techniques are disclosed for providing highly scalable interconnects. Although the techniques can be used in any interconnect processes, they are particularly useful in backend interconnects having high aspect ratio features. In an example, a thin conformal film (liner) is deposited on the sidewalls of a trench to be filled, and a conductive fill material is deposited into the trench on the liner. In other such examples, there may be a barrier layer between the liner and the conductive fill material (e.g., to inhibit electromigration of copper into surrounding dielectric material). In any such cases, a microwave anneal is then conducted. The liner is configured to resonate at the microwave frequency range and thus absorbs microwave energy to selectively anneal (heat) the conductive fill material to modify its structure (grain size) and/or gap fill. In another example, the fill material is a dielectric. In such cases, the liner allows for better gap fill and densification of the dielectric material. In any such cases, the anneal is selective to the deposited fill material and other layer(s) that the liner is in contact with, and other layers (such as layers in the device layer or layers within bit cells) are not subjected to heat. This selective nature maintains the integrity of previously deposited thin films or otherwise sensitive materials and devices.
Some examples of materials that resonate at microwave frequencies (e.g., 2.4-2.5 GHz) or otherwise absorb microwave energy and can be used for the liner are (a) organic thin films like diethylene glycol dibenzoate (DEGDB), and (b) inorganic thin films like doped indium and zinc based oxides (e.g., indium tin oxide; indium gallium zinc oxide; indium tungsten oxide; or zinc oxide). Example materials that do not resonate at microwave frequencies include, for instance, silicon, silicon dioxide, titanium, titanium nitride, tantalum, and tantalum nitride; such materials thus have no source to absorb microwave energy and heat-up. The liner materials can be deposited by conformal deposition techniques like atomic layer deposition (ALD) or chemical vapor deposition (CVD). The thickness of the liner can vary from one embodiment to the next, but in some example cases is in the range of one to three monolayers to 40 angstroms, such as 5-30 angstroms.
Note that the conductivity (or resistivity, as the case may be) of the liner material can be tuned to maximize or otherwise achieve a desired level of microwave energy absorption. For example, relatively high microwave energy absorption can be achieved when the liner has a conductivity in the range of about 1000-10000 siemens per meter (S/m). In terms of resistivity, a relatively high microwave energy absorption can be achieved when the liner has a resistivity in the range of about 10−4 to 10−3 ohm meters (Ω·m). To this end, the conductivity (or resistivity) of the microwave absorbing liner plays a role in the microwave interaction (e.g., in terms of absorption and reflection of energy and conduction within the liner material). Further note that the liner actually heats any material with which it is in contact. The amount of heat imparted by the microwave-resonant liner into its neighboring layer(s) will depend on factors such as the surface area of the contact as well as the material being heated and the thickness or volume of that material.
So, for instance, consider the example case where the liner is deposited on the walls of a high aspect ratio recess (e.g., trench or via having a height-to-width ratio of 4:1 or higher (e.g., 5:1, 6:1, 7:1, etc.) in a relatively large volume of dielectric material (e.g., silicon dioxide), and the fill material is a metal (and possibly with a metal-containing barrier layer between the liner and the metal fill material). For such metal and metal-containing materials, the heat conduction is relatively high and hence the liner readily heats the volume of metal fill material (and any metal-containing barrier layer, if present). Example fill metals include, for instance, copper, aluminum, tungsten, molybdenum, ruthenium, or alloys of same. Example barrier materials include tantalum, titanium or nitrides of same (e.g., titanium nitride, tantalum nitride, titanium silicon nitride, tantalum silicon nitride). On the other hand, the thermal conduction for the relatively large volume of dielectric on which the liner sits is relatively poor, so that relatively large bulk of dielectric material will not be sufficiently heated so as to reflow or otherwise materially change in its structure.
Further consider the example case where the liner is deposited on the walls of a high aspect ratio recess that is similar to that above but in a relatively large volume of a metal-containing material, and the relatively smaller volume of fill material is a dielectric (and possibly with a metal-containing barrier layer between the liner and the dielectric fill material). Even though the heat conduction in dielectric fill material is relatively poor, the heat generated by the liner may be sufficient to heat the smaller volume of dielectric material within the high aspect ratio recess so as to achieve at least some reflow in that volume of dielectric material. To this end, the liner can be used to heat dielectric material in high aspect ratio narrow openings to achieve better gap fill, according to some examples. Example dielectric materials that can be reflowed include, for instance, silicon dioxide, or low-k variants such as silicon dioxide doped with carbon, hydrogen, nitrogen, or fluorine.
In any such cases, the microwave-based anneal can be carried out to selectively heat the layers in contact with the liner. In some embodiments, the range of microwave energy used during the anneal process is in the range of 2.4-2.5 Gigahertz (e.g., 2.45 GHz). The duration of the anneal can vary from one embodiment to the next, and depends on factors such as the volume to be heated and the thickness of the liner. The greater the volume and/or the thicker the liner, the longer the anneal may be. An example duration is in the range of several seconds to several minutes, although some examples may call for an even longer duration. Use of the techniques provided herein will manifest in a number of ways. For example, cross-sectional imaging of the interconnect layers by way of scanning electron microscopy or SEM, transmission electron microscopy or TEM, or other suitable inspection tool will reveal the use of a microwave absorbing liner, as variously described herein.
As will be appreciated, other interconnect structure configurations including conductive features having any number of profiles, geometries, and functions can benefit from the techniques provided herein and the present description is not intended to be limited to this particular interconnect layout. As will further be appreciated, other portions of the integrated circuit not shown in these cross-sections can vary from one embodiment to the next. For instance, there may be a device layer below (or above, as the case may be) these interconnect layers, the device layer including a plurality of transistor devices, the interconnect layers providing interconnect to one or more of those transistor devices. The interconnect layers may be part of, for instance, a local interconnect structure just above or below a device layer, or part of a relatively deep backend interconnect structure (e.g., any two neighboring layers of metallization layers M1-M9 above a given device layer). In another example case, the interconnect layers may be part of a memory structure (e.g., dynamic random access memory) that includes an array of bit cells (e.g., 1T-1C bit cells), the interconnect layers providing control signals (e.g., wordline and bitline control signals) to one or more of those bitcells.
The dielectric layer 103 may be implemented with any suitable dielectric or insulator materials, such as silicon dioxide, silicon carbide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, organic polymers (e.g., perfluorocyclobutane or polytetrafluoroethylene), fluorosilicate glass, and organosilicates (e.g., silsesquioxane, siloxane, or organosilicate glass). The dielectric material may be low-k (e.g., k<3.9), standard-k, or high-k (e.g., k>7) depending on the desired isolation and capacitance, and may include pores or voids to further reduce its dielectric constant. Although only two recesses are shown, the dielectric layer 103 may include any number of recesses (e.g., holes for vias, or trenches conductive runs). The recesses can be formed in the dielectric layer, for example, using lithography including via and/or trench patterning and subsequent etch processes (e.g., wet and/or dry etch techniques) followed by planarization, polishing, cleans, or other desired processing. The recess dimensions can vary from one example embodiment to the next. In some example cases, the recess has an opening that is in the range of about 5 nanometers (nm) to 50 nm (e.g., 10 to 25 nm) and a depth in the range of about 5 nm to 500 nm (e.g., 25 to 250 nm), and the recess has an aspect ratio (D2:D1) in the range of about 1:1 to 20:1 (e.g., 5:1). In a more general sense, the recess can any recess including those in which it is difficult to obtain sufficient fill.
The liner 105 can be, for example, a thin conformal film that is conformally deposited (e.g., via ALD, CVD, or other conformal deposition process) on the sidewalls of the recesses to be filled. Any excess liner material (such as that on the field above the recesses) can be removed along with any excess fill material, for instance, using a chemical mechanical planarization (CMP) process. The thickness of the liner 105 can vary from one embodiment to the next, but in some cases is in the range of one to several monolayers to 40 angstroms, such as 5-30 angstroms. The liner 105 is configured to resonate at the microwave frequency range and thus absorbs microwave energy to selectively anneal (heat) the fill material 107a-b to improve gap fill and densification (as shown with 107a in
Liner 105 heats material with which it is in contact, including the fill material 107a-b. The amount of heat imparted by liner 105 into its neighboring layer(s) will depend on factors such as the surface area of the contact as well as the material being heated and the volume of that material. So, for instance, consider the example case where liner 105 is deposited on the walls of a high aspect ratio recess (e.g., trench or via having a height-to-width ratio of 4:1 or higher (e.g., 5:1, 6:1, 7:1, etc.) in a relatively large volume of dielectric material 103 (e.g., silicon dioxide), and fill material 107a-b is a metal (and possibly with a relatively thin metal-containing barrier layer between liner 105 and metal fill material 107a-b). For such metal and metal-containing materials, the heat conduction is relatively high and hence liner 105 readily heats the volume of metal fill material 107a-b (and any metal-containing barrier layer, if present). Example fill conductive fill materials 107a-b include, for instance, copper, aluminum, tungsten, molybdenum, ruthenium, or alloys of same, which can be deposited for example by CVD, ALD, electroplating, or other suitable fill material deposition process. Example barrier materials include tantalum, titanium or nitrides of same (e.g., titanium nitride, tantalum nitride, titanium silicon nitride, tantalum silicon nitride), which can be deposited for example by ALD, CVD, or other conformal deposition process. Note that the relative thinness (e.g., 5-30 angstroms) of a given barrier layer allows the heat from the liner to thermally conduct through the barrier layer and into the fill material 107a-b. The thermal conduction for the large volume of dielectric 103 on which liner 105 sits is relatively poor, so that dielectric material 103 will not be sufficiently heated so as to reflow or otherwise materially change in its structure.
In the examples shown in
In some example cases, the trench opening in the upper layer is about 10 nm to 100 nm (e.g., 20 to 50 nm), and the via opening in the middle layer is about 5 nm to 50 nm (e.g., 10 to 25 nm), and the entire dual-damascene structure has an average height-to-width aspect ratio in the range of about 30:1 to 5:1 (e.g., 10:1). Note that an average width of the dual-damascene structure can be calculated by taking a first width at the mid-portion of the trench in the upper layer, and a second width at the mid-portion of the via in the middle layer, and taking the average of those two widths. The average width can then be used along with the overall height of the dual-damascene structure, to determine the average height-to-width aspect ratio of that trench. As will be appreciated, the geometry and configuration of the dual-damascene structure can vary from one embodiment to the next, and the present description is not intended to be limited to any particular configuration.
Etch stop layers 102 can be, for example, silicon nitride or silicon oxynitride or silicon carbide, or any other material that provides etch selectivity with respect to layer 103. In one example case, etch stop layers 102 include a nitride (e.g., silicon nitride) and layer 103 includes an oxide (e.g., silicon dioxide). Etch stop layers can be provided, for example, by ALD, CVD, or other conformal deposition process.
As can be further seen, a substrate of the device layer is configured with various DRAM cell components integrated therein, such as access transistor T and word line WL. Such DRAM devices may include a plurality of bit cells, with each cell generally including a storage capacitor communicatively coupled to a bitline by way of an access transistor that is gated by a word line. Other standard or proprietary DRAM components and features may also be included (e.g., row and column select circuitry, sense circuitry, power select circuitry, etc.). Each layer includes various metal lines (M1, M1′, M2, and M2′) and corresponding vias (V0, V0′, V1, and V1′) formed within respective dielectric layers 103. Each layer 103 in this example structure is generally isolated or otherwise demarcated from neighboring layers by an etch stop layer 102. In addition, each metal line and via of this example embodiment is configured with a liner 105, as previously discussed. And as further noted, other embodiments may include barrier layer 106 between liner 105 and the fill material making up the trench/via structures. The trench/via structures correspond to fill materials 107a-b.
Any number of suitable substrates can be used to implement the substrate, including bulk substrates (e.g., silicon, germanium, III-V materials, etc.), semiconductor-on-insulator substrates (XOI, where X is a semiconductor material such as silicon, germanium or germanium-enriched silicon), and multi-layered structures such as those suitable for forming nanowire and nanoribbon channel regions. In one specific example case, the substrate is a silicon bulk substrate. In other implementations, the substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group III-V or group IV materials may also be used to form the substrate. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which an integrated circuit having interconnects and/or conductive features configured with a microwave-resonant liner as variously described herein may be used.
The method continues with depositing 503 a microwave-resonant liner into the one or more recesses. Conformal deposition processes such as ALD and/or CVD processes can be used to deposit the liner. The previous discussion with respect to liner materials and geometry is equally applicable here. The method continues with depositing 505 fill material into the trenches and on the liner. In some cases, the method includes depositing a barrier layer on the liner, prior to depositing the fill material. The previous discussion with respect to fill and barrier materials and geometry is equally applicable here. The method continues with selectively annealing 507, via microwave energy, the fill material to increase grain size (e.g.,
The communication chip 606 enables wireless communications for the transfer of data to and from the computing system 600. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 606 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing system 600 may include a plurality of communication chips 606. For instance, a first communication chip 606 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 606 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. The processor 604 of the computing system 600 includes an integrated circuit die packaged within the processor 604. In some example embodiments of the present disclosure, the integrated circuit die of the processor 604 includes one or more occurrences of a microwave-resonant liner as variously provided herein. The term “processor” may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
The communication chip 606 may also include an integrated circuit die packaged within the communication chip 606. In accordance with some such example embodiments, the integrated circuit die of the communication chip 606 includes one or more occurrences of a microwave-resonant liner as variously provided herein. As will be appreciated in light of this disclosure, note that multi-standard wireless capability may be integrated directly into the processor 604 (e.g., where functionality of any chips 606 is integrated into processor 604, rather than having separate communication chips). Further note that processor 604 may be a chip set having such wireless capability. In short, any number of processor 604 and/or communication chips 606 can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.
In various implementations, the computing system 600 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the system 600 may be any other electronic device that processes data or employs interconnect structures configured with microwave-resonant liners as variously provided herein. As will be appreciated in light of this disclosure, various embodiments of the present disclosure can be used to improve performance on products fabricated at any process node (e.g., in the micron range, or sub-micron and beyond).
The following examples pertain to further embodiments, from which numerous permutations and configurations will be apparent.
Example 1 includes an integrated circuit, comprising: a first layer comprising dielectric material, the first layer having a recess that extends into the dielectric material; a second layer within the recess and comprising a metal; and a third layer within the recess and between the first layer and the second layer, the third layer comprising a material that resonates at microwave frequencies.
Example 2 includes the integrated circuit of Example 1, wherein the metal of the second layer is a first metal, and the integrated circuit comprises a fourth layer between the second layer and the third layer, the fourth layer comprising a second metal elementally different from the first metal.
Example 3 includes the integrated circuit of Example 2, wherein: the dielectric material of the first layer comprises silicon and oxygen; the first metal of the second layer comprises copper; the material of the third layer comprises either (1) oxygen along with indium and/or zinc, or (2) diethylene glycol dibenzoate (DEGDB); and the second metal of the fourth layer comprises titanium or tantalum.
Example 4 includes the integrated circuit of Example 3, wherein the material of the third layer comprises: indium, tin, and oxygen; indium, gallium, zinc, and oxygen; indium, tungsten, and oxygen; or zinc and oxygen.
Example 5 includes the integrated circuit of Example 3, wherein the material of the third layer comprises diethylene glycol dibenzoate (DEGDB).
Example 6 includes the integrated circuit of any one of Examples 1 through 5, wherein the metal of the second layer comprises at least one of copper, aluminum, tungsten, molybdenum, or ruthenium.
Example 7 includes the integrated circuit of any one of Examples 1 through 6, wherein the dielectric material of the first layer comprises silicon and oxygen.
Example 8 includes the integrated circuit of any one of Examples 1 through 7, wherein the dielectric material of the first layer includes at least one of carbon, hydrogen, nitrogen, or fluorine.
Example 9 includes the integrated circuit of any one of Examples 1 through 8, wherein the material of the third layer resonates at frequencies in the range of 2.4 gigahertz to 2.5 gigahertz.
Example 10 includes the integrated circuit of any one of Examples 1 through 9, wherein the third layer has a thickness in the range of 5 angstroms to 30 angstroms.
Example 11 includes the integrated circuit of any one of Examples 1 through 10, wherein the recess is a dual damascene recess.
Example 12 includes the integrated circuit of any one of Examples 1 through 11, and further includes a plurality of transistor devices above or below the first layer, wherein at least one of the transistor devices is connected to the second layer.
Example 13 includes the integrated circuit of any one of Examples 1 through 12, wherein the material of the third layer comprises: oxygen along with indium and/or zinc; or diethylene glycol dibenzoate (DEGDB).
Example 14 includes the integrated circuit of Example 13, wherein the material of the third layer comprises: indium, tin, and oxygen; indium, gallium, zinc, and oxygen; indium, tungsten, and oxygen; or zinc and oxygen.
Example 15 includes the integrated circuit of Example 13, wherein the material of the third layer comprises diethylene glycol dibenzoate (DEGDB).
Example 16 is an electronic system comprising the integrated circuit of any one of Examples 1 through 15. The electronic system may be, for instance, a general-purpose computer (e.g., laptop or desktop) or mobile communication device (e.g., smartphone) or a special-purpose computer (e.g., game console or measurement system).
Example 17 is microprocessor or memory chip comprising the integrated circuit of any one of Examples 1 through 15.
Example 18 is an integrated circuit, comprising: a first layer comprising dielectric material, the first layer having a recess that extends into the dielectric material, the dielectric material including silicon and oxygen; a second layer within the recess and comprising copper or aluminum; a third layer within the recess and between the first layer and the second layer, the third layer comprising a material that resonates at microwave frequencies; and a fourth layer between the second layer and the third layer, the fourth layer comprising at least one of titanium or tantalum.
Example 19 includes the integrated circuit of Example 18, wherein the recess is a dual damascene recess.
Example 20 includes the integrated circuit of Example 18 or 19, wherein the material of the third layer comprises: indium, tin, and oxygen; indium, gallium, zinc, and oxygen; indium, tungsten, and oxygen; or zinc and oxygen.
Example 21 includes the integrated circuit of Example 18 or 19, wherein the material of the third layer comprises diethylene glycol dibenzoate (DEGDB).
Example 22 is an integrated circuit, comprising: a first layer comprising dielectric material, the first layer having a recess that extends into the dielectric material; a second layer within the recess and comprising a metal; and a third layer within the recess and between the first layer and the second layer, the third layer including (1) oxygen along with indium and/or zinc, or (2) diethylene glycol dibenzoate (DEGDB).
Example 23 includes the integrated circuit of Example 22, wherein the metal of the second layer is a first metal, and the integrated circuit comprises a fourth layer between the second layer and the third layer, the fourth layer comprising a second metal elementally different from the first metal.
Example 24 includes the integrated circuit of Example 23, wherein the dielectric material of the first layer comprises silicon and oxygen; the first metal of the second layer comprises copper; and the second metal of the fourth layer comprises titanium or tantalum.
Example 25 includes the integrated circuit of any one of Examples 22 through 24, wherein the metal of the second layer comprises at least one of copper, aluminum, tungsten, molybdenum, or ruthenium.
Example 26 includes the integrated circuit of any one of Examples 22 through 25, wherein the dielectric material of the first layer comprises silicon and oxygen.
Example 27 includes the integrated circuit of any one of Examples 22 through 26, wherein the dielectric material of the first layer includes at least one of carbon, hydrogen, nitrogen, or fluorine.
Example 28 includes the integrated circuit of any one of Examples 22 through 27, wherein the material of the third layer comprises: indium, tin, and oxygen; indium, gallium, zinc, and oxygen; indium, tungsten, and oxygen; or zinc and oxygen.
Example 29 includes the integrated circuit of any one of Examples 22 through 27, wherein the material of the third layer comprises diethylene glycol dibenzoate (DEGDB).
Example 30 is an integrated circuit, comprising: a first layer having a recess that extends into the first layer; a second layer within the recess and comprising a metal or a dielectric; and a third layer within the recess and between the first layer and the second layer, the third layer including (1) oxygen along with indium and/or zinc, or (2) diethylene glycol dibenzoate (DEGDB).
Example 31 includes the integrated circuit of Example 30, and further includes a fourth layer between the second layer and the third layer.
Example 32 includes the integrated circuit of Example 30, wherein the first layer comprises silicon and oxygen; the second layer comprises copper; and the fourth layer comprises titanium or tantalum.
Example 33 includes the integrated circuit of any one of Examples 30 through 32, wherein the second layer comprises at least one of copper, aluminum, tungsten, molybdenum, or ruthenium.
Example 34 includes the integrated circuit of any one of Examples 30 through 33, wherein the first layer comprises silicon and oxygen.
Example 35 includes the integrated circuit of any one of Examples 30 through 34, wherein the first layer includes at least one of carbon, hydrogen, nitrogen, or fluorine.
Example 36 includes the integrated circuit of any one of Examples 30 through 35, wherein the third layer comprises: indium, tin, and oxygen; indium, gallium, zinc, and oxygen; indium, tungsten, and oxygen; or zinc and oxygen.
Example 37 includes the integrated circuit of any one of Examples 30 through 35, wherein the third layer comprises diethylene glycol dibenzoate (DEGDB).
Example 38 is a method for forming an integrated circuit, the method comprising: forming a first layer having a recess that extends into the first layer; forming a second layer within the recess, the second layer including (1) oxygen along with indium and/or zinc, or (2) diethylene glycol dibenzoate (DEGDB); and forming, after forming the second layer, a third layer within the recess and comprising a metal or a dielectric.
Example 39 includes the method of Example 38, wherein forming the first layer includes patterning an interconnect layer and etching to form one or more trenches within the interconnect layer, the recess being one of the one or more trenches.
Example 40 includes the method of Example 38 or 39, wherein forming the second layer includes conformally depositing the second layer in the one or more trenches, prior to forming the third layer.
Example 41 includes the method of Example 40, wherein forming the third layer includes: depositing fill material into the one or more trenches, the fill material being one of the metal or the dielectric of the third layer; and selectively annealing, via microwave energy, the fill material to increase grain size and/or improve gap fill.
Example 42 includes the method of Example 41, wherein selectively annealing, via microwave energy, the fill material to increase grain size and/or improve gap fill is performed for a period in the range of 3 seconds to 30 minutes.
Example 43 includes the method of Example 41 or 42, wherein selectively annealing, via microwave energy, the fill material to increase grain size and/or improve gap fill is performed at a frequency in the range of 2.4 gigahertz to 2.5 gigahertz.
Example 44 includes the method of any one of Examples 38 through 43, wherein after forming the second layer and before forming the third layer, the method includes forming a fourth layer within the recess.
Example 45 includes the method of Example 44, wherein the first layer comprises silicon and oxygen; the third layer comprises copper; and the fourth layer comprises titanium or tantalum.
Example 46 includes the method of any one of Examples 38 through 45, wherein the third layer comprises at least one of copper, aluminum, tungsten, molybdenum, or ruthenium.
Example 47 includes the method of any one of Examples 38 through 46, wherein the first layer comprises silicon and oxygen.
Example 48 includes the method of any one of Examples 38 through 47, wherein the first layer includes at least one of carbon, hydrogen, nitrogen, or fluorine.
Example 49 includes the method of any one of Examples 38 through 48, wherein the second layer comprises: indium, tin, and oxygen; indium, gallium, zinc, and oxygen; indium, tungsten, and oxygen; or zinc and oxygen.
Example 50 includes the method of any one of Examples 38 through 48, wherein the second layer comprises diethylene glycol dibenzoate (DEGDB).
The foregoing description of example embodiments of the present disclosure has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the present disclosure be limited not by this detailed description, but rather by the claims appended hereto.
