Patent Grant
10297502
The present invention relates to structures and methods for providing micro-transfer printable integrated circuits on semiconductor substrates using isolation structures.
Integrated circuits (ICs) are widely used in electronic devices. Integrated circuits are typically formed on a semiconductor wafer using photolithographic processes and then packaged, for example in a ceramic or plastic package, with pins or bumps on the package providing externally accessible electrical connections to the integrated circuit.
In some applications, the bare integrated circuit dies are not separately packaged but are placed on a destination substrate and electrically connected on the destination substrate, for example using photolithographic or printed-circuit board methods, to form an electronic system. However, this can be difficult to accomplish when the integrated circuits are small. Thus, an efficient method of transferring bare dies from a relatively small and expensive source substrate (e.g., crystalline semiconductor) to a relatively large and inexpensive destination substrate (e.g., amorphous glass or plastic) is very desirable, since the integrated circuits can provide much higher data processing efficiency than thin-film semiconductor structures formed on large substrates.
One approach to handling and placing small integrated circuits (chiplets) uses micro-transfer printing, for example as described in U.S. Pat. Nos. 8,722,458, 7,622,367 and 8,506,867, each of which is hereby incorporated by reference in its entirety. In these methods, an integrated circuit is formed on a source wafer, for example a semiconductor wafer, and undercut by etching a gap between a bottom side of the integrated circuit and the wafer. A stamp contacts a top side of the integrated circuit to adhere the integrated circuit to the stamp, the stamp and integrated circuit are transported to a destination substrate, for example a glass or plastic substrate, the integrated circuit is contacted and adhered to the destination substrate, and the stamp removed to “print” the integrated circuit from the source wafer to the destination substrate. Multiple integrated circuits can be “printed” in a common step with a single stamp. The integrated circuits can then be electrically connected using conventional photolithographic and printed-circuit board methods. This technique has the advantage of locating many (e.g., tens of thousands to millions) small integrated circuit devices on a destination substrate in a single print step. For example, U.S. Pat. No. 8,722,458 teaches transferring light-emitting, light-sensing, or light-collecting semiconductor elements from a wafer substrate to a destination substrate using a patterned elastomer stamp whose spatial pattern matches the location of the semiconductor elements on the wafer substrate.
The micro-transfer printing process requires constructing releasable (micro-transfer printable) integrated circuits on a source substrate. The releasable integrated circuits are typically formed using photolithographic methods and materials. There is a need, however, for improvements in processes and structures for making robust releasable integrated circuit in a reliable, efficient, and cost-effective manner.
In an embodiment of the present invention, a semiconductor structure suitable for micro-transfer printing includes a semiconductor substrate and a patterned insulation layer disposed on or over the semiconductor substrate. The insulation layer pattern defines one or more etch vias in contact with the semiconductor substrate. Each etch via is exposed. A semiconductor device is disposed on the patterned insulation layer and is surrounded by an isolation material in one or more isolation vias that are adjacent to the etch via. The etch via can be at least partially filled with a semiconductor material that is etchable with a common etchant as the semiconductor substrate. Alternatively, the etch via is empty and the semiconductor substrate is patterned to form a gap that separates at least a part of the semiconductor device from the semiconductor substrate and forms a tether physically connecting the semiconductor device to an anchor portion of the semiconductor substrate or the patterned insulation layer.
In an embodiment, the isolation material and the insulation layer include the same material. In another embodiment, the semiconductor substrate and the semiconductor device include at least some of the same materials.
The semiconductor substrate can include a plurality of isolation vias surrounding a corresponding plurality of semiconductor devices with each isolation via adjacent to an etch via. In one configuration, a different etch via is adjacent to each semiconductor device. In another configuration, a common etch via is adjacent to two or more semiconductor devices. In one embodiment, the etch via is surrounded by the patterned insulation layer to form a surrounding anchor structure. In another embodiment, the anchor structure is substantially linear. The etch via can be at least partially filled with a semiconductor material that is etchable with a common etchant that etches the semiconductor substrate. Alternatively, the etch via can be empty and the semiconductor substrate is patterned to form a gap that separates at least a part of the semiconductor device from the semiconductor substrate and forms a tether physically connecting the semiconductor device to an anchor portion of the semiconductor substrate or the patterned insulation layer.
In various configurations, the semiconductor device is an integrated circuit, is a light-emitting diode, includes a diode, or includes a transistor. The semiconductor device can have a length or width less than or equal to 1000 microns, less than or equal to 750 microns, less than or equal to 500 microns, less than or equal to 250 microns, less than or equal to 100 microns, less than or equal to 50 microns, less than or equal to 20 microns, less than or equal to 10 microns, less than or equal to 5 microns, or less than or equal to 2 microns. In other embodiments, the semiconductor device is larger, for example having a size of up to 300 microns by 80 microns or 500 microns by 150 microns, or having a length or width of 500 microns, 750 microns, or 1,000 microns.
A method of making a semiconductor structure suitable for micro-transfer printing, according to embodiments of the present invention, includes providing a semiconductor substrate having an insulation layer on or over the semiconductor substrate and a base semiconductor layer on or over the insulation layer. The base semiconductor layer and the insulation layer are patterned to expose a portion of the semiconductor substrate through a corresponding etch via. Semiconductor material is disposed over the base semiconductor layer and in the etch via to form a second semiconductor layer so that the semiconductor material is in contact with the semiconductor substrate in the etch via and the etch via is at least partially filled with the semiconductor material. An isolation via is formed adjacent to the etch via through the semiconductor material and isolation material disposed in at least each isolation via. A semiconductor device is formed or constructed in or on the semiconductor material (including either or both of the first and second semiconductor layers) and is surrounded by isolation material in a direction parallel to the semiconductor substrate. The semiconductor material in the etch via is exposed and the semiconductor material in the etch via and an associated portion of the semiconductor substrate are etched in a common step with a common etchant to undercut the semiconductor device and form a tether attaching the semiconductor device to an anchor portion of the insulation layer or semiconductor substrate, thereby constructing a micro-transfer printable semiconductor device.
The step of processing the semiconductor material to form a semiconductor device can include disposing and patterning one or more dielectric or electrically conductive layers. The etch via can be exposed by patterning one or more of the dielectric or electrically conductive layers or the etch via is exposed by processing the semiconductor layer to form a semiconductor device.
The step of disposing isolation material in at least each isolation via can include a blanket deposition of isolation material that extends on or over the semiconductor material and that is then patterned to expose at least a portion of the semiconductor material.
In a further embodiment of the present invention, the semiconductor device is micro-transfer printed from the semiconductor substrate to a destination substrate.
The present invention provides structures and methods for efficiently forming robust releasable integrated circuits for micro-transfer printing in a cost-effective manner. Furthermore, when compared to other manufacturing methods, the present invention enables higher resolution tethers that are more easily made because the tether structures are constructed early in the process before the semiconductor devices are formed. The semiconductor devices are also more robust and less prone to process difficulties because the number of process steps performed to make a micro-transfer printable device after the device is constructed is consequently reduced. Furthermore, semiconductor devices made according to methods of the present invention can be arranged at a higher density on a wafer since multiple etching operations are unnecessary after the semiconductor devices are constructed, providing a more efficient and cost-effective use of expensive wafers.
In one aspect, the disclosed technology includes a method of making a semiconductor structure suitable for micro-transfer printing, including: providing a semiconductor substrate having an insulation layer on or over the semiconductor substrate and a base semiconductor layer on or over the insulation layer; patterning the base semiconductor layer and the insulation layer to expose a portion of the semiconductor substrate through a corresponding etch via; disposing semiconductor material over the base semiconductor layer and in the etch via so that the semiconductor material is in contact with the semiconductor substrate in the etch via and the etch via is at least partially filled with the semiconductor material; forming an isolation via over the insulation layer through the semiconductor material and the base semiconductor layer; disposing isolation material in at least each isolation via; forming a semiconductor device in or on the semiconductor material, the semiconductor device surrounded by isolation material in a direction parallel to the semiconductor substrate; exposing the semiconductor material in the etch via; and etching the semiconductor material in the etch via and an associated portion of the semiconductor substrate in a common step to undercut the semiconductor device and form one or more tethers attaching the semiconductor device to an anchor portion of the insulation layer or semiconductor substrate, thereby constructing a micro-transfer printable semiconductor device.
In certain embodiments, the step of forming the semiconductor device includes disposing and patterning one or more dielectric or electrically conductive layers.
In certain embodiments, the step of exposing the etch via is performed by patterning one or more of the dielectric or electrically conductive layers or wherein the step of exposing the etch via is performed by the step of processing the semiconductor material to form a semiconductor device.
In certain embodiments, the step of disposing isolation material in at least each isolation via includes a blanket deposition of isolation material that extends on or over the semiconductor material.
In certain embodiments, the method includes patterning the isolation material to expose at least a portion of the semiconductor material.
In certain embodiments, the method includes micro-transfer printing the semiconductor device from the semiconductor substrate to a destination substrate.
In certain embodiments, the method includes patterning the insulation layer in a pattern different from the base semiconductor layer to form a tether structure or an anchor structure.
In another aspect, the disclosed technology includes a semiconductor structure suitable for micro-transfer printing, including: a semiconductor substrate; a patterned insulation layer disposed on or over the semiconductor substrate, the insulation layer pattern defining one or more exposed etch vias in contact with the semiconductor substrate; and a semiconductor device disposed on the patterned insulation layer, at least a portion of the semiconductor device is surrounded by an isolation material in one or more isolation vias, and the one or more isolation vias are adjacent to the etch via.
In certain embodiments, the insulation layer and the isolation material are or include the same material or wherein the insulation layer and the isolation material are dielectric materials, are silicon oxide or silicon nitride.
In certain embodiments, the semiconductor substrate and the semiconductor material are or include the same material or wherein the semiconductor substrate and the semiconductor material are silicon, silicon <111>, or silicon <100>.
In certain embodiments, the semiconductor structure includes a plurality of isolation vias surrounding a corresponding plurality of semiconductor devices, each isolation via adjacent to an etch via.
In certain embodiments, a different etch via contacts the semiconductor substrate for etching each semiconductor device.
In certain embodiments, a common etch via contacts the semiconductor substrate for etching two or more semiconductor devices.
In certain embodiments, the etch via is at least partially filled with a semiconductor material that is etchable with a common etchant as the semiconductor substrate.
In certain embodiments, the etch via is empty and the semiconductor substrate is patterned to form a gap that separates at least a part of the semiconductor device from the semiconductor substrate and forms one or more tethers physically connecting the semiconductor device to an anchor portion of the semiconductor substrate or the patterned insulation layer.
In certain embodiments, the semiconductor device is an integrated circuit, is a light-emitting diode, includes a diode, or includes a transistor.
In certain embodiments, the semiconductor device has a length or width less than or equal to 250 microns, less than or equal to 100 microns, less than or equal to 50 microns, less than or equal to 20 microns, less than or equal to 10 microns, less than or equal to 5 microns, or less than or equal to 2 microns, and greater than zero microns.
In certain embodiments, the semiconductor device has a thickness or depth less than or equal to one micron, two microns, five microns, ten microns, twenty microns, or fifty microns and greater than zero microns.
In certain embodiments, the one or more tethers comprise a buried oxide layer in a silicon on insulator substrate.
The foregoing and other objects, aspects, features, and advantages of the present disclosure will become more apparent and better understood by referring to the following description taken in conjunction with the accompanying drawings, in which:
The features and advantages of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, in which like reference characters identify corresponding elements throughout. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The figures are not drawn to scale since the variation in size of various elements in the Figures is too great to permit depiction to scale.
Embodiments of the present invention provide structures and methods for efficiently forming robust releasable integrated circuits for micro-transfer printing in a cost-effective manner. The integrated circuits are surrounded by an isolation layer that provides environmental and electrical protection to the device. Methods of the present invention provide reduced processing steps to make such robust releasable or released integrated circuits suitable for micro-transfer printing using a stamp. Moreover, embodiments of the present invention provide structures and methods to enable micro-transfer printing from devices formed on alternative substrates or disposed on handle substrates that include materials different from materials in the integrated circuits.
Referring to
If an additional layer is located between the insulation layer 20 and the semiconductor substrate 10 and is etchable with common materials as the semiconductor substrate 10, the additional layer can be considered to be part of the semiconductor substrate 10. If the additional layer is etchable with common materials as the insulation layer 20, the additional layer can be considered to be part of the insulation layer 20. Similarly, if an additional layer is located between the insulation layer 20 and the base semiconductor layer 32 and is etchable with common materials as the insulation layer 20, the additional layer can be considered to be part of the insulation layer 20. If the additional layer is etchable with common materials as the base semiconductor layer 32, the additional layer can be considered to be part of the base semiconductor layer 32.
Referring next to
Referring to
Patterning the base semiconductor layer 32 and the insulation layer 20 and those layers described below can be done with conventional photolithographic methods and materials, for example by coating with a photoresist, pattern-wise exposing and developing the photoresist, etching the patterned photoresist, and stripping the photoresist to make a patterned layer. The insulation layer 20 and the base semiconductor layer 32 can be patterned in separate steps with different etchants and can be patterned into the same pattern (as shown in
In step 115 and as shown in
In step 120 and as shown in
In step 125 and as shown in
Referring to
The semiconductor device 34 can be formed in step 135 in crystalline silicon deposited on the patterned base semiconductor layer 32P to provide a high-performance semiconductor device 34, for example operable at fast clock rates and with low power. The portion of the patterned semiconductor material 30P that is processed to form the semiconductor device 34 is illustrated with cross hatching to indicate the completed semiconductor device 34. The patterned semiconductor material 30P portion of the semiconductor device 34 can be surrounded by patterned isolation material 22P in the isolation vias 36 in a direction parallel to the semiconductor substrate 10 that provides environmental and electrical protection to the patterned semiconductor material 30P portion of the semiconductor device 34. The dielectric and electrically conductive layer 40 can extend above the isolation material 22P so that at least a portion of the semiconductor device 24 is surrounded by the patterned isolation material 22P in one or more isolation vias 36. In combination with the patterned insulation layer 20P (which can be the same material as the isolation layer 22) and the dielectric and metal layers on the top of the patterned semiconductor material 30P, the semiconductor device 34 is protected from the environment and subsequent processing steps, such as etching steps.
As illustrated in
Referring to
As shown in
As shown in
Referring to
In various embodiments of the present invention, the insulation layer 20 and the isolation material 22 are or include the same material, such as dielectric materials, silicon oxide, or silicon nitride. In other embodiments, the semiconductor substrate 10 and the semiconductor material 30 are or include the same material, are silicon, silicon <111> or silicon <100>.
A plurality of isolation vias 36 can surround a corresponding plurality of semiconductor devices 34, with each isolation via 36 adjacent to an etch via 38. The etch vias 38 can be connected to form an extended area over the semiconductor substrate 10 in contact with patterned isolation material 22P forming walled islands surrounding semiconductor devices 34.
In embodiments of the present invention, the semiconductor device 34 is an integrated circuit, is a light-emitting diode, includes a diode, or includes a transistor. The semiconductor device 34 can have a length or width less than or equal to 200 microns, less than or equal to 100 microns, less than or equal to 50 microns, less than or equal to 20 microns, less than or equal to 10 microns, less than or equal to 5 microns, or less than or equal to 2 microns. The semiconductor device 34 can have a thickness or depth less than or equal to one micron, two microns, five microns, ten microns, twenty microns, or fifty microns.
As shown in
In an alternative method of the present invention and referring to
In step 125 the isolation layer 22 is deposited in the isolation vias 36 and over the patterned second semiconductor layer 30P (
Referring next to
In a further embodiment of the present invention and referring to
The micro-transfer printable semiconductor devices 34 made by methods of the present invention can include a variety of semiconductor structures, including a diode, a light-emitting diode (LED), a laser, a laser diode, a photo-diode, a photo-transistor, a transistor, an integrated circuit, a digital circuit, or a CMOS integrated circuit.
In embodiments of the present invention, the micro-transfer printable semiconductor devices 34 have a length greater than width, for example having an aspect ratio greater than or equal to 1.5, 2, 4, 8, 10, 20, or 50, and electrical contacts that are adjacent to the ends of the semiconductor devices 34 along the length of the micro-transfer printable semiconductor devices 34. The semiconductor devices 34 can have a variety of different sizes. For example, the semiconductor devices 34 can have a width from 0.5 to 2 μm, 2 to 5 μm, 5 to 10 μm, 10 to 20 μm, or 20 to 50 μm, a length from 2 to 5 μm, 5 to 10 μm, 10 to 20 μm, or 20 to 50 μm, 50 to 100 μm, or 100 to 250 μm, or a thickness from 0.5 to 1 μm, 1 to 2 μm, 2 to 5 μm, 4 to 10 μm, 10 to 20 μm, or 20 to 50 μm.
Methods of forming micro-transfer printable structures are described, for example, in the paper AMOLED Displays using Transfer-Printed Integrated Circuits (Journal of the Society for Information Display, 2011, DOI #10.1889/JSID19.4.335, 1071-0922/11/1904-0335, pages 335-341) and U.S. Pat. No. 8,889,485, referenced above. For a discussion of micro-transfer printing techniques see, U.S. Pat. Nos. 8,722,458, 7,622,367 and 8,506,867, each of which is hereby incorporated by reference in its entirety. Micro-transfer printing using compound micro-assembly structures and methods can also be used with the present invention, for example, as described in U.S. patent application Ser. No. 14/822,868, filed Aug. 10, 2015, entitled Compound Micro-Assembly Strategies and Devices, which is hereby incorporated by reference in its entirety. Additional details useful in understanding and performing aspects of the present invention are described in U.S. patent application Ser. No. 14/743,981, filed Jun. 18, 2015, entitled Micro Assembled LED Displays and Lighting Elements, which is hereby incorporated by reference in its entirety.
As is understood by those skilled in the art, the terms “over” and “under” are relative terms and can be interchanged in reference to different orientations of the layers, elements, and substrates included in the present invention. For example, a first layer on a second layer, in some implementations means a first layer directly on and in contact with a second layer. In other implementations, a first layer on a second layer includes a first layer and a second layer with another layer therebetween.
Having described certain implementations of embodiments, it will now become apparent to one of skill in the art that other implementations incorporating the concepts of the disclosure may be used. Therefore, the disclosure should not be limited to certain implementations, but rather should be limited only by the spirit and scope of the following claims.
Throughout the description, where apparatus and systems are described as having, including, or comprising specific components, or where processes and methods are described as having, including, or comprising specific steps, it is contemplated that, additionally, there are apparatus, and systems of the disclosed technology that consist essentially of, or consist of, the recited components, and that there are processes and methods according to the disclosed technology that consist essentially of, or consist of, the recited processing steps.
It should be understood that the order of steps or order for performing certain action is immaterial so long as the disclosed technology remains operable. Moreover, two or more steps or actions in some circumstances can be conducted simultaneously. The invention has been described in detail with particular reference to certain embodiments thereof, but it will be understood that variations and modifications can be effected within the spirit and scope of the invention.
This application claims priority to and benefit of U.S. Patent Application No. 62/436,038, filed Dec. 19, 2016, entitled Isolation Structure for Micro-Transfer Printable Devices, the content of which is hereby incorporated by reference in its entirety.
| Number | Name | Date | Kind |
|---|---|---|---|
| 3673471 | Klein | Jun 1972 | A |
| 5475224 | Koh | Dec 1995 | A |
| 5621555 | Park | Apr 1997 | A |
| 5815303 | Berlin | Sep 1998 | A |
| 5882532 | Field et al. | Mar 1999 | A |
| 6051472 | Abiko | Apr 2000 | A |
| 6142358 | Cohn et al. | Nov 2000 | A |
| 6278242 | Cok et al. | Aug 2001 | B1 |
| 6577367 | Kim | Jun 2003 | B2 |
| 6717560 | Cok et al. | Apr 2004 | B2 |
| 6756576 | McElroy et al. | Jun 2004 | B1 |
| 6933532 | Arnold et al. | Aug 2005 | B2 |
| 6969624 | Iwafuchi et al. | Nov 2005 | B2 |
| 7129457 | McElroy et al. | Oct 2006 | B2 |
| 7195733 | Rogers et al. | Mar 2007 | B2 |
| 7288753 | Cok | Oct 2007 | B2 |
| 7354801 | Sugiyama et al. | Apr 2008 | B2 |
| 7399693 | Sekiguchi et al. | Jul 2008 | B2 |
| 7521292 | Rogers et al. | Apr 2009 | B2 |
| 7557367 | Rogers et al. | Jul 2009 | B2 |
| 7586497 | Boroson et al. | Sep 2009 | B2 |
| 7622367 | Nuzzo et al. | Nov 2009 | B1 |
| 7662545 | Nuzzo et al. | Feb 2010 | B2 |
| 7704684 | Rogers et al. | Apr 2010 | B2 |
| 7799699 | Nuzzo et al. | Sep 2010 | B2 |
| 7816856 | Cok et al. | Oct 2010 | B2 |
| 7893612 | Cok | Feb 2011 | B2 |
| 7927976 | Menard | Apr 2011 | B2 |
| 7932123 | Rogers et al. | Apr 2011 | B2 |
| 7943491 | Nuzzo et al. | May 2011 | B2 |
| 7972875 | Rogers et al. | Jul 2011 | B2 |
| 7982296 | Nuzzo et al. | Jul 2011 | B2 |
| 7999454 | Winters et al. | Aug 2011 | B2 |
| 8029139 | Ellinger et al. | Oct 2011 | B2 |
| 8039847 | Nuzzo et al. | Oct 2011 | B2 |
| 8198621 | Rogers et al. | Jun 2012 | B2 |
| 8207547 | Lin | Jun 2012 | B2 |
| 8261660 | Menard | Sep 2012 | B2 |
| 8334545 | Levermore et al. | Dec 2012 | B2 |
| 8394706 | Nuzzo et al. | Mar 2013 | B2 |
| 8440546 | Nuzzo et al. | May 2013 | B2 |
| 8470701 | Rogers et al. | Jun 2013 | B2 |
| 8502192 | Kwak et al. | Aug 2013 | B2 |
| 8506867 | Menard | Aug 2013 | B2 |
| 8558243 | Bibl et al. | Oct 2013 | B2 |
| 8664699 | Nuzzo et al. | Mar 2014 | B2 |
| 8686447 | Tomoda et al. | Apr 2014 | B2 |
| 8722458 | Rogers et al. | May 2014 | B2 |
| 8754396 | Rogers et al. | Jun 2014 | B2 |
| 8766970 | Chien et al. | Jul 2014 | B2 |
| 8779484 | Shen | Jul 2014 | B2 |
| 8791474 | Bibl et al. | Jul 2014 | B1 |
| 8794501 | Bibl et al. | Aug 2014 | B2 |
| 8803857 | Cok | Aug 2014 | B2 |
| 8817369 | Daiku | Aug 2014 | B2 |
| 8835940 | Hu et al. | Sep 2014 | B2 |
| 8854294 | Sakariya | Oct 2014 | B2 |
| 8877648 | Bower et al. | Nov 2014 | B2 |
| 8889485 | Bower | Nov 2014 | B2 |
| 8895406 | Rogers et al. | Nov 2014 | B2 |
| 8934259 | Bower et al. | Jan 2015 | B2 |
| 8941215 | Hu et al. | Jan 2015 | B2 |
| 8987765 | Bibl et al. | Mar 2015 | B2 |
| 9105714 | Hu et al. | Aug 2015 | B2 |
| 9142468 | Bower et al. | Sep 2015 | B2 |
| 9153171 | Sakariya et al. | Oct 2015 | B2 |
| 9161448 | Menard et al. | Oct 2015 | B2 |
| 9166114 | Hu et al. | Oct 2015 | B2 |
| 9178123 | Sakariya et al. | Nov 2015 | B2 |
| 9240397 | Bibl et al. | Jan 2016 | B2 |
| 9358775 | Bower et al. | Jun 2016 | B2 |
| 9367094 | Bibl et al. | Jun 2016 | B2 |
| 9434150 | Bower et al. | Sep 2016 | B2 |
| 9478583 | Hu et al. | Oct 2016 | B2 |
| 9484504 | Bibl et al. | Nov 2016 | B2 |
| 9520537 | Bower et al. | Dec 2016 | B2 |
| 9555644 | Rogers et al. | Jan 2017 | B2 |
| 9583533 | Hu et al. | Feb 2017 | B2 |
| 9601356 | Bower | Mar 2017 | B2 |
| 9640715 | Bower et al. | May 2017 | B2 |
| 9716082 | Bower et al. | Jul 2017 | B2 |
| 9761754 | Bower et al. | Sep 2017 | B2 |
| 9765934 | Rogers et al. | Sep 2017 | B2 |
| 9865832 | Bibl et al. | Jan 2018 | B2 |
| 9929053 | Bower et al. | Mar 2018 | B2 |
| 9947584 | Bower et al. | Apr 2018 | B2 |
| 9991413 | Bower et al. | Jun 2018 | B2 |
| 20030062580 | Sato et al. | Apr 2003 | A1 |
| 20030141570 | Chen et al. | Jul 2003 | A1 |
| 20050189610 | Usuda | Sep 2005 | A1 |
| 20060063309 | Sugiyama et al. | Mar 2006 | A1 |
| 20060079010 | Hara et al. | Apr 2006 | A1 |
| 20060145177 | Hagimoto et al. | Jul 2006 | A1 |
| 20070032089 | Nuzzo et al. | Feb 2007 | A1 |
| 20070173034 | Tsurume et al. | Jul 2007 | A1 |
| 20070281556 | Elliott et al. | Dec 2007 | A1 |
| 20080079246 | Dix | Apr 2008 | A1 |
| 20080108171 | Rogers et al. | May 2008 | A1 |
| 20090202089 | Zhang et al. | Aug 2009 | A1 |
| 20100123268 | Menard | May 2010 | A1 |
| 20100248484 | Bower et al. | Sep 2010 | A1 |
| 20100306993 | Mayyas et al. | Dec 2010 | A1 |
| 20100317132 | Rogers et al. | Dec 2010 | A1 |
| 20100326518 | Juso et al. | Dec 2010 | A1 |
| 20120228669 | Bower et al. | Sep 2012 | A1 |
| 20120314388 | Bower et al. | Dec 2012 | A1 |
| 20130069275 | Menard et al. | Mar 2013 | A1 |
| 20130088416 | Smith et al. | Apr 2013 | A1 |
| 20130196474 | Meitl et al. | Aug 2013 | A1 |
| 20130207964 | Fleck et al. | Aug 2013 | A1 |
| 20130221355 | Bower et al. | Aug 2013 | A1 |
| 20130273695 | Menard et al. | Oct 2013 | A1 |
| 20140084240 | Hu et al. | Mar 2014 | A1 |
| 20140104243 | Sakariya et al. | Apr 2014 | A1 |
| 20140159043 | Sakariya et al. | Jun 2014 | A1 |
| 20140264763 | Meitl et al. | Sep 2014 | A1 |
| 20140267683 | Bibl et al. | Sep 2014 | A1 |
| 20140340900 | Bathurst et al. | Nov 2014 | A1 |
| 20140367633 | Bibl et al. | Dec 2014 | A1 |
| 20150028362 | Chan et al. | Jan 2015 | A1 |
| 20150135525 | Bower | May 2015 | A1 |
| 20150137153 | Bibl | May 2015 | A1 |
| 20150137187 | Aoki et al. | May 2015 | A1 |
| 20150371874 | Bower et al. | Dec 2015 | A1 |
| 20150372053 | Bower et al. | Dec 2015 | A1 |
| 20150372187 | Bower et al. | Dec 2015 | A1 |
| 20160020131 | Bower et al. | Jan 2016 | A1 |
| 20160086855 | Bower et al. | Mar 2016 | A1 |
| 20160093600 | Bower et al. | Mar 2016 | A1 |
| 20170047306 | Meitl et al. | Feb 2017 | A1 |
| 20170062235 | Kim | Mar 2017 | A1 |
| 20170154819 | Bower et al. | Jun 2017 | A1 |
| 20170173852 | Moore et al. | Jun 2017 | A1 |
| 20170256521 | Cok et al. | Sep 2017 | A1 |
| 20170338374 | Zou et al. | Nov 2017 | A1 |
| 20180096964 | Bonafede et al. | Apr 2018 | A1 |
| 20180166337 | Bower et al. | Jun 2018 | A1 |
| 20180204772 | Bower et al. | Jul 2018 | A1 |
| Number | Date | Country |
|---|---|---|
| 1531489 | May 2005 | EP |
| 2005108943 | Apr 2005 | JP |
| 2005259912 | Sep 2005 | JP |
| 2006108441 | Apr 2006 | JP |
| 2009105450 | May 2009 | JP |
| 2011066130 | Mar 2011 | JP |
| WO-2008036837 | Mar 2008 | WO |
| WO-2008103931 | Aug 2008 | WO |
| WO-2010111601 | Sep 2010 | WO |
| WO-2011123285 | Oct 2011 | WO |
| WO-2012018997 | Feb 2012 | WO |
| WO-2015193435 | Dec 2015 | WO |
| WO-2016120400 | Aug 2016 | WO |
| WO-2018114583 | Jun 2018 | WO |
| Entry |
|---|
| Cok, R. S. et al., AMOLED displays with transfer-printed integrated circuits, Journal of the SID, 19(4):335-341 (2011). |
| Roscher, H., VCSEL Arrays with Redundant Pixel Designs for 10Gbits/s 2-D Space-Parallel MMF Transmission, Annual Report, optoelectronics Department, (2005). |
| Yaniv et al., A 640×480 Pixel Computer Display Using Pin Diodes with Device Redundancy, 1988 International Display Research Conference, IEEE, CH-2678-1/88:152-154 (1988). |
| Lothian, J. R. et al., Wet and Dry Etching Characteristics of Al0.5In0.5P, Journal of Vacuum Science & Technology B, Microelectronics Processing and Phenomena USA, 10(3):1061-1065 (1992). |
| Yazawa, Y. et al., GaInP Single-Junction and GaInP/GaAs Two-Junction Thin-Film Solar Cell Structures by Epitaxial Lift-Off, Solar Energy Materials and Solar Cells, Elsevier Science Publishers, Amsterdam, 50(1-4):229-235 (1998). |
| International Search Report, PCT/EP2017/082795 (Isolation Structure for Micro-Transfer-Printable Devices, filed Dec. 14, 2017), issued by ISA/EPO, 4 pages, dated Jun. 7, 2018. |
| Written Opinion, PCT/EP2017/082795 (Isolation Structure for Micro-Transfer-Printable Devices, filed Dec. 14, 2017), issued by ISA/EPO, 7 pages, dated Jun. 7, 2018. |
| Bower, C. A. et al., Transfer Printing: An Approach for Massively Parallel Assembly of Microscale Devices, IEE, Electronic Components and Technology Conference, (2008). |
| Cok, R. S. et al., 60.3: AMOLED Displays Using Transfer-Printed Integrated Circuits, Society for Information Display, 10:902-904, (2010). |
| Cok, R. S. et al., Inorganic light-emitting diode displays using micro-transfer printing, Journal of the SID, 25(10):589-609, (2017). |
| Feng, X. et al., Competing Fracture in Kinetically Controlled Transfer Printing, Langmuir, 23(25):12555-12560, (2007). |
| Gent, A.N., Adhesion and Strength of Viscoelastic Solids. Is There a Relationship between Adhesion and Bulk Properties?, American Chemical Society, Langmuir, 12(19):4492-4496, (1996). |
| Kim, Dae-Hyeong et al., Optimized Structural Designs for Stretchable Silicon Integrated Circuits, Small, 5(24):2841-2847, (2009). |
| Kim, Dae-Hyeong et al., Stretchable and Foldable Silicon Integrated Circuits, Science, 320:507-511, (2008). |
| Kim, S. et al., Microstructured elastomeric surfaces with reversible adhesion and examples of their use in deterministic assembly by transfer printing, PNAS, 107(40):17095-17100, (2010). |
| Kim, T. et al., Kinetically controlled, adhesiveless transfer printing using microstructured stamps, Applied Physics Letters, 94(11):113502-1-113502-3, (2009). |
| Meitl, M. A. et al., Transfer printing by kinetic control of adhesion to an elastomeric stamp, Nature Material, 5:33-38, (2006). |
| Michel, B. et al., Printing meets lithography: Soft approaches to high-resolution patterning, J. Res. & Dev. 45(5):697-708, (2001). |
| Trindade, A. J. et al., Precision transfer printing of ultra-thin AlInGaN micron-size light-emitting diodes, Crown, 978-1-4577-1507-5/13:217-218 (2012). |
| Number | Date | Country | |
|---|---|---|---|
| 20180174910 A1 | Jun 2018 | US |
| Number | Date | Country | |
|---|---|---|---|
| 62436038 | Dec 2016 | US |
