Claims
- 1. A multi-layer lead frame for at least one semiconductor chip comprising:
- a lead frame body made of a metal strip and having an opening and a plurality of inner leads, said inner leads having respective tips which define at least a part of said opening;
- a metal plane which is independent from said lead frame body, has top and bottom planar surfaces and is electrically connected to one of said inner leads at a connecting point, said metal plane having wire bonding areas for connection to the semiconductor chip and inner holes formed int he metal plane and located beside said wire bonding areas within said opening; and
- an insulative adhesive layer adhering said top planar surface to said inner leads.
- 2. A multi-layer lead frame as set forth in claim 1, wherein said opening is covered by said metal plane.
- 3. A multi-layer lead frame according to claim 1, further comprising bonding wires bonded to said metal plane at said wire bonding areas and connectable to provide one of power supply and ground connections for the semiconductor device.
- 4. A multi-layer lead frame according to claim 1, wherein said metal plane has outer holes formed therein along an outer periphery of said metal plane.
- 5. A multi-layer lead frame according to claim 4, wherein said outer holes comprise round holes
- 6. A multi-layer lead frame according to claim 1, further comprising molded resin filled within each inner hole and encapsulating the semiconductor device.
- 7. A multi-layer lead frame according to claim 1, wherein said inner holes comprise slit-like through holes.
- 8. A multi-layer lead frame according to claim 1, wherein said inner holes comprise L-shaped through holes.
- 9. A multi-layer lead frame according to claim 1, wherein said inner holes comprise one of U, V and C-shaped through holes.
- 10. A multi-layer lead frame for at least one semiconductor chip comprising:
- a lead frame body made of a metal strip and having an opening and a plurality of inner leads, said inner leads having respective tips which define at least a part of said opening;
- a metal plane which is independent from said lead frame body and has top and bottom planar surfaces, said metal plane having wire bonding areas and inner holes formed in the metal plane and located beside said wire bonding areas within said opening; and
- an insulative adhesive layer adhering said top planar surface to said inner leads.
- 11. A multi-layer lead frame as set forth in claim 10, wherein said opening is covered by said metal plane.
- 12. A multi-layer lead frame according to claim 10, further comprising bonding wires bonded to said metal plane at said wire bonding areas and connectable to provide one of power supply and ground connections for the semiconductor device.
- 13. A multi-layer lead frame according to claim 10, wherein said metal plane has outer holes formed therein along an outer periphery of said metal plane.
- 14. A multi-layer lead frame according to claim 13, wherein said outer holes comprise round holes.
- 15. A multi-layer lead frame according to claim 10, further comprising molded resin filled within each inner hole and encapsulating the semiconductor chip.
- 16. A multi-layer lead frame according to claim 10, wherein said inner holes comprise through holes.
- 17. A multi-layer lead frame according to claim 10, wherein said inner holes comprise slit-like through holes.
- 18. A multi-layer lead frame according to claim 10, wherein said inner holes comprise L-shaped through holes.
- 19. A multi-layer lead frame according to claim 10, wherein said inner holes comprise one of U, V and C-shaped through holes.
- 20. A semiconductor device comprising:
- (a) a multi-layer lead frame for a semiconductor device comprising:
- a lead frame body made of a metal strip and having an opening and a plurality of inner leads, said inner leads having respective tips which define at least a part of said opening;
- a metal plane which is independent from said lead frame body and has top and bottom planar surfaces, said metal plane having a stage portion, wire bonding areas at a peripheral portion of said stage portion within said opening and through holes formed in said metal plane and located beside said wire bonding areas; and
- an insulative adhesive layer adhering said top planar surface to said inner leads;
- (b) a semiconductor chip mounted on said stage portion;
- (c) bonding-wires electrically connecting said semiconductor chip to said wire bonding areas of said metal plane; and
- (d) a resin hermetically and integrally molding at least a part of said multi-layer lead frame, said semiconductor chip, and said bonding-wires in such a manner that said through holes are also filled with said resin.
Priority Claims (2)
Number |
Date |
Country |
Kind |
1-268649 |
Oct 1989 |
JPX |
|
02-26786 |
Feb 1990 |
JPX |
|
Parent Case Info
This application is a continuation of application Ser. No. 07/803,724, filed Dec. 9, 1991, now U.S. Pat. No. 5,237,202.
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4796078 |
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4891687 |
Mallik et al. |
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Continuations (1)
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Number |
Date |
Country |
Parent |
803724 |
Dec 1991 |
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