Patent Application
20060151862
The present invention relates to lead-frame-based semiconductor packages and lead frames thereof, and more particularly, to a lead-frame-based semiconductor package having flash runners, and a lead frame of the semiconductor package.
A conventional semiconductor package using a lead frame as a chip carrier, such as a quad flat package (QFP) or quad flat non-leaded (QFN) package, is fabricated by the steps of mounting a semiconductor chip on the lead frame that comprises a die pad and a plurality of leads; electrically connecting bond pads on a surface of the chip to the corresponding leads via a plurality of gold wires; and encapsulating the chip and the gold wires via an encapsulant, such that the lead-frame-based semiconductor package is formed. Further, a surface of the die pad can be exposed from the encapsulant so as to accelerate dissipation of heat from the chip via the die pad.
However, there is a flash issue for fabricating the encapsulant of the foregoing conventional semiconductor package occurred as shown in
U.S. Pat. No. 6,204,553 has disclosed a solution to the flash problem. As shown in
However, the above conventional method still has a drawback that the flashes 65 can only flow into the nearby grooves 63 but not be evenly distributed, that is, the grooves 63 do not provide a flow guiding and diversion function. This thereby causes uneven distribution of the flashes 65 in the grooves 63 as shown in
Therefore, the problem to be solved here is to provide a lead-frame-based semiconductor package, which can completely solve the problem of flashes on a lower surface of a die pad, thereby keeping the heat dissipating efficiency and saving cost of an unnecessary deflashing process.
In light of the above drawbacks in the prior art, an objective of the present invention is to provide a lead-frame-based semiconductor package and a lead frame thereof, so as to prevent flashes from occurrence.
Another objective of the present invention is to provide a lead-frame-based semiconductor package and a lead frame thereof, which can simplify the fabrication processes.
Still another objective of the present invention is to provide a lead-frame-based semiconductor package and a lead frame thereof, which can reduce the fabrication cost.
A further objective of the present invention is to provide a lead-frame-based semiconductor package and a lead frame thereof, so as to enhance adhesion between an encapsulant and the lead frame.
In accordance with the above and other objectives, the present invention proposes a lead-frame-based semiconductor package, comprising: a lead frame having at least one die pad and a plurality of leads around the die pad, wherein a plurality of grooves and runners are formed on a lower surface of the die pad, and each of the grooves is connected to an edge of the die pad by at least one of the runners; at least one chip mounted on an upper surface of the die pad, and electrically connected to the plurality of leads; and an encapsulant for encapsulating the chip, with the grooves and runners being exposed from the encapsulant.
The present invention also proposes a lead frame, comprising: at least one die pad formed with a plurality of grooves and runners on a surface thereof, wherein each of the grooves is connected to an edge of the die pad by at least one of the runners; and a plurality of leads formed around the die pad.
The grooves are interconnected to encompass and form an area or a shape corresponding to the shape of the die pad. Each of the grooves is connected to the edge of the die pad by at least one of the runners. In other words, each edge of a bottom surface of the die pad is provided with at least one of the runners that can be connected to the grooves.
Moreover, the grooves have the same depth and width as the runners, and the depth of the runners is half of the thickness of the die pad. Generally, the depth of the runners can be made as 0.05 mm to 0.15 mm, preferably 0.1 mm; and the width of the runners can be 0.03 mm to 0.2 mm, preferably 0.1 mm.
Therefore, by the foregoing arrangement, when a conventional molding process is performed, if excess flashes occur, the runners can guide the flow of flashes and the grooves can accommodate the flashes, such that the flashes may firstly flow along each edge of the die pad into the runners and then fill the grooves. Moreover, since the plurality of runners and grooves are interconnected, the flashes received in the runners and grooves can be evenly distributed without leaking out of the grooves and flashing to the surface of the die pad, such that the flash problem in the prior art can be completely solved by this flash guiding and diversion mechanism.
The present invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein:
As shown in
The semiconductor package further comprises a chip 20 mounted on a top surface of the die pad 11, wherein the chip 20 is electrically connected to the plurality of leads 12 by a plurality of bonding wires 21 such as gold wires. Then, an encapsulant 25 can be fabricated by a molding process to encapsulate the chip 20, the bonding wires 21 and a portion of the leads 12, wherein bottom surfaces of the leads 12 and the bottom surface 110 of the die pad 11 are exposed from the encapsulant 25, such that the plurality of grooves 15 and runners 16 are all exposed from the encapsulant 25.
Therefore, by the foregoing arrangement, when a conventional molding process is performed, if flashes 30 occur, the runners 16 can guide the flow of flashes 30 and the grooves 15 can accommodate the flashes 30, such that the flashes 30 may firstly flow along each edge of the die pad 11 into the runners 16 and then fill the grooves 15. Moreover, since the plurality of runners 16 and grooves 15 are interconnected, the flashes 30 received in the runners 16 and grooves 15 can be evenly distributed without leaking out of the grooves 15 and flashing to the surface of the die pad 11, such that the flash problem in the prior art can be completely solved by this flash guiding and diversion mechanism.
The grooves 15 have the same depth and width as the runners 16, and the depth of the runners 16 is half of the thickness of the die pad 11. Generally, the depth of the runners 16 can be made as 0.05 mm to 0.15 mm, preferably 0.1 mm; and the width of the runners 16 can be 0.03 mm to 0.2 mm, preferably 0.1 mm.
Besides the foregoing embodiment, the grooves 15 and the runners 16 can have other modifications in quantity and location. For example, as shown in
Accordingly, the lead frame 10 proposed in the present invention comprises at least one die pad 11 formed with a plurality of grooves 15 and runners 16 on a surface thereof, wherein each of the grooves 15 is connected to an edge of the die pad 11 by at least one of the runners 16; and a plurality of leads 12 formed around the die pad 11.
Therefore, the lead-frame-based semiconductor package and the lead frame thereof in the present invention utilize the runners to guide the flow of flashes and thereby improve a flash preventing effect, such that the fabrication cost and processes can be reduced, and the problems encountered in the prior art can be effectively solved.
The present invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
| Number | Date | Country | Kind |
|---|---|---|---|
| 094100697 | Jan 2005 | TW | national |
