Patent Application
20240421246
The present invention relates to light emitting devices, and particularly to light emitting diodes containing a dielectric masking layer containing pinholes and methods of fabricating the same.
Light emitting devices such as light emitting diodes (LEDs) are used in electronic displays, such as backlights in liquid crystal displays located in laptops or televisions. Light emitting devices include light emitting diodes and various other types of electronic devices configured to emit light.
According to one embodiment, a method of forming a light emitting diode (LED) includes forming a buffer layer over a support substrate, forming a dielectric masking layer having a thickness of 20 nm or less and containing pinholes having a width of 200 nm or less on the buffer layer, forming a n-doped semiconductor material layer on the dielectric masking layer such that the n-doped semiconductor material of the n-doped semiconductor layer fills the pinholes and contacts the buffer layer, forming an active region over the n-doped semiconductor material layer, and forming a p-doped semiconductor material layer over the active region.
According to another embodiment, a light emitting diode (LED) includes a semiconductor buffer layer, a n-doped semiconductor material layer, a dielectric masking layer having a thickness of 20 nm or less and containing pinholes having a width of 200 nm or less filled with the n-doped semiconductor material of the n-doped semiconductor layer located between the semiconductor buffer layer and the n-doped semiconductor material layer, a p-doped semiconductor material layer, and an active region disposed between the n-doped semiconductor layer and the p-doped semiconductor layer.
According to another embodiment, a structure includes a first material layer, a second material layer; and a dielectric masking layer having a thickness of 20 nm or less and containing pinholes having a width of 200 nm or less filled with the second material of second material layer located between the first material layer and the second material layer.
According to another embodiment, a method includes forming a first material layer, forming a dielectric masking layer having a thickness of 20 nm or less and containing pinholes having a width of 200 nm or less on the first material layer, and forming a second material layer on the dielectric masking layer such that the second material of the second material layer fills the pinholes and contacts the first material layer.
A display device, such as a direct view display device, can be formed from an ordered array of pixels bonded to a backplane. Each pixel can include a set of subpixels that emit light at a respective peak wavelength. For example, a pixel can include a red subpixel, a green subpixel, and a blue subpixel. Each subpixel can include one or more light emitting diodes that emit light of a particular wavelength. Each pixel is driven by a backplane circuit such that any combination of colors within a color gamut may be shown on the display for each pixel. The display panel can be formed by a process in which LED subpixels are soldered to, or otherwise electrically attached to, a bond pad located on the backplane. The bond pad is electrically driven by the backplane circuit and other driving electronics.
The single crystalline buffer semiconductor layer 24 includes a single crystalline compound semiconductor material such as a III-V compound semiconductor material, for example a Group III-nitride compound semiconductor material. The deposition process for forming the single crystalline buffer semiconductor layer 24 can employ any of metalorganic vapor phase epitaxy (MOVPE), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), metal-organic molecular beam epitaxy (MOMBE), and atomic layer deposition (ALD). The single crystalline buffer semiconductor layer 24 can have a constant or a graded composition such that the composition of the single crystalline buffer semiconductor layer 24 at the interface with the support substrate 22 provides a substantial lattice matching with the two-dimensional lattice structure of the top surface of the support substrate 22. The composition of the single crystalline buffer semiconductor layer 24 can be gradually changed during the deposition process. If the support substrate 22 includes patterned sapphire, then the bottom surface of the single crystalline buffer semiconductor layer 24 may be a patterned (i.e., rough) surface.
The materials that can be employed for a bottom portion of the single crystalline buffer semiconductor layer 24 can be, for example, Ga1-w-xInwAlxN in which w and x range between zero and less than one, and can be zero (i.e., GaN) and are selected to match the lattice constant of the top surface of the support substrate 22. Optionally, As and/or P may also be included in the material for the bottom portion of the buffer layer, in which case the bottom portion of the single crystalline buffer semiconductor layer 24 can include Ga1-w-xInwAlxN1-x-1AsyPz in which y and z between zero and less than one, that matches the lattice constant of the top surface of the support substrate 22. The materials that can be employed for an top portion of the single crystalline buffer semiconductor layer 24 include, but are not limited to, III-V compound materials, including III-nitride materials, such as gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride, and gallium indium nitride, as well as other III-V materials, such as gallium phosphide (GaP), gallium arsenide (GaAs), gallium antimonide (GaSb), Indium phosphide (InP), indium arsenide (InAs), and indium antimonide (InSb). The composition of the single crystalline buffer semiconductor layer 24 can gradually change between the bottom portion of the single crystalline buffer semiconductor layer 24 and the top portion of single crystalline buffer semiconductor layer 24 such that dislocations caused by a gradual lattice parameter change along the growth direction (vertical direction) does not propagate to the top surface of the single crystalline buffer semiconductor layer 24. In one embodiment, a thin bottom portion of the single crystalline buffer semiconductor layer 24 less than 1 micron in thickness may be undoped or doped at a low concentration of silicon.
A high quality single crystalline surface with low defect density can be provided at the top surface of the single crystalline buffer semiconductor layer 24. Optionally, the top surface of the single crystalline buffer semiconductor layer 24 may be planarized to provide a planar top surface, for example, by chemical mechanical planarization. A suitable surface clean process can be performed after the planarization process to remove contaminants from the top surface of the single crystalline buffer semiconductor layer 24. The average thickness of the single crystalline buffer semiconductor layer 24 may be in a range from 2 microns to 10 microns, although lesser and greater thicknesses can also be employed.
An n-doped compound semiconductor substrate layer 26 is subsequently formed directly on the top surface of the single crystalline buffer semiconductor layer 24. The n-doped compound semiconductor substrate layer 26 can be formed as a continuous material layer having a uniform thickness over the entire top surface of the single crystalline buffer semiconductor layer 24. The n-doped compound semiconductor substrate layer 26 includes an n-doped compound semiconductor material. The n-doped compound semiconductor substrate layer 26 can be lattice matched with the single crystalline compound semiconductor material of the top portion of the single crystalline buffer semiconductor layer 24. The n-doped compound semiconductor substrate layer 26 may, or may not, include the same compound semiconductor material as the top portion of the single crystalline buffer semiconductor layer 24. In one embodiment, the n-doped compound semiconductor substrate layer 26 can include an n-doped direct band gap compound semiconductor material. In one embodiment, the n-doped compound semiconductor substrate layer 26 can include n-doped gallium nitride (GaN), indium gallium nitride (InGaN) or other III-V semiconductor materials, such as gallium phosphide or its ternary or quarternary compounds. The deposition process for forming the n-doped compound semiconductor substrate layer 26 can employ any of metalorganic vapor phase epitaxy (MOVPE), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), metal-organic molecular beam epitaxy (MOMBE), and atomic layer deposition (ALD). The thickness of the n-doped compound semiconductor substrate layer 26 can be in a range from 300 nm to 2 microns, although lesser and greater thicknesses can also be employed. The support substrate 22, the single crystalline buffer semiconductor layer 24, and the n-doped compound semiconductor substrate layer 26 collectively comprise a substrate 20.
In some embodiments (such as the embodiments illustrated in
A photoresist layer (not shown) can be applied over the top surface of the dielectric material layer, and can be lithographically patterned to form openings therethrough by lithographic exposure and development. In one embodiment, the openings in the photoresist layer can be formed as a two-dimensional periodic array. The size and shape of each opening can be selected to optimize the shape and size of semiconductor structures to be subsequently formed by a selective deposition process (such as a selective epitaxy process). The pattern of the openings in the photoresist layer can be transferred through the dielectric material layer to form the patterned growth mask layer 42. The photoresist layer can be subsequently removed, for example, by ashing. Alternatively, the growth mask layer can be patterned using electron beam lithography or nano-imprint lithography followed by etching. The patterned growth mask layer 42 includes openings, which may, or may not, be arranged as a two-dimensional periodic array. The shape of each opening may be circular, elliptical, or polygonal (such as hexagonal). A portion of the top surface of the n-doped compound semiconductor substrate layer 26 is physically exposed underneath each opening through the patterned growth mask layer 42.
The single crystalline buffer semiconductor layer 24, the n-doped compound semiconductor substrate layer 26, and additional structures to be formed thereupon will be subsequently patterned to define an array of subpixels, which is an array of light emitting diodes 10. Thus, each subsequently patterned area of the single crystalline buffer semiconductor layer 24 and the n-doped compound semiconductor substrate layer 26 will correspond to the area of a respective light emitting diode 10. For example, the array of light emitting diodes 10 may be formed as a rectangular array or a hexagonal array, and each light emitting diode 10 may be formed with a maximum lateral dimension (such as the diagonal of a rectangular shape or the diameter of a circumscribing circle of a hexagonal shape) in a range from 1 micron to 60 microns, such as from 2 micron to 30 microns. For example, the maximum lateral dimension of each opening through the patterned growth mask layer 42 may be in a range from 50 nm to 50 microns (such as from 200 nm to 10 microns), although lesser and greater dimensions may also be employed.
In an alternative embodiment, the single crystalline buffer semiconductor layer 24 and the n-doped compound semiconductor substrate layer 26 are patterned by a combination of a lithographic process and an anisotropic etch prior to formation of the additional structures (e.g., epitaxial growth of subsequent semiconductor materials) on the n-doped compound semiconductor substrate layer 26. For example, a photoresist layer can be applied over the n-doped compound semiconductor substrate layer 26, and is lithographically patterned to cover each discrete area of light emitting diodes 10. For example, two sets of line trenches extending along orthogonal horizontal directions can be formed through the n-doped compound semiconductor substrate layer 26 and the single crystalline buffer semiconductor layer 24 to form a rectangular array of patterned portions of the n-doped compound semiconductor substrate layer 26 and the single crystalline buffer semiconductor layer 24. The photoresist layer can be subsequently removed.
In configurations such as the configurations of
In some other embodiments (such as the embodiments illustrated in
N-doped compound semiconductor regions 32 can be grown through, and over, the growth mask layer 42 by a selective compound semiconductor deposition process, which can be a selective epitaxy process. The shapes and sizes of the n-doped compound semiconductor regions 32 can be determined based on the shapes and dimensions of the openings through the growth mask layer 42 and by the process conditions of the selective compound semiconductor deposition process. The n-doped compound semiconductor regions 32 can be formed with various crystallographic facets located within a respective crystallographic plane. As used herein, a “p-plane” means a “pyramid plane,” which can by any of the {1
In some embodiments (such as the embodiments illustrated in
In some embodiments (such as the embodiments illustrated in
In some embodiments (such as the embodiments illustrated in
Selective epitaxy processes that may be employed to form the n-doped compound semiconductor regions 32 are described, for example, in U.S. Pat. No. 9,444,007 to Kryliouk et al., U.S. Pat. No. 9,419,183 to Lowgren et al., U.S. Pat. No. 9,281,442 to Romano et al., and U.S. Pat. No. 8,669,574 to Konsek et al., each of which is assigned to Glo AB and is incorporated herein by reference in their entirety.
In some embodiments (such as the embodiments illustrated in
Subsequently, an active region 34 including an optically active compound semiconductor layer stack configured to emit light is formed on each n-doped compound semiconductor region 32. Each active region 34 includes at least one semiconductor material that emits light upon application of a suitable electrical bias. For example, each active region 34 can include a single or a multi-quantum well (MQW) structure that emits light upon application of an electrical bias thereacross. For example, the quantum well(s) may comprise indium gallium nitride well(s) located between gallium nitride or aluminum gallium nitride barrier layers. Alternatively, the active regions 34 can include any other suitable semiconductor layers (e.g., such as gallium phosphide or its ternary or quarternary compounds) or stack of layers for light emitting diode applications provided that it can be grown on the surfaces of the n-doped compound semiconductor regions 32. The set of all layers within an active region 34 is herein referred to as an active layer.
In one embodiment, each of the plurality of active regions 34 includes a respective optically active compound semiconductor layer stack configured to emit light. In a non-limiting illustrative example, the active region 34 can include a layer stack including, from bottom to top, a silicon-doped GaN layer having a thickness of 30 nm to 70 nm, such as about 50 nm to about 60 nm, a GaN layer having a thickness of 2 nm to 10 nm, such as about 5 nm to 7 nm, an InGaN layer having a thickness of 1 nm to 5 nm, such as about 3 nm to 4 nm, and a GaN barrier layer having a thickness of 10 nm to 30 nm, such as about 15 nm to 20 nm. Optionally, an AlGaN cap layer may be formed on the InGaN layer for red LEDs. The sequence of layers, composition of each layer, and the thickness of each layer within each active region 34 can be optimized to increase emission intensity and to provide the target peak emission wavelength. The active regions 34 may emit any color light, such as blue, green or red light depending on the composition of the semiconductor material therein and the strain that is applied to the semiconductor material.
A selective epitaxy process can be employed to grow the active regions 34. The process parameters of the selective epitaxy process can be selected such that the active regions 34 are grown as conformal structures having a same thickness throughout. In another embodiment, the active regions 34 can be grown as a pseudo-conformal structure in which the horizontal portions have the same thickness (such as a first thickness t1) throughout, and faceted portions have a thickness (such as a second thickness t2) that is less than the thickness of the horizontal portions. In one embodiment, each of the plurality of active regions 34 can include a top planar portion having the first thickness t1 and sidewall portions overlying tapered planar sidewalls of a respective one of the n-doped compound semiconductor regions 32 and having the second thickness t2. In one embodiment, the ratio of the first thickness t1 to the second thickness t2 can be in a range from 2 to 50, although lesser and greater ratios can also be employed. Methods for growing a layer stack for active regions 34 on nanowires are described, for example, in U.S. Pat. No. 9,444,007 to Kryliouk et al., U.S. Pat. No. 9,419,183 to Lowgren et al., U.S. Pat. No. 9,281,442 to Romano et al., and U.S. Pat. No. 8,669,574 to Konsek et al. An active region 34 contacts, surrounds, and overlies an underlying n-doped compound semiconductor region 32. In one embodiment shown in
A p-doped semiconductor material layer 36 is formed on the planar top surfaces and faceted outer surfaces of the active regions 34. The p-doped semiconductor material layer 36 includes a doped semiconductor material having a doping of a second conductivity type, which is the opposite of the first conductivity type. For example, if the first conductivity type is n-type, then the second conductivity type is p-type. If the first conductivity type is p-type, then the second conductivity type is n-type.
The p-doped semiconductor material layer 36 can include a compound semiconductor material. The compound semiconductor material of the p-doped semiconductor material layer 36 can be any suitable semiconductor material, such as p-type III-nitride compound semiconductor material, e.g., gallium nitride and/or aluminum gallium nitride. In one embodiment, the n-doped compound semiconductor regions 32 can include n-doped GaN or InGaN, and the p-doped semiconductor material layer 36 can include p-doped AlGaN and/or GaN. Alternatively, regions 32 and/or layer 36 can include other semiconductor materials, such as such as gallium phosphide or its ternary or quarternary compounds.
The p-doped semiconductor material layer 36 can be formed by selective deposition of the doped semiconductor material on the outer surfaces of the active regions 34. For example, a selective epitaxy process can be employed. During the selective deposition process (which can be a selective epitaxy process), discrete semiconductor material portions grow from the outer surfaces of each of the active regions until the discrete semiconductor material portions merge to form the p-doped semiconductor material layer 36 as a continuous semiconductor material layer within the area of each light emitting diode 10. In case portions of the top surface of the growth mask layer 42 are not covered by the n-doped compound semiconductor regions 32 or the active regions 34, the bottom surface of the p-doped semiconductor material layer 36 may contact such portions of the top surface of the growth mask layer 42.
An anode contact 50 can be formed on the top surface of the p-doped semiconductor material layer 36.
The transparent conductive oxide layer 53 can be deposited over the p-doped semiconductor material layer 36. The transparent conductive oxide layer 53 can be deposited as a continuous material layer that extends across the entire area of the p-doped semiconductor material layer 36. The thickness of the transparent conductive oxide layer 53 can be in a range from 50 nm to 600 nm, such as from 10 nm to 300 nm, although lesser and greater thicknesses can also be employed. The transparent conductive oxide layer 53 includes a transparent conductive oxide material such as a material selected from doped zinc oxide, indium tin oxide, cadmium tin oxide (Cd2SnO4), zinc stannate (Zn2SnO4), and doped titanium dioxide (TiO2). Exemplary doped zinc oxide materials include boron-doped zinc oxide, fluorine doped zinc oxide, gallium doped zinc oxide, and aluminum doped zinc oxide. In one embodiment, the anode contact 50 cam be optically transparent.
Alternatively, gold may be deposited first, and nickel oxide may be formed subsequently. Yet alternately, gold and nickel may be deposited as a stack of at least two layers, and oxidation and interdiffusion may be induced by thermal oxidation of nickel into nickel oxide to form the NiO:Au composite layer 55. The thickness of the NiO:Au composite layer 55 can be in a range from 2 nm to 200 nm, such as from 5 nm to 100 nm, although lesser and greater thicknesses can also be employed.
An optional dielectric material layer 60 can be subsequently formed on the physically exposed surfaces of the exemplary structure in the embodiments of
The dielectric material layer 60 can be subsequently patterned to provide an opening above each anode contact 50. For example, a photoresist layer can be applied over the exemplary structure, and can be lithographically patterned to form openings within each periphery of the anode contacts 50. An anisotropic etch process or an isotropic etch process can be performed employing the patterned photoresist layer as an etch mask layer. For example, if the dielectric material layer 60 includes silicon oxide, an isotropic etch process employing dilute hydrofluoric acid can be employed to form openings through the dielectric material layer 60. The area of each opening through the dielectric material layer 60 may be in a range from 10% to 90% of the area of an underlying anode contact 50. The sidewalls of the dielectric material layer 60 around the openings may be tapered or may be vertical. The photoresist layer can be subsequently removed, for example, by ashing.
Referring to
As shown in
Referring to
Around each area of a light emitting diode 10, a combination of the first metal layer 71 and the second metal layer 72 is deposited within a center region of the light emitting diode 10, while only the first metal layer 71 is deposited in a peripheral region, which is located outside a periphery of the center region. The center region may be entirely within the area defined by the periphery of an anode contact 50. The peripheral region can have an inner periphery that coincides with a periphery of the center region. Specifically, the inner periphery of the peripheral region can coincide with the sidewalls of the patterned lift-off mask 77.
The combination of the first metal layer 71 and the second metal layer 72 constitutes a single metal layer having two different thicknesses. Specifically, the combination of the first metal layer 71 and the second metal layer 72 constitutes a dual thickness metal adhesion layer (71, 72) having a first thickness at a peripheral region (i.e., the region in which only the first metal layer 71 is deposited) and having a second thickness that is greater than the first thickness at a center region (i.e., the region in which both the first metal layer 71 and the second metal layer 72 are deposited). In one embodiment, the first thickness is in a range from 0.3 nm to 10 nm, and the second thickness in a range from 0.6 nm to 50 nm. In another embodiment, the first thickness is in a range from 0.6 nm to 4 nm, and the second thickness in a range from 1 nm to 10 nm.
Aluminum can be deposited by an anisotropic deposition method (such as sputtering or vacuum evaporation). An aluminum layer 74 can be formed directly on the dual thickness metal adhesion layer (71, 72) over the anode contact 50, and an additional aluminum layer 74′ can be formed on the additional second metal layer 72′ over the patterned lift-off mask 77. The aluminum layer 74 can consist essentially of aluminum. The aluminum layer 74 provides malleability during subsequent laser processing process, such as laser ablation processes and laser solder processes, so that active regions 34 of the light emitting devices 10 are protected from mechanical shock and/or structural damage. A metal having a higher malleability, such as gold or silver, may also be used in lieu of aluminum. Horizontal portions of the aluminum layer 74 can have a thickness in a range from 500 nm to 3,000 nm, such as from 800 nm to 2,000 nm, over the dual thickness metal adhesion layer (71, 72).
A metallic adhesion material can be deposited over the aluminum layer 74 by an anisotropic deposition process such as physical vapor deposition or vacuum evaporation. The metallic adhesion material can include an elemental metal such as nickel or platinum. A metallic adhesion layer 76 is formed on the top surface of the aluminum layer 74 overlying the anode contact 50, and an additional metallic adhesion layer 76′ is formed on the additional aluminum layer 74′ over the patterned lift-off mask 77. Horizontal portions of the metallic adhesion layer 76 can have a uniform thickness, which can be in a range from 1 nm to 300 nm, such as from 10 nm to 100 nm, although lesser and greater thicknesses can also be employed. The stack of the dual thickness metal adhesion layer (71, 72), the aluminum layer 74, and the metallic adhesion layer 76 constitutes a reflector 70, which can function as a reflector and a portion of an anode of the light emitting device 10. The stack of the additional metallic adhesion layer 76′, the additional aluminum layer 74′, and the additional second metal layer 72′ constitute an additional reflector 70′.
Referring to
A photoresist layer (not shown) can be applied over the exemplary structure and lithographically patterned to cover each area of the light emitting diodes 10. The patterned areas of the photoresist layer can be arranged as a two-dimensional array with channels (corresponding to areas from which the material of the photoresist layer is removed during development) laterally surrounding each area of the light emitting diodes 10. An anisotropic etch process is performed to pattern the anode contact 50, the p-doped semiconductor material layer 36, the active regions 34, the n-doped compound semiconductor regions 32, the growth mask layer 42 (if present), the n-doped compound semiconductor substrate layer 26, and the single crystalline buffer semiconductor layer 24. The anisotropic etch process can stop on the support substrate 22.
In the embodiments shown in
Alternatively, in the embodiments shown in
Each etched mesa comprising a contiguous set of patterned portions of the reflector 70, anode contact 50, the p-doped semiconductor material layer 36, the active regions 34, the n-doped compound semiconductor regions 32, the growth mask layer 42 (if present), the n-doped compound semiconductor substrate layer 26, and the single crystalline buffer semiconductor layer 24 constitute components of a respective light emitting diode 10. An optional dielectric layer, such as silicon oxide or silicon nitride, can be deposited over the sidewalls of the etched mesa while exposing the top surface of the reflector 70. In case the n-doped compound semiconductor substrate layer 26 and the single crystalline buffer semiconductor layer 24 are patterned as discrete material portions prior to formation of the n-doped compound semiconductor regions 32 (as in the case of the alternative configurations of
As shown in
A second metallic bonding pad metal can be anisotropically deposited to form a second metallic bonding pad layer 84 and a second metallic material layer 84′. The second metallic bonding pad layer 84 can be deposited directly on the first metallic bonding pad layer 82 overlying the anode contact 50 and the reflector 70, and the second metallic material layer 84′ can be deposited on a top surface of the first metallic material layer 82′ over the patterned lift-off mask 77. The second metallic bonding pad layer 84 and the second metallic material layer 84′ can include an adhesion promoting metal having a melting temperature greater than 1,500 degrees Celsius. In one embodiment, the second metallic bonding pad layer 84 and the second metallic material layer 84′ can consist essentially of platinum. Horizontal portions of the second metallic bonding pad layer 84 and the second metallic material layer 84′ can have a thickness in a range from 50 nm to 500 nm, such as from 100 nm to 250 nm, although lesser and greater thicknesses can also be employed.
The exemplary structure is placed in an environment having an elevated temperature, which can be in a range from 100 degrees Celsius to 230 degrees Celsius (i.e., below the tin melting point), such as from 120 degrees Celsius to 200 degrees Celsius. Tin is deposited within each area inside an outer periphery of a topmost surface of the second metallic bonding pad layer 84 and on the second metallic material layer 84′ at the elevated temperature. Either pure tin (containing only unavoidable impurities) or tin containing less than 1 atomic percent (e.g., 0.5 atomic percent or less) of silver and/or copper as a dendrite prevention element is deposited in this step. Tin is a high temperature solder material, and provides a controlled reflow during a laser solder process that is subsequently employed. The elevated temperature during deposition of tin induces diffusion of tin into the second metallic bonding pad layer 84 during the deposition of tin onto the second metallic bonding pad layer 84.
A third metallic bonding pad layer 86 and a third metallic material layer 86′comprising an alloy (e.g., intermetallic) of platinum and tin is formed in upper regions of the respective second metallic bonding pad layer 84 and the second metallic material layer 84′ into which tin diffuses. The third metallic bonding pad layer 86 may contain between 60 and 80 weight percent tin and 20 to 40 weight percent platinum. The remaining lower portion of the second metallic bonding pad layer 84 includes tin at an atomic concentration less than 0.5% in atomic concentration, and is considered to be the remaining second metallic bonding pad layer 84. Thus, the second metallic bonding pad layer 84 can include surface portions including tin at an atomic concentration less than 0.5%, and can include a portion that consists essentially of platinum. The entire volume of the second metallic bonding pad layer 84 includes platinum at an atomic concentration of at least 99%, such as at least 99.5%. The unreacted portion of the deposited tin forms a tin portion 431. The tin portion 431 can include tin at an atomic concentration of at least 99%, such as at least 99.5% and may optionally include 0.5 atomic percent of silver and/or copper.
The thickness of the tin portion 431 can be in a range from 1 micron to 10 microns, such as from 1.5 micron to 4 microns. The first metallic bonding pad layer 82, the second metallic bonding pad layer 84, and the third metallic bonding pad layer 86 collectively constitute a device-side bonding pad 80. The thickness of the third metallic bonding pad layer 86 can be less than the thickness of the second metallic bonding pad layer 84. For example, the thickness of the second metallic bonding pad layer 84 can be in a range from 50 nm to 500 nm, such as from 100 nm to 250 nm. The thickness of the third metallic bonding pad layer 86 can be in a range from 40 nm to 400 nm, such as from 80 nm to 200 nm. Each region of the tin portion 431 includes tin at an atomic concentration of at least 99%. Regions of the tin portion 431 that are spaced from the device-side bonding pad 80 by more than 200 nm can consist essentially of tin. The tin to platinum volume ratio in the device-side bonding pad 80 can be at least 30:1, such as at least 50:1, for example 100:1 to 30:1. The stack of the third metallic material layer 86′, the second metallic material layer 84′ and the first metallic material layer 82′ constitutes a metallic material layer stack 80′.
Referring back to
In one embodiment, the first metallic bonding pad layer 82 can consist essentially of titanium, and the second metallic bonding pad layer 84 can consist essentially of platinum. In one embodiment, the first metallic bonding pad layer 82 can have a thickness in a range from 30 nm to 300 nm, the thinned portion of the second metallic bonding pad layer 84 can have a thickness in a range from 10 nm to 200 nm, the third metallic bonding pad layer 86 can have a thickness in a range from 40 nm to 400 nm within areas in which the tin portion 431 contacts the third metallic bonding pad layer 84, and the tin portion 431 can have a thickness in a range from 1 micron to 10 microns.
A direct view display device can be formed by transferring the light emitting diodes 10 of
Referring to
Generally, the same set of processing steps employed to form device-side bonding pads 80 can be employed to form an array of backplane-side bonding pads 421 on the front side of the backplane substrate 400. For example, a lift-off mask 277 can be formed on the top surface of the backplane substrate 400 by depositing and patterning a photoresist layer. The photoresist layer can be patterned to form openings in regions in which a backplane-side bonding pad 421 is to be subsequently formed. Material layers for forming backplane-side bonding pads 421 can be deposited. For example, a first backplane-side bonding pad metal can be anisotropically deposited to form a first backplane-side bonding pad layer 412 and a first metallic material layer 412′. The first backplane-side bonding pad layer 412 can be deposited directly on the physically exposed portions of the top surface of the backplane substrate 400, and the first metallic material layer 412′ can be deposited on a top surface of the patterned lift-off mask 277. The first backplane-side bonding pad layer 412 and the first metallic material layer 412′ can include a transition metal such as titanium or tantalum. In one embodiment, the first backplane-side bonding pad layer 412 and the first metallic material layer 412′ can consist essentially of titanium or tantalum. Horizontal portions of the first backplane-side bonding pad layer 412 and the first metallic material layer 412′ can have a thickness in a range from 30 nm to 300 nm, such as from 60 nm to 200 nm, although lesser and greater thicknesses can also be employed. The first backplane-side bonding pad layer 412 is electrically connected to the anode contact 50.
A second backplane-side bonding pad metal can be anisotropically deposited to form a second backplane-side bonding pad layer 414 and a second metallic material layer 414′. The second backplane-side bonding pad layer 414 can be deposited directly on the first backplane-side bonding pad layer 412, and the second metallic material layer 414′ can be deposited on a top surface of the first metallic material layer 412′ over the patterned lift-off mask 277. The second backplane-side bonding pad layer 414 and the second metallic material layer 414′ can include an adhesion promoting metal having a melting temperature greater than 1,500 degrees Celsius. In one embodiment, the second backplane-side bonding pad layer 414 and the second metallic material layer 414′ can consist essentially of platinum. The second backplane-side bonding pad layer 414 and the second metallic material layer 414′ can have a thickness in a range from 50 nm to 500 nm, such as from 100 nm to 250 nm, although lesser and greater thicknesses can also be employed.
The backplane 401 can be subsequently placed in an environment having an elevated temperature, which can be in a range from 100 degrees Celsius to 230 degrees Celsius, such as from 120 degrees Celsius to 200 degrees Celsius. Either pure tin or tin containing less than 1 atomic percent Ag and/or Cu can be deposited. Tin is deposited within each area inside an outer periphery of a topmost surface of the second backplane-side bonding pad layer 414 at the elevated temperature. Tin is a high temperature solder material, and reduces reflow during a laser solder process that is subsequently employed. The elevated temperature during deposition of tin induces diffusion of tin into the second backplane-side bonding pad layer 414 during the deposition of tin onto the second backplane-side bonding pad layer 414.
A third backplane-side bonding pad layer 416 comprising an alloy (e.g., intermetallic) of platinum and tin is formed in an upper region of the second backplane-side bonding pad layer 414 into tin diffuses. The third backplane-side bonding pad layer 416 may contain between 60 and 80 weight percent tin and 20 to 40 weight percent platinum. The remaining lower portion of the second backplane-side bonding pad layer 414 includes tin at an atomic concentration less than 0.5% in atomic concentration, and is considered to be the remaining second backplane-side bonding pad layer 414. Thus, the second backplane-side bonding pad layer 414 can include surface portions including tin at an atomic concentration less than 0.5%, and can include a portion that consists essentially of platinum. The entire volume of the second backplane-side bonding pad layer 414 includes platinum at an atomic concentration of at least 99%, such as at least 99.5%. The unreacted portion of the deposited tin forms a backplane-side tin portion 441 and a sacrificial tin portion on the patterned lift-off mask 277. The tin portion 441 can include tin at an atomic concentration of at least 99%, such as at least 99.5% and may optionally include 0.5 atomic percent of silver and/or copper.
Referring to
The first backplane-side bonding pad layer 412, the second backplane-side bonding pad layer 414, and the third backplane-side bonding pad layer 416 collectively constitute a backplane-side bonding pad 421. Each region of the backplane-side tin portion 441 includes tin at an atomic concentration of at least 99%. Regions of the backplane-side tin portion 441 that are spaced from the backplane-side bonding pad 421 by more than 200 nm can consist essentially of tin. The tin to platinum volume ratio in the combination of the backplane-side bonding pad 421 and the backplane-side tin portion 441 can be at least 30:1, such as at least 50:1, for example 100:1 to 30:1.
In one embodiment, the first backplane-side bonding pad layer 412 can consist essentially of titanium, and the second backplane-side bonding pad layer 414 can consist essentially of platinum. In one embodiment, the first backplane-side bonding pad layer 412 can have a thickness in a range from 30 nm to 300 nm, the thinned portion of the second backplane-side bonding pad layer 414 can have a thickness in a range from 10 nm to 200 nm, the third backplane-side bonding pad layer 416 can have a thickness in a range from 40 nm to 400 nm within areas in which the tin portion 431 contacts the third backplane-side bonding pad layer 416, and the backplane-side tin portion 441 can have a thickness in a range from 1 micron to 10 microns, such as 1.5 to 4 microns.
Multiple instances of a structure including a light emitting diode 10 and a tin portion 431 bonded thereto (as illustrated in
Referring to
Each backplane-side bonding pads (421, 422, 423) can have the same structure as the backplane-side bonding pad 421 illustrated in
Referring to
In one embodiment, the assembly of the backplane 401 and the backplane-side tin portions (441, 442, 443) can overlie the assembly of the first support substrate 22B and the first light emitting diodes 10B, and the heating laser 467 be irradiated on the assembly through backplane 401. A laser beam from the heating laser 467 propagate through the backplane 401 onto the backside of a selected backplane-side bonding pad 421, and heat and reflow the underlying backplane-side tin portion 441 and the underlying tin portion 431 to form a soldered (i.e., bonded) tin portion 451.
The backplane driver circuitry 440 (including the metal interconnect structures embedded in the backplane substrate 400) can be configured to provide openings over each backplane-side bonding pad (421, 422, 423) so that collateral heating of the metal interconnect structures inside the backplane substrate 400 can be minimized.
Alternatively, the assembly of the first support substrate 22B and the first light emitting diodes 10B can overlie the backplane 401. In this case, the laser beam may be transmitted through the first support substrate 22B and irradiate the reflector material layer 70 of an irradiated first light emitting diode 10B, which absorbs the laser beam and heats an underlying pair of a tin portion 431 and the underlying backplane-side tin portion 441 for selective heating and reflow to form a soldered (i.e., bonded) tin portion 451.
A soldered tin portion 451 may be formed from the reflowed materials of each heated and reflowed pair of a tin portion 431 and a backplane-side tin portion 441 from either method of laser irradiation. A third metallic bonding pad layer 86 and a third backplane-side bonding pad layer 416 that are bonded to the soldered tin portion 451 provide adhesion of the soldered tin portion 451 to an underlying backplane-side bonding pad 421 and an overlying device-side bonding pad 80 through gradual increase in the platinum concentration for each bonded first light emitting diode 10B.
The duration of the laser irradiation that induces the reflow of a vertical stack of a tin portion 431 and a backplane-side tin portion 441 can be less than 1 second, and may be less than 0.1 second, and/or less than 0.01 second, and/or less than 0.001 second. Thus, the irradiation process functions as a flash anneal. Such a short reflow time is generally insufficient for intermetallic formation. Further, the stack of a tin portion 431 and a backplane-side tin portion 441 consists of tin and optionally a small amount of platinum, silver or cupper (less than 0.5% in atomic concentration), and as such complex intermetallic formation is avoided. Thus, the soldered tin portions 451 can provide good adhesion without formation of complex intermetallic compounds in the solder material, which prevents formation of composition gradients of constituent metals within the center region of each soldered tin portion 451. The center region (occupying more than 99% in volume) of each soldered tin portion 451 can consist of tin (i.e., pure tin with unavoidable impurities) or tin containing 0.5 atomic percent or less of silver and/or copper as an anti-dendrite agent. Each soldered tin portion 451 can be relatively thin (e.g., 10 microns or less in thickness, such as 3 to 7 microns in thickness) due to its purity and provide a good planarity due to its softness.
Referring to
Referring to
Referring to
Referring to
The laser beam may be transmitted through the backplane substrate 401 and irradiate a selected backplane-side bonding pad 422 and an underlying backplane-side tin portion 442. Upon reflow of the backplane-side tin portion 442, an underlying tin portion 431 can be thermally connected and reflow. Depending on the intensity of the laser beam, the backplane-side tin portion 442 and the underlying tin portion 431 may be simultaneously heated by the laser beam. Alternatively, the laser beam may be transmitted through the second support substrate 22G and irradiate the reflector material layer 70 of an irradiated second light emitting diode 10G, which absorbs the laser beam and heats an underlying pair of a tin portion 431 and a backplane-side tin portion 442 for selective heating and reflow. A soldered tin portion 452 may be formed from the reflowed materials of each heated and reflowed pair of a tin portion 431 and a backplane-side tin portion 442. A third metallic bonding pad layer 86 and a third backplane-side bonding pad layer 416 that are bonded to the soldered tin portion 452 provide adhesion of the soldered tin portion 452 to an underlying backplane-side bonding pad 422 and an overlying device-side bonding pad 80 through gradual increase in the platinum concentration for each bonded second light emitting diode 10G.
Referring to
Referring to
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A front side transparent conductive oxide layer 450 can be formed over the dielectric matrix 445 and directly on the electrical nodes that are located on top of each transferred light emitting diode (10B, 10G, 10R). For example, the front side transparent conductive oxide layer 450 can be deposited on the compound semiconductor material layer 26 of each transferred light emitting diode (10B, 10G, 10R) and the physically exposed conductive pad structure (not shown) located on the backplane substrate 400, thereby providing a common electrical ground for the transferred light emitting diodes (10B, 10G, 10R). Alternatively, if the single crystalline buffer semiconductor layer 24 has a high resistivity and is not completely removed during the laser ablation step described above, additional n-type dopants can be introduced into the single crystalline buffer semiconductor layer 24 to provide sufficiently high conductivity, and the n-doped single crystalline buffer semiconductor layer 24 can be employed as a conductive path to the front side transparent conductive oxide layer 450.
An optional transparent passivation dielectric layer 452 can be formed over the front side transparent conductive oxide layer 450. The transparent passivation dielectric layer 452 can include silicon nitride or silicon oxide. Thus, the transferred light emitting diode (10B, 10G, 10R) can emit light through the n-doped compound semiconductor substrate layer 26, the front side transparent conductive oxide layer 450 and the transparent passivation dielectric layer 452. The light emitting diodes are vertical devices because they have electrical contacts on opposite sides, i.e., one electrical contact at top and another electrical contact at bottom.
Referring to
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The nickel atoms in the residual nickel layer 151 diffuse into the transparent conductive oxide layer 53, and combine with oxygen atoms in the transparent conductive oxide layer 53. A nickel-doped conductive oxide layer 251 can be formed at an interface between the transparent conductive oxide layer 53 and the p-doped semiconductor material layer 36. The nickel-doped conductive oxide layer 251 is a surface layer having a thickness in a range from 0.3 nm to 1 nm. The surface concentration of nickel, provided by integrating the bulk concentration of nickel over the entire thickness of the nickel-doped conductive oxide layer 251, can be in a range from 4×1013/cm2 to 2×1021/cm2, although lesser and greater surface concentrations of nickel atoms can also be employed. The transparent conductive oxide layer 53 may be substantially free of nickel, i.e., may contain nickel at an atomic concentration less than 0.1 part per million, and/or less than 1 part per billion. The nickel-doped conductive oxide layer 251 can provide enhanced adhesion between the p-doped semiconductor material layer 36 and the transparent conductive oxide layer 53.
Referring to
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In one embodiment, the nickel layer 151L is completely removed from the surface of the p-doped semiconductor material layer 36 after the step of etching back the nickel layer, and the residual nickel layer 151 illustrated in
In one embodiment, the nickel doped surface region 351 of the p-doped semiconductor material layer 36 has a nickel concentration in a range from 4×1013/cm2 to 2×1021/cm2, and a thickness in a range from 0.3 nm to 1 nm. However, lesser and greater concentrations of nickel and/or thicknesses may also be used
Referring to
In this embodiment, a dielectric masking layer 542 is formed on the buffer layer 24, as shown in
In another embodiment, plural (e.g., two or more) dielectric masking layers 542 containing pinholes 543 may be formed in a stack to make the dislocation termination at the dielectric masking layer more effective.
Preferably, the dielectric masking layer 542 is grown by atomic layer deposition (ALD) such that the pinholes 543 are formed spontaneously during the ALD growth without using lithography and etching. Thus, dielectric masking layer 542 with in-situ formed pinholes 543 is simpler to fabricate than the masking layer 42 of the previous embodiments in which the openings may be formed by lithography and etching.
Growth of dielectric layers by ALD typically requires a minimum thickness to fill the pinholes. The minimum thickness is typically a function of ALD growth temperature. The higher the temperature, the lower the minimum thickness required to fill the pinholes. Therefore, the dielectric masking layer 542 is grown to less than the minimum thickness required to fill the pinholes 543.
For example, for aluminum oxide dielectric masking layer 542 grown by ALD, the minimum thickness required to fill the pinholes 543 at a relatively high temperature (e.g., greater than 125° C.) is about 10 nm. In contrast, the minimum thickness required to fill the pinholes 543 at a relatively low temperature (e.g., about 100° C.) is about 3 nm. Therefore, when the ALD growth of the dielectric masking layer occurs at a temperature greater than 125° C., then the thickness of the dielectric masking layer is preferably 1 to 2 nm. In contrast, when the ALD growth of the dielectric masking layer occurs at a temperature of 80 to 120° C., then the thickness of the dielectric masking layer may be greater, and is preferably 1 to 3 nm. In general, the pinholes 543 preferably have a width of 0.1 to 200 nm, such as 0.1 to 20 nm, such as 1 to 10 nm, and the dielectric masking layer 542 preferably has a thickness of 1 nm to 20 nm, such as 1 nm to 3 nm.
Since the pinholes 543 are formed spontaneously in-situ during the ALD growth, in one embodiment the pinholes 543 are randomly distributed laterally (i.e., in a direction perpendicular to the top surfaces of the support substrate 22 and the semiconductor buffer layer 24) along the dielectric masking layer 542. Therefore, the distances d1, d2, etc. between nearest neighbor pinholes 543 may not be equal to each other and may vary randomly laterally along the dielectric masking layer 542, as shown in
As shown in
The semiconductor buffer layer 24 and the n-doped semiconductor material layer 26 may both comprise a III-nitride semiconductor material. For example, if the semiconductor buffer layer 24 comprises undoped gallium nitride, then the n-doped semiconductor material layer 26 may comprise n-doped gallium nitride. Preferably, the ALD growth of the dielectric masking layer 542 and epitaxial growth of the n-doped semiconductor material layer 26 from the semiconductor buffer layer 24 by metal organic chemical vapor deposition (MOCVD) (which may also be referred to as metal organic vapor phase epitaxy) occurs without breaking vacuum. In one embodiment, both the ALD and the MOCVD steps are carried out in the same vapor deposition chamber without breaking vacuum. In another embodiment, the ALD and the MOCVD steps are carried out in different deposition chambers of a same vacuum cluster tool. In other words, the ALD and the MOCVD steps are carried out in different deposition chambers of a multi-chamber deposition apparatus, with the support substrate 22 being moved between the deposition chambers through vacuum transfer ports.
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Optionally, the support substrate 22 may be removed from the LED 10 as described above and as shown in
In one embodiment, the pinholes 543 are randomly distributed laterally along the dielectric masking layer 542. A distance “d” between nearest neighbor pinholes 543 varies randomly laterally along the dielectric masking layer. The pinholes 543 extend through an entire thickness of the dielectric masking layer 542, such that the n-doped semiconductor material of the n-doped semiconductor layer 26 located in the pinholes 543 contacts the semiconductor buffer layer 24. In another embodiment, the pinholes 543 are provided in an ordered array and are distributed non-randomly.
In one embodiment, the pinholes 543 have a width of 0.1 to 200 nm, such as 0.1 to 20 nm, such as 1 to 10 nm, and the dielectric masking layer 542 has a thickness of 1 nm to 20 nm, such as 1 nm to 3 nm. The dielectric masking layer 542 may comprise any suitable insulating material, such as aluminum oxide or silicon nitride.
In one embodiment, the semiconductor buffer layer 24 and the n-doped semiconductor material layer 26 comprise a III-nitride semiconductor material. In one embodiment, the semiconductor buffer layer 24 comprises undoped gallium nitride and the n-doped semiconductor material layer 26 comprises n-doped gallium nitride.
While a III-nitride semiconductor LED containing the masking layer 542 with the pinholes 543 is described in the prior embodiments, the present invention is not so limited. The masking layer 542 containing the pinholes 543 may be located in any suitable device structure between any two layers. For example, a structure may include any first material layer 24, any second material layer 26, and a masking layer 542 having a thickness of 20 nm or less and containing pinholes 543 having a width of 200 nm or less filled with the second material of second material layer 26 located between the first material layer 24 and the second material layer 26. The first material layer 24 may comprise any suitable semiconductor, conductive or insulating material. The second material layer 26 may comprise any suitable semiconductor, conductive or insulating material. The first material may be the same as or different from the second material layer. For example, the first material layer 24 may comprise silicon (e.g., a silicon layer or a silicon substrate) and the second material layer 26 may comprise a compound semiconductor layer, such as a II-VI or III-V semiconductor material layer, including a III-nitride semiconductor material layer, such as a GaN layer. The structure may comprise a multi-layer substrate (e.g., a GaN on Si substrate) for growth of additional device layers or may comprise a portion of a device, such as a transistor, thyristor, photodetector, solar cell, laser or LED. In general, a method of embodiments of the present disclosure includes forming a first material layer 24, forming a masking layer 542 having a thickness of 20 nm or less and containing pinholes 543 having a width of 200 nm or less on the first material layer, and forming a second material layer 26 on the dielectric masking layer 543 such that the second material of the second material layer fills the pinholes and contacts the first material layer.
The preceding description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the following claims and the principles and novel features disclosed herein.
This is a Continuation Application of U.S. application Ser. No. 17/176,857 filed Feb. 16, 2021, which claims benefit of U.S. Provisional No. 62/993,919 filed on Mar. 24, 2020 and U.S. Provisional No. 62/977,920 filed Feb. 18, 2020 in the United States Patent and Trademark Office. The disclosures of which are incorporated herein by reference in their entireties.
| Number | Date | Country | |
|---|---|---|---|
| 62993919 | Mar 2020 | US | |
| 62977920 | Feb 2020 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 17176857 | Feb 2021 | US |
| Child | 18814791 | US |
