Patent Application
20240145240
Aspects of the present disclosure generally relate to the field of semiconductor devices and methods for manufacturing semiconductor devices. More particularly, the disclosure relates to selective deposition of epitaxial silicon films.
A typical selective epitaxy process involves a deposition reaction and an etch reaction. The deposition reaction causes an epitaxial layer to be formed on monocrystalline surfaces of a substrate and a polycrystalline and/or amorphous layer to be formed on non-monocrystalline surfaces, for example, a patterned dielectric layer deposited atop the substrate. The etch reaction removes the epitaxial layer and the polycrystalline and/or amorphous layer at different rates, providing a net selective process that can result in deposition of an epitaxial material and limited, or no, deposition of polycrystalline material.
As the critical dimensions of devices continue to shrink, methods of selective epitaxial deposition, such as the exemplary method described above, involve lower processing temperatures (e.g., about 600 degrees Celsius or less). Unfortunately, typical etching gases fail to provide a suitable selective window between the epitaxial layer and the polycrystalline and/or amorphous layer at such temperatures. In addition, the current cyclic deposition/etch process is a complex process, which is difficult to maintain and has low throughput.
For the foregoing reasons, there is a need for selective epitaxial processes that can be performed at lower temperatures.
Aspects of the present disclosure generally relate to the field of semiconductor devices and methods for manufacturing semiconductor devices. More particularly, the disclosure relates to selective deposition of epitaxial silicon films.
In at least one aspect, a method of forming a semiconductor device is provided. The method includes forming a multi-material layer on a substrate positioned in a processing region. The multi-material layer includes a plurality of crystalline first layers and a plurality of non-crystalline second layers arranged in an alternating pattern. The method further includes selectively forming a source region and a drain region on the crystalline first layers of the substrate. The formed source region and drain region contain an n-type dopant precursor concentration of greater than about 1×1021 atoms/cm3. Forming the source region and the drain region further includes flowing a first chlorosilane precursor gas selected from dichlorosilane and trichlorosilane; co-flowing a higher order chlorosilane precursor gas having a formula ClySixH(2X+2−y), wherein y is 3 or more and x is one or more and the higher order chlorosilane precursor gas is different from the first chlorosilane precursor gas; co-flowing an n-type dopant precursor gas with the first chlorosilane precursor gas and the higher order chlorosilane precursor gas; and heating the substrate to a temperature of about 550° C. or less.
Implementations may include one or more of the following. The higher order chlorosilane precursor gas comprises trichlorosilane (Cl3SiH), hexachlorodisilane (Si2Cl6), tetrachlorosilane (SiCl4), pentachlorodisilane (Cl5Si2H), octachlorotrisilane (Cl8Si3), or a combination thereof. A flow rate of the higher order chlorosilane precursor gas to a flow rate of the first chlorosilane precursor gas is 3:1 or greater. A flow rate of the higher order chlorosilane precursor gas to a flow rate of the first chlorosilane precursor gas is 10:1 or greater. Forming the source region and the drain region further includes maintaining the temperature within the processing region in a range from about 450 degrees Celsius to about 500 degrees Celsius, and a pressure within the processing region is maintained in a range from about 10 Torr to about 600 Torr. The n-type dopant precursor is a phosphorous containing precursor, an antimony precursor, or a combination thereof. The n-type dopant precursor is an antimony-containing precursor and the n-type dopant precursor concentration is an antimony concentration within the source region and the drain region that is greater than about 2×1021 atoms/cm3. The antimony-containing precursor is one or a combination of stibine, antimony trichloride, antimony tetrachloride, antimony pentachloride, triphenylantimony, antimony trihydride, antimonytrioxide, antimony pentoxide, antimony trifluoride, antimony tribromide, antimonytriiodide, antimony pentafluoride, triethyl antimony, and trimethyl antimony. The growth rate of the source region and the drain region on the crystalline first layers is greater than about 50 times the growth rate on the non-crystalline second layers. The non-crystalline second layers further comprise dielectric spacers disposed on the outer portion thereof. A plurality of gaps are formed adjacent to the non-crystalline second layers during the selective formation of the source region and the drain region. The method further includes flowing the first chlorosilane precursor at a flow rate in a range from about 100 to about 1,000 sccm; flowing the higher order chlorosilane at a flow rate in a range from about 1,000 to about 10,000 sccm; and flowing the n-type dopant precursor at a flow rate in a range from about 300 to about 1,000 sccm. The method further includes flowing hydrogen gas at a flow rate in a range from about 1 to about 40 SLM.
In another aspect, a method of forming a semiconductor device is provided. The method includes forming a multi-material layer on a substrate positioned in a processing region. The multi-material layer includes a plurality of crystalline first layers and a plurality of non-crystalline second layers arranged in an alternating pattern. The method further includes selectively forming a source region and a drain region on the crystalline first layers of the substrate. The formed source region and drain region contain an n-type dopant precursor concentration of greater than about 2×1021 atoms/cm3. Forming the source region and the drain region further includes flowing dichlorosilane; co-flowing trichlorosilane; co-flowing a phosphorous-containing precursor gas with the dichlorosilane and the trichlorosilane; and heating the substrate to a temperature of about 550° C. or less, wherein a ratio of a flow rate of TCS to DCS is in a range from about 3:1 to about 7:1.
Implementations may include one or more of the following. The phosphorous-containing precursor gas is selected from phosphine, trimethylphosphine, dimethylphosphine, triethylphosphine, diethylphosphine, tert-butylphosphine, or a combination thereof. The method further includes flowing the dichlorosilane at a flow rate in a range from about 700 sccm to about 1000 sccm; flowing the trichlorosilane at a flow rate in a range from about 2000 sccm to about 7000 sccm; and flowing phosphine at a flow rate in a range from about 0.1 sccm and 300 sccm. The method further includes flowing an antimony-containing precursor gas at a flow rate in a range from about 10 sccm to about 100 sccm.
In yet another aspect, a method of forming a semiconductor device is provided. The method includes forming a multi-material layer on a substrate positioned in a processing region. The multi-material layer includes a plurality of crystalline first layers and a plurality of non-crystalline second layers arranged in an alternating pattern. The method further includes selectively forming a source region and a drain region on the crystalline first layers of the substrate. The formed source region and drain region contain an n-type dopant precursor concentration of greater than about 1×1021 atoms/cm3. Forming the source region and the drain region further includes flowing pentachlorodisilane; co-flowing trichlorosilane; co-flowing an antimony-containing precursor gas with the pentachlorodisilane and the trichlorosilane; and heating the substrate to a temperature of about 550° C. or less, wherein a ratio of a flow rate of trichlorosilane to pentachlorodisilane is in a range from about 9:1 to about 16:1.
Implementations may include one or more of the following. The antimony-containing precursor gas is selected from stibine, antimony trichloride, antimony tetrachloride, antimony pentachloride, triphenylantimony, antimony trihydride, antimonytrioxide, antimony pentoxide, antimony trifluoride, antimony tribromide, antimonytriiodide, antimony pentafluoride, triethyl antimony, and trimethyl antimony. The method further includes flowing the pentachlorodisilane at a flow rate in a range from about 100 sccm to about 1000 sccm; flowing the trichlorosilane at a flow rate in a range from about 7000 sccm to about 10000 sccm; and flowing the antimony-containing precursor at a flow rate in a range from about 0.1 sccm and 100 sccm.
In another aspect, a non-transitory computer readable medium has stored thereon instructions, which, when executed by a processor, causes the process to perform operations of the above apparatus and/or method.
So that the manner in which the above-recited features of the present disclosure can be understood in detail, a more particular description of the aspects, briefly summarized above, may be had by reference to implementations, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical implementations of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective implementations.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one implementation may be beneficially incorporated in other implementations without further recitation.
Aspects of the present disclosure generally relate to the field of semiconductor devices and methods for manufacturing semiconductor devices. More particularly, the disclosure relates to selective deposition of epitaxial silicon films. A method of epitaxial deposition of n-channel metal oxide semiconductor (NMOS) source/drain regions formed in devices, for example, within horizontal gate all around (hGAA) device structures is provided. The method is performed at a temperature of 550 degrees Celsius or less. The method includes the use of a chlorosilane precursor, a higher order chlorosilane precursor, and an n-type dopant precursor selected from an antimony-containing precursor, a phosphorous-containing precursor, an arsenic-containing precursor, or a combination thereof.
Current epitaxial deposition processes have difficulty achieving co-flow selective Si:P or Si:Sb epitaxial deposition at low temperatures (e.g., 550 degrees Celsius or less) because HCl is not active at these low temperatures. As a result, current epitaxial deposition processes are performed using a cyclic deposition/etch process, which is complicated and time consuming leading to throughput issues. Aspects of the present disclosure provide a selective epitaxial deposition process that provides the co-flow of chlorosilane precursors with at least one of an antimony-containing precursor and a phosphorous-containing precursor. Aspects of the present disclosure utilize co-flowing of multiple chlorosilane precursors to enable combination of silicon and at least one of phosphorous and antimony in the same matrix using a low-temperature selective process. The deposited epitaxial layer using the epitaxial deposition techniques described not only contains phosphorous and/or antimony but also has a high activated phosphorous and/or antimony concentration.
The combination of chlorosilane precursors of the present disclosure is utilized to continuously etch the epitaxial layer as it is formed and improves the selectivity of the epitaxial layer as the epitaxial layer is deposited onto a device, for example, a superlattice structure. The epitaxial layer is formed only on the crystalline portions of the superlattice structure and not on oxide or non-crystalline surfaces. The antimony-containing precursor lowers the temperature at which the epitaxial layer is deposited and increases the growth rate of the epitaxial layer on the crystalline portions of the superlattice structure. The phosphorous-containing precursor dopes the epitaxial layer with phosphorous and enables better adhesion to the crystalline portions of the superlattice structure.
It has also been shown that the growth rate of the epitaxial layer with respect to the exposed crystalline surfaces of the superlattice structure changes with the addition of different concentrations of antimony in the epitaxial layer. In some aspects described, the concentration of antimony in the epitaxial layer is greater than about 1.0×1021 atoms/cm3 and growth is in primarily the <110> direction. The antimony concentration has been shown to cause the predominant crystal growth in the <110> direction. The crystal growth primarily in the <110> direction reduces faceting of the epitaxial layer on the superlattice structure.
The term “substrate” is intended to broadly cover any article or material having a surface onto which a material layer can be deposited. A substrate may include a bulk material such as silicon (e.g., single crystal silicon which may include dopants) or may include one or more layers overlying the bulk material. The substrate may be a planar substrate or a patterned substrate. Patterned substrates are substrates that may include electronic features formed into or onto a processing surface of the substrate. The substrate may contain monocrystalline surfaces and/or one secondary surface that is non-monocrystalline, such as polycrystalline or amorphous surfaces. Monocrystalline surfaces may include the bare crystalline substrate or a deposited single crystal layer usually made from a material such as silicon, germanium, silicon germanium or silicon carbon. Polycrystalline or amorphous surfaces may include dielectric materials, such as oxides or nitrides, specifically silicon oxide or silicon nitride, as well as amorphous silicon surfaces. The substrate may have various dimensions, such as 200 mm, 300 mm, 450 mm, or another diameter, as well as, being a rectangular or square panel. Unless otherwise noted, examples described are conducted on substrates with a 200 mm diameter, a 300 mm diameter, or a 450 mm diameter substrate.
In at least one aspect, the substrate includes a first surface and a second surface different from the first surface. At least one of the first surface and the second surface is monocrystalline and the other surface is non-monocrystalline. Positioning the substrate in the processing chamber may include adjusting one or more reactor conditions, such as temperature, pressure, and/or carrier gas (e.g., Ar, N2, H2, or He) flow rate, to conditions suitable for epitaxial film formation.
At operation 120, the substrate is heated to a temperature of 550 degrees Celsius or less. In at least one aspect, the temperature in the processing chamber may be adjusted so that a reaction region formed at or near an exposed surface of the substrate, or that the surface of the substrate itself, is about 550 degrees Celsius or less, or 500 degrees Celsius or less, or 450 degrees Celsius or less. In one example, the substrate is heated to a temperature in a range from about 400 degrees Celsius to about 550 degrees Celsius, or in a range from about 450 degrees Celsius to about 550 degrees Celsius, or in a range from about 450 degrees Celsius to about 500 degrees Celsius, or in a range from about 400 degrees Celsius to about 500 degrees Celsius. Not to be bound by theory but in some implementations where Si:P is formed, deposition of Si:P at temperatures below 450 degrees Celsius has a very slow growth rate and deposition at temperatures greater than 550 degrees Celsius may affect the thermal budget of other materials formed on the substrate. It is possible to minimize the thermal budget of the final device by heating the substrate to the lowest temperature sufficient to thermally decompose process reagents and epitaxially deposit a layer on the substrate. The pressure in the processing chamber may be adjusted so that the reaction region pressure is within range of about 1 to about 760 Torr, or in a range from about 1 torr to about 600 torr, or in a range from about 100 torr to about 300 torr, or in a range from about 200 torr to about 300 torr. In some implementations, a carrier gas (e.g., nitrogen) may be flowed into the processing chamber at a flow rate of approximately 1 to 40 SLM (standard liters per minute). Nitrogen remains inert during low temperature deposition processes. Therefore, nitrogen is not incorporated into the deposited layer during low temperature processes. Also, a nitrogen carrier gas does not form hydrogen-terminated surfaces as does a hydrogen carrier gas. However, it will be appreciated that in some implementations, a different carrier/diluent gas may be employed, for example, an inert carrier gas such as argon or helium, a different flow rate may be used, or that such gas(es) may be omitted.
At operation 130, a first chlorosilane precursor gas is introduced into the processing chamber. The first chlorosilane precursor gas includes precursors with both silicon and chlorine. In at least one implementation, the first chlorosilane gas includes dichlorosilane (SiCl2H2) (DCS), trichlorosilane (SiCl3H) (TCS), or a combination thereof. In one example, where dichlorosilane is used, the dichlorosilane is flowed into the processing chamber at a flow rate in a range from about 100 sccm to about 1000 sccm, or in a range from about 700 sccm to about 1000 sccm, or in a range from about 800 sccm to about 950 sccm, or in a range from about 850 sccm to about 900 sccm. In another example, where trichlorosilane is used, the trichlorosilane is flowed into the processing chamber at a flow rate in a range from about 1000 sccm to about 10000 sccm, or in a range from about 7000 sccm to about 10000 sccm, or in a range from about 7500 sccm to about 9000 sccm, or in a range from about 8000 sccm to about 8500 sccm.
At operation 140, a second chlorosilane precursor gas is introduced into the processing chamber. The second chlorosilane precursor gas is different from the first chlorosilane precursor gas. In at least one implementation, the second chlorosilane precursor gas is a higher order chlorosilane gas. The higher order chlorosilane gas may have formula ClySixH(2x+2−y) wherein y is 3 or more, or 5 or more, and x is one or more, or two or more, or 3 or more. In one example, y is from 5 to 8 and x is from 2 to 3. In at least one implementation, the second chlorosilane precursor gas comprises, consists of, or essentially consists of trichlorosilane, hexachlorodisilane (Si2Cl6), tetrachlorosilane (SiCl4), pentachlorodisilane (Cl5Si2H), octachlorotrisilane (Cl8Si3), or a combination thereof. In another implementation, the second chlorosilane gas comprises, consists of, or essentially consists of pentachlorodisilane (Cl5Si2H), hexachlorodisilane (Si2Cl6), octachlorotrisilane (Cl8Si3), or a combination thereof. In one example, where pentachlorodisilane (PCDS) is used, the pentachlorodisilane is flowed into the processing chamber at a flow rate in a range from about 100 sccm to about 1000 sccm, or in a range from about 300 sccm to about 600 sccm, or in a range from about 400 sccm to about 550 sccm, or in a range from about 450 sccm to about 500 sccm. In another example, where trichlorosilane is used, the trichlorosilane is flowed into the processing chamber at a flow rate in a range from about 1000 sccm to about 10000 sccm, or in a range from about 7000 sccm to about 10000 sccm, or in a range from about 7500 sccm to about 9000 sccm, or in a range from about 8000 sccm to about 8500 sccm.
At operation 150, an n-type dopant precursor is introduced into the processing chamber. In at least one aspect, the n-type dopant precursor comprises, consists of, or essentially consists of a phosphorous containing precursor, an antimony precursor, an arsenic-containing precursor, or a combination thereof. In at least one implementation, the antimony-containing precursor includes one or a combination of stibine, antimony trichloride, antimony tetrachloride, antimony pentachloride, triphenylantimony, antimony trihydride, antimonytrioxide, antimony pentoxide, antimony trifluoride, antimony tribromide, antimonytriiodide, antimony pentafluoride, triethyl antimony, and trimethyl antimony. In at least one particular implementation, triethyl antinomy is used. The antimony-containing precursor may have a flow rate in a range from about 0.1 sccm and 300 sccm, or in a range from about 10 sccm to about 100 sccm. In at least one implementation, the phosphorous-containing precursor includes one or a combination of phosphine and alkylphosphines. Suitable alkylphosphines include trimethylphosphine ((CH3)3P), dimethylphosphine ((CH3)2PH), triethylphosphine ((CH3CH2)3P), tert-butylphosphine, and diethylphosphine ((CH3CH2)2PH). In at least one particular implementation, phosphine is used. The phosphorous-containing precursor may have a flow rate in a range from about 0.1 sccm and 1,000 sccm, 0.1 sccm and 300 sccm, or in a range from about 100 sccm to about 300 sccm, or in a range from about 300 to about 1,000 sccm. In at least one implementation, the arsenic-containing precursor includes one or a combination of arsine (AsH3), halogenated arsenic compounds, trimethylarsenic, and silylarsines [(H3Si)3-xAsRx] where x=0, 1, 2, and Rx is hydrogen or deuterium. The arsenic-containing precursor may have a flow rate in a range from about 0.1 sccm and 1,000 sccm, 0.1 sccm and 300 sccm, or in a range from about 100 sccm to about 300 sccm, or in a range from about 300 to about 1,000 sccm.
It is contemplated that the operation 130, the operation 140, and the operation 150 may occur simultaneously, substantially simultaneously, or in any targeted order. In at least one aspect, each of the first chlorosilane precursor gas, the second chlorosilane precursor gas, the antimony-containing precursor, and the phosphorous-containing precursor are co-flowed into the process chamber simultaneously. Not to be bound by theory but it is believed that co-flowing each of the first chlorosilane precursor gas, the second chlorosilane precursor gas, the antimony-containing precursor, and the phosphorous-containing precursor improves the electrical conductivity of the antimony-doped source/drain regions and enables the deposition temperature to be less than 550 degrees Celsius. In one implementation, at least two of the precursor gases are mixed prior to being delivered to the processing region. In another implementation, at least two of the precursor gases are delivered to the processing region separately and mixed within the processing region.
In at least one implementation, a flow rate of the second chlorosilane precursor gas to a flow rate of the first chlorosilane precursor gas is 3:1 or greater, for example, in a range from about 3:1 to about 7:1. In one example, a flow rate of the second chlorosilane precursor gas to a flow rate of the first chlorosilane precursor gas is 10:1 or greater. In another aspect, a flow rate of the first chlorosilane precursor gas to a flow rate of the second chlorosilane precursor gas is 7:1 or greater, for example, in a range from about 7:1 to about 20:1, or in a range from about 9:1 to about 16:1. In one example, a flow rate of the first chlorosilane precursor gas to a flow rate of the second chlorosilane precursor gas is 10:1 or greater.
In one aspect, the first chlorosilane precursor gas is dichlorosilane, the second chlorosilane precursor gas is trichlorosilane, and the n-type dopant gas is phosphine. The mixture of DCS and TCS includes a mixture of TCS to DCS at a ratio of a flow rate 2:1 or greater, for example, in a range from about 3:1 to about 7:1. In some implementations, TCS has been shown to only grow phosphorous-doped epitaxial layers when DCS is present and does not form the phosphorous-doped epitaxial layers or forms the phosphorous-doped epitaxial layers at a drastically reduced rate when the DCS is not co-flown therewith. DCS has been shown to increase the growth rate of the phosphorous-doped source/drain regions. The chlorosilane precursors enable growth of the phosphorous-doped epitaxial layers. As the phosphorous-doped epitaxial layers are grown, etch back operations are not performed. The chlorine within the chlorosilane precursor gases has been shown to improve the crystalline growth of the epitaxial layer without additional etch back processes. In one example, dichlorosilane is introduced into the processing chamber at a flow rate in a range from about 700 sccm to about 1000 sccm, or in a range from about 800 sccm to about 950 sccm, or in a range from about 850 sccm to about 900 sccm. Trichlorosilane is introduced into the processing chamber at a flow rate in a range from about 1000 sccm to about 10000 sccm, or in a range from about 2000 sccm to about 7000 sccm, or in a range from about 3000 sccm to about 6000 sccm, or in a range from about 3000 sccm to about 4000 sccm. Phosphine is introduced into the processing chamber at a flow rate in a range from about 0.1 sccm and 300 sccm, or in a range from about 100 sccm to about 300 sccm.
In another aspect, the first chlorosilane precursor gas is trichlorosilane (TCS), the second chlorosilane precursor gas is pentachlorodisilane (PCDS), and the n-type dopant gases include triethyl antimony, and optionally phosphine. The mixture of TCS and PCDS includes a mixture of TCS to PCDS at about 7:1 to about 20:1, or in a range from about 9:1 to about 16:1. In some implementations, TCS has been shown to only grow antimony-doped epitaxial layers when PCDS is present and does not form the antimony-doped epitaxial layers or forms the antimony-doped epitaxial layers at a drastically reduced rate when the PCDS is not co-flown therewith. PCDS has been shown to increase the growth rate of the antimony-doped source/drain regions. The chlorosilane precursor gases enable growth of the antimony-doped epitaxial layers. As the antimony-doped epitaxial layers are grown, etch back operations are not performed. The chlorine within the chlorinated silicon precursor has been shown to improve the crystalline growth of the epitaxial layer without additional etch back processes. In one example, PCDS is introduced into the processing chamber at a flow rate in a range from about 100 sccm to about 1000 sccm, or in a range from about 300 sccm to about 600 sccm, or in a range from about 400 sccm to about 550 sccm, or in a range from about 450 sccm to about 500 sccm. Trichlorosilane is introduced into the processing chamber at a flow rate in a range from about 1000 sccm to about 10000 sccm, or in a range from about 7000 sccm to about 10000 sccm, or in a range from about 7500 sccm to about 9000 sccm, or in a range from about 8000 sccm to about 8500 sccm. Triethyl antimony is introduced into the processing chamber at a flow rate of a flow rate in a range from about 0.1 sccm and 100 sccm, or in a range from about 100 sccm to about 300 sccm. Phosphine is introduced into the processing chamber at a flow rate of a flow rate in a range from about 0.1 sccm and 300 sccm, or in a range from about 100 sccm to about 300 sccm.
At operation 160, an n-type doped silicon layer is selectively formed on the first surface. The mixture of the first chlorosilane precursor gas, the second chlorosilane precursor gas, and the one or more n-type dopants are thermally reacted to selectively form the n-type doped silicon layer on the first surface. In one aspect, the n-type doped silicon layer is a phosphorous doped silicon layer having a phosphorous concentration of 2×1021 atoms/cm3 or greater, for example, 3.5×1021 atoms/cm3, 3.9×1021 atoms/cm3, or 4×1021 atoms/cm3 or greater. In another aspect, the n-type doped silicon layer is an antimony doped silicon layer having an antimony concentration of 1×1021 atoms/cm3 or greater, for example, 1.5×1021 atoms/cm3, 2×1021 atoms/cm3, or 3×1021 atoms/cm3 or greater. In some implementations, the n-type doped silicon layer is then exposed to a thermal treatment process, for example, a spike anneal process. The spike anneal process may be performed at temperatures of about 900° C. to about 1200° C. for a time of about 1 second to about 30 seconds.
The hGAA structure 200 includes the multi-material layer 205 disposed on a top surface 203 of the substrate 202, such as on top of an optional material layer 204 disposed on the substrate 202. In implementations in which the optional material layer 204 is not present, the multi-material layer 205 is directly formed on the substrate 202.
In one example, the optional material layer 204 is an insulating material. Suitable examples of the insulating material may include silicon oxide material, silicon nitride material, silicon oxynitride material, or any suitable insulating materials. Alternatively, the optional material layer 204 may be any suitable materials including conductive material or non-conductive material as needed. The multi-material layer 205 includes at least one pair of layers, each pair comprising the first layer 206 and the second layer 208. Although the example depicted in
In at least one implementation, the first layers 206 are crystalline material layers, such as a single crystalline, polycrystalline, or monocrystalline silicon layer. The first layers 206 are formed using an epitaxial deposition process. Alternatively, the first layers 206 are doped silicon layers, including p-type doped silicon layers or n-type doped layers. Suitable p-type dopants include B dopants, Al dopants, Ga dopants, In dopants, or the like. Suitable n-type dopants include N dopants, P dopants, As dopants, Sb dopants, or the like. In yet another example, the first layers 206 are a group III-V material, such as a GaAs layer.
The second layers 208 are non-crystalline material layers. In at least one aspect, the second layers 208 are Ge containing layers, such as SiGe layers, Ge layers, or other suitable layers. Alternatively, the second layers 208 are doped silicon layers, including p-type doped silicon layers or n-type doped layers. In yet another example, the second layers 208 are group III-V materials, such as a GaAs layer. In still another example, the first layers 206 are silicon layers and the second layers 208 are a metal material having a high-k material coating on outer surfaces of the metal material. Suitable examples of the high-k material includes hafnium dioxide (HfO2), zirconium dioxide (ZrO2), hafnium silicate oxide (HfSiO4), hafnium aluminum oxide (HfAlO), zirconium silicate oxide (ZrSiO4), tantalum dioxide (TaO2), aluminum oxide, aluminum doped hafnium dioxide, bismuth strontium titanium (BST), or platinum zirconium titanium (PZT), among others. In one particular example, the coating layer is a hafnium dioxide (HfO2) layer. In at least one implementation, the second layers 208 are a similar material to the gate structure 212 to form a wraparound gate around the first layers 206.
The spacers 210 are formed adjacent to the ends of the second layers 208 and may be considered a portion of the second layers 208. The spacers 210 are dielectric spacers or air gaps. The spacers 210 may be formed by etching away a portion of each of the second layers 208 using an etching precursor to form a recess at the ends of each of the second layers 208. The spacers 210 are formed in the recesses adjacent each of the second layers 208. A liner layer (not shown) may additionally be deposited within the recesses before the deposition of the spacers 210. The spacers 210 are formed from a dielectric material and separate each of the nanowires or nanosheets formed as the first layers 206. In at least one implementation, the spacers 210 are selected to be a silicon containing material that may reduce parasitic capacitance between the gate and source/drain structure in the hGAA nanowire structure, such as a low-K material. The silicon containing material or the low-K material may be silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbide nitride, doped silicon layer, or other suitable materials, such as Black Diamond® material available from Applied Materials.
In at least one example, the spacers 210 are a low-k material (e.g., dielectric constant less than 4) or a silicon oxide/silicon nitride/silicon carbide containing material. In another example, the spacers 210 are air gaps.
The gate structure 212 is disposed over and around the multi-material layer 205. The gate structure 212 includes a gate electrode layer and may additionally include a gate dielectric layer, gate spacers, and a mask layer, according to one implementation. The gate electrode layer of the gate structure 212 includes a polysilicon layer or a metal layer that is capped with a polysilicon layer. The gate electrode layer can include metal nitrides (such as titanium nitride (TiN), tantalum nitride (TaN) or molybdenum nitride (MoNx)), metal carbides (such as tantalum carbide (TaC) or hafnium carbide (HfC)), metal-nitride-carbides (such as TaCN), metal oxides (such as molybdenum oxide (MoOx)), metal oxynitrides (such as molybdenum oxynitride (MoOxNy)), metal silicides (such as nickel silicide), or a combination thereof. The gate electrode layer is disposed on top of and around the multi-material layer 205.
A gate dielectric layer may optionally be disposed below the gate electrode layer and below the multi-material layer 205. The optional gate dielectric layer can include silicon oxide (SiOx), which can be formed by a thermal oxidation of one or more of the first layers 206 or and/or the second layers 208, or by any suitable deposition process. Suitable materials for forming the gate dielectric layer include silicon oxide, silicon nitrides, oxynitrides, metal oxides such as hafnium oxide (HfO2), hafnium zirconium oxide (HfZrOx), hafnium silicon oxide (HfSiOx), hafnium titanium oxide (HfTiOx), hafnium aluminum oxide (HfAlOx), and combinations and multi-layers thereof. Gate spacers are formed on sidewalls of the gate electrode layer. Each gate spacer includes a nitride portion and/or an oxide portion. A mask layer is formed on top of the gate electrode layer and can include silicon nitride.
The hGAA structure 200 is formed using the method 400 of
The multi-material layer 205 and the gate structure 212 described with respect to
The gate structure 212 is formed around the multi-material layer 205. In at least one implementation, the gate electrode layer of the gate structure 212 is a similar material to the material of each of the second layers 208 within the multi-material layer 205. The gate structure 212 and the second layers 208 form a wrap-around gate around each of the first layers 206. The first layers 206 act as nanowires or nanosheets disposed within the wrap-around gate. The first layers 206 serve as a channel between source/drain regions after the formation of the source/drain regions.
After the formation of the film-stack during operation 410, the n-type doped source/drain regions 214a, 214b are formed during operation 420 as shown in
In at least one implementation, the deposition gas mixture includes a first chlorosilane precursor, a second chlorosilane precursor, and an n-type dopant as described.
The amount of excessive point defects in the n-type doped source/drain regions 214a, 214b can be controlled by varying processing conditions, such as partial pressure of the precursors, ratio of the precursors, processing temperature, and/or layer thickness. The amount of excessive point defects in the n-type doped source/drain regions 214a, 214b can control diffusion of the antimony atoms into the first layers 206 of the multi-material layer 205. During the deposition of the n-type doped source/drain regions 214a, 214b, Sb atoms can be diffused into the first layers 206 of the multi-material layer 205. P-dopants are added to the n-type doped source/drain regions 214a, 214b using a P-containing precursor. The P-containing precursor is flown simultaneously to both the chlorosilane-containing precursor and the antimony-containing precursor.
Each of the first chlorosilane containing precursor gas, the second chlorosilane containing precursor gas, and the n-type containing precursor are co-flowed into the process chamber simultaneously. Co-flowing each of the first chlorosilane containing precursor gas, the second chlorosilane containing precursor gas, and the n-type containing precursor gas improves the electrical conductivity of the antimony and/or phosphorous-doped source/drain regions 214a, 214b and enables the deposition temperature to be less than 550 degrees Celsius. In some implementations, the phosphorous-containing precursor is a generic n-type dopant precursor. In one example described, the ratio of first chlorosilane precursor gas to the second chlorosilane precursor gas to the n-type dopant precursor gas (e.g., phosphorous) flown into the process chamber is about 3:1:0.1 to about 7:1:0.3 for TCS/DCS/PH3. In another example described, the ratio of first chlorosilane precursor gas to the second chlorosilane precursor gas to the n-type dopant precursor gas (e.g., antimony) flown into the process chamber is about 7:1:0.1 to about 20:1:1, or is about 9:1:0.1 to 16:1:0.1 for TCS/PCDS/TeSb. In yet another example described, the ratio of first chlorosilane precursor gas to the second chlorosilane precursor gas to the n-type dopant precursor gas (e.g., antimony) flown into the process chamber is about 3:1:0.1:0.1 to about 7:1:0.3:0.3 for TCS/PCDS/TeSb/PH3.
In one example, the n-type doped source/drain regions 214a, 214b have a phosphorous concentration of 2.0×1021 atoms/cm3 or greater, for example, 3.5×1021 atoms/cm3, 3.9×1021 atoms/cm3, or 4.0×1021 atoms/cm3 or greater. In another example, the n-type doped source/drain regions 214a, 214b have an antimony concentration of 1.0×1021 atoms/cm3 or greater, for example, 1.5×1021 atoms/cm3, 2.0×1021 atoms/cm3, or 3.0×1021 atoms/cm3 or greater. In yet another example, the n-type doped source/drain regions 214a, 214b have an antimony concentration of 1.0×1021 atoms/cm3 or greater, for example, 1.5×1021 atoms/cm3, 2.0×1021 atoms/cm3, or 3.0×1021 atoms/cm3 or greater. The phosphorous-dopant concentration within the deposited n-type doped source/drain regions 214a, 214b is about 2.0×1021 atoms/cm3 to about 4.0×1021 atoms/cm3. The low temperature deposition of the n-type doped source/drain regions 214a, 214b further decreases the migration of the antimony into other portions of the multi-material layer 205 and the substrate as the antimony diffusion may cause degradation of device performance.
The concentration of the antimony-dopant within the n-type doped source/drain regions 214a, 214b alters the growth rate of the n-type doped source/drain regions 214a, 214b. It has been found that with lower concentrations of antimony-dopant or in implementations without co-flow of the antimony-dopant, the deposition rate of the n-type doped source/drain regions 214a, 214b at temperatures less than 550 degrees Celsius is greatly reduced. In some implementations, the concentration of the antimony within the n-type doped source/drain regions 214a, 214b has been found to increase deposition rates by over twice the growth rate compared to processes without any antimony-containing precursor. In some implementations, the growth rate of the n-type doped source/drain regions 214a, 214b is near zero on both crystalline and non-crystalline locations of the substrate at temperatures less than 550 degrees Celsius without the simultaneous co-flow of both the antimony-containing precursor and the chlorosilane precursors. The antimony within the antimony-containing precursor acts to lower the surface activation energy of the first layers 206, so that the n-type doped source/drain regions 214a, 214b are formed. The growth rate of the n-type doped source/drain regions 214a, 214b is highly selective to crystalline structures, such that the growth rate of the n-type doped source/drain regions 214a, 214b on the first layers 206 is greater than about 100× the growth rate of the n-type doped source/drain regions s 214a, 214b on the spacers 210 and the gate structure 212, such as greater than about 150× the growth rate. In some implementations, the growth rate of the n-type doped source/drain regions 214a, 214b is about 10 angstroms/minute to about 20 angstroms/minute.
In some implementations, the deposition of the n-type doped source/drain regions 214a, 214b with antimony is performed in a first processing chamber and the doping of the n-type doped source/drain regions 214a, 214b with phosphorous is performed in a second processing chamber. In yet other implementations, the formation of the n-type doped source/drain regions 214a, 214b with antimony and the doping of the n-type doped source/drain regions 214a, 214b with phosphorous are performed in one chamber.
After operation 420, operation 430 of thermally treating the hGAA structure 200 is performed. In at least one implementation, thermal treatment of the hGAA structure is a spike anneal process. The spike anneal process is performed at temperatures of about 900° C. to about 1200° C. for a time of about 1 second to about 30 seconds. Due to the large size of the Sb atoms, the Sb atoms do not diffuse at the same rate as the P dopant. The short time period of the spike anneal thus suppresses Sb atom diffusion, while allowing some P dopant to diffuse in the first layers 206 to form a doped region 320 of the first layers 206 of the multi-material layer 205 as shown in
As the temperature of operation 420 and operation 430 is kept below about 550° C., the diffusion of dopants and warpage of the multi-material layer 205 is reduced.
A capping layer (not shown) may be optionally deposited over the hGAA structure 200 after the formation of the n-type doped source/drain regions 214a, 214b. The capping layer is a silicon-containing layer and is deposited on top of each of the n-type doped source/drain regions 214a, 214b and the spacers 210, such that the capping layer fills the gaps 211.
The following non-limiting examples are provided to further illustrate implementations described. However, the examples are not intended to be all-inclusive and are not intended to limit the scope of the embodiments described.
The examples were performed on a wafer with exposed crystalline silicon layer wafer having a patterned silicon nitride layer deposited on the exposed crystalline silicon layer. The patterned silicon nitride layer exposes trenches formed in the crystalline silicon.
In the Summary and in the Detailed Description, and the Claims, and in the accompanying drawings, reference is made to particular features (including method operations) of the present disclosure. It is to be understood that the disclosure in this specification includes all possible combinations of such particular features. For example, where a particular feature is disclosed in the context of a particular aspect, implementation, or example of the present disclosure, or a particular claim, that feature can also be used, to the extent possible in combination with and/or in the context of other particular aspects and implementations of the present disclosure, and in the present disclosure generally.
The term “comprises” and grammatical equivalents thereof are used to mean that other components, ingredients, operations, etc. are optionally present. For example, an article “comprising” (or “which comprises”) components A, B, and C can consist of (i.e., contain only) components A, B, and C, or can contain not only components A, B, and C but also one or more other components. In addition, whenever a composition, an element or a group of elements is preceded with the transitional phrase “comprising” and grammatical equivalents thereof, it is understood that it is contemplated that the same composition or group of elements may be preceded with transitional phrases “consisting essentially of,” “consisting of,” “selected from the group of consisting of,” or “is” preceding the recitation of the composition, element, or elements and vice versa.
Where reference is made to a method comprising two or more defined operations, the defined operations can be carried out in any order or simultaneously (except where the context excludes that possibility), and the method can include one or more other operations which are carried out before any of the defined operations, between two of the defined operations, or after all of the defined operations (except where the context excludes that possibility).
When introducing elements of the present disclosure or exemplary aspects or embodiment(s) thereof, the articles “a,” “an,” “the” and “said” are intended to mean that there are one or more of the elements.
While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
This application claims the benefit of U.S. Provisional Patent Application Ser. No. 63/419,359, filed Oct. 26, 2022, which is incorporated by reference herein in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 63419359 | Oct 2022 | US |
