Patent Application
20240421124
This application claims the priority benefit of Taiwan application serial no. 112122519, filed on Jun. 16, 2023. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
The disclosure relates to an electronic component, and in particular relates to a manufacturing method of an electronic package and an electronic package.
There are many types of electronic packaging technologies currently used for multi-chips, one of which is to form a redistribution structure on a bridge element, and then bond multiple chips to the redistribution structure in a flip-chip manner. Therefore, the bridge element overlapping with the adjacent chips can shorten the signal transmission path between the adjacent chips. In order to protect the chips and the bridge element, a conventional method is to adopt a molding compound to cover the bridge element and the chips. However, even if the chips are correctly positioned, the injection of the molding compound may still cause alignment shift of the chips. and the thermal curing process of the molding compound may accumulate stress on the contact surface between the chips and the material due to the large difference in thermal expansion coefficient.
The disclosure provides a manufacturing method of an electronic package, which is used to manufacture the electronic package.
The disclosure provides an electronic package, which is used to provide preferable packaging quality.
A manufacturing method of an electronic package according to an embodiment of the disclosure includes the following steps. Multiple chips and a base dielectric layer are provided. A back surface of each of the chips is fixed to a back surface temporary carrier via a back surface temporary bonding layer. The base dielectric layer surrounds each of the chips and covers the back surface temporary bonding layer. A material of the base dielectric layer includes a silicate composite material or a material suitable for chemical-mechanical polishing. At least one bridge element is installed on active surfaces of the adjacent chips such that the bridge element respectively partially overlaps with the adjacent chips. Multiple bridging pads of the bridge element are respectively bonded to multiple first chip pads of the active surfaces of the adjacent chips. An intermediate dielectric layer covering the base dielectric layer, the chips, and the bridge element is formed. The bridge element and the intermediate dielectric layer are thinned and planarized. Multiple intermediate conductive vias and a redistribution structure are formed. The intermediate conductive vias respectively pass through the intermediate dielectric layer and are respectively connected to multiple second chip pads of the active surfaces of the chips, and the redistribution structure is on the intermediate dielectric layer and the intermediate conductive vias. Multiple conductive bumps are formed on the redistribution structure. The back surface temporary bonding layer and the back surface temporary carrier are removed to expose the back surface of each of the chips.
An electronic package according to an embodiment of the disclosure includes a sub-package. The sub-package includes multiple chips, a base dielectric layer, at least one bridge element, an intermediate dielectric layer, multiple intermediate conductive vias, a redistribution structure, and multiple conductive bumps. The base dielectric layer covers the chips and exposes active surfaces and back surfaces of at least part of the chips. A material of the base dielectric layer includes a silicate composite material or a material suitable for chemical-mechanical polishing. The at least one bridge element respectively partially overlaps with the adjacent chips. Multiple bridging pads of the bridge element are respectively bonded to multiple first chip pads of the active surfaces of the adjacent chips. The intermediate dielectric layer is disposed on the chips and the base dielectric layer and surrounds the at least one bridge element. The intermediate conductive vias pass through the intermediate dielectric layer and are respectively connected to multiple second chip pads of the active surfaces of the chips. The redistribution structure is disposed on the intermediate dielectric layer and the intermediate conductive vias. The conductive bumps are disposed on the redistribution structure.
Based on the above, the material of the base dielectric layer and the material of the intermediate dielectric layer can reduce the interface stress between the material and each chip, so that the control of the material and processing is easier to obtain a finished product with high reliability. Moreover, the direct copper bond of the bridge element to the chips also helps to drastically improve transmission performance and power cost performance ratio. In other words, the bridging pads of the bridge element are respectively bonded to the first chip pads of the active surfaces of the adjacent chips, which helps to reduce circuit power, increase bridging density, and achieve high-performance computing applications.
A manufacturing method of an electronic package according to an embodiment of the disclosure will be described below with reference to
Please refer to
In the embodiment, one of the chips 110 may be a central processing unit chip, a logic chip, a graphics processing chip, an input/output chip, a memory chip, a base band chip, a radio frequency (RF) chip, or an integrated circuit chip with a specific function. In other words, the chips 110 may include a combination of the chips of different functional types, so that an electronic package 10 may be used in a chiplet packaging technology, which is similar to system in package (SiP). Since the chips 110 may have different functions, the sizes of the chips 110 may be different. In some embodiments, the chips may be a combination of a central processing unit chip and a logic chip, a combination of a central processing unit chip and an input/output chip, a combination of a graphics processing chip and a memory chip, or a combination of a radio frequency chip and a base band chip, and may also be a combination of two chips with the same function.
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It is worth mentioning that in the known packaging technology, the molding compound is often used to cover the chip, but the coefficient of thermal expansion of the molding compound is much greater than the coefficient of thermal expansion of the chip. Moreover, the particles of the molding compounds are larger, so it is not easy for the particles to fill the gap, and the molding compound is also prone to stress. However, the disclosure uses a nanoscale material with a coefficient of thermal expansion close to the coefficient of thermal expansion of silicon. The material has smaller particles and improved filling capability, so the material can effectively fill the gap. In the embodiment, the base dielectric layer 121 may fill the gap G between two adjacent chips 110.
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In the embodiment, the chips 110 and the base dielectric layer 121 may be provided by the above steps corresponding to
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In an embodiment, the material of the bridge element 130 may include an inorganic material such as silicon, glass, and ceramics or an organic material. The bridge element 130 may be an active element or a passive element. Furthermore, in the embodiment, the connection between the bridge element 130 and the chip 110 is a direct connection (pad to pad) between the bridging pad 131 and the first chip pad 111. Compared with the prior art, each chip is connected to the bridge element through a redistribution structure (redistribution layer, RDL). The embodiment may further shorten a transmission distance of electrical signals between the chips, and there is less issue of alignment shift. Furthermore, in an embodiment, the size of the first chip pad 111 is not greater than the size of a second chip pad 112. A pitch of two adjacent first chip pads 111 is not greater than a pitch of two adjacent second chip pads 112, and the pitch of two adjacent first chip pads 111 is, for example, less than 10 μm. In addition, a distribution density of the first chip pads 111 may be greater than a distribution density of the second chip pads 112.
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In the embodiment, forming the intermediate conductive vias 142 may include forming multiple through holes in the intermediate dielectric layer 141, and filling a conductive material into the through holes to form the intermediate conductive vias 142.
In the embodiment, the redistribution structure 150 may be formed by adopting a build-up process. The redistribution structure 150 may include multiple redistribution patterned conductive layers 152, multiple redistribution dielectric layers 154, and multiple redistribution conductive vias 156. The redistribution patterned conductive layers 152 are alternately stacked with the redistribution dielectric layers 154. The redistribution conductive vias 156 are respectively connected to the redistribution patterned conductive layers 152. In addition, multiple under bump metallurgy (UBM) layers 158 are further formed on multiple parts of the redistribution patterned conductive layers 152 farthest from the chips 110.
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An electronic package according to an embodiment of the disclosure will be described below with reference to
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The bridge element 130 respectively partially overlaps with the adjacent chips 110. wherein the thickness of the bridge element 130 is less than the thickness of the chips 110. The bridging pads 131 of the bridge element 130 may be respectively bonded to the first chip pads 111 of the active surfaces 110a of the adjacent chips 110. The intermediate dielectric layer 141 is disposed on the chips 110 and the base dielectric layer 121 and surrounds the bridge element 130.
The material of the intermediate dielectric layer 141 is a silicate composite material, silicon oxide, derivatives of silicon oxide, silicon oxynitride, silicon carbonitride, polyimide, or benzocyclobutene. The silicate composite material is preferably a silicate nanocomposite material. In an embodiment, the materials of the intermediate dielectric layer 141 and the base dielectric layer 121 may be the same or different and may be determined depending on the requirements of different situations. In addition, the material of the intermediate dielectric layer 141 includes a material suitable for chemical-mechanical polishing, and is preferably a composite material or an inorganic compound. It is worth mentioning that known molding compounds are usually polymer materials with filler particles, and are not suitable to be used as the material for chemical-mechanical polishing due to particle issues, so the polymer material (the molding compound) cannot be used as the material of the intermediate dielectric layer 141.
The intermediate conductive vias 142 pass through the intermediate dielectric layer 141 and are respectively connected to the second chip pads 112 of the active surfaces 110a of the chips 110. The redistribution structure 150 is disposed on the intermediate dielectric layer 141 and the intermediate conductive vias 142. The conductive bumps 160 are disposed on the redistribution structure 150.
In the embodiment, the base dielectric layer 121 may fill the gap G between two adjacent chips 110. In addition, the base dielectric layer 121 has a material with a low coefficient of thermal expansion. The coefficient of thermal expansion is, for example, less than 10 ppm/° C., and may be more preferably controlled to be less than 5 ppm/° C. Therefore, the coefficient of thermal expansion of the base dielectric layer 121 is similar to the coefficient of thermal expansion of silicon. In other words, the coefficient of thermal expansion of the base dielectric layer 121 is similar to the coefficient of thermal expansion of the chip 110, so that chip warpage caused by the large difference between the coefficient of thermal expansion of the chip 110 and the base dielectric layer 121 in the past can be prevented.
In the embodiment, the distribution density of the first chip pads 111 may be greater than the distribution density of the second chip pads 112. In addition, since the bridging pads 131 of the bridge element 130 are directly bonded to the first chip pads 111 of the active surfaces 110a of the chips 110, the base dielectric layer 121 or the intermediate dielectric layer 141 does not fill the gap between two adjacent bridging pads 131, nor does the base dielectric layer 121 or the intermediate dielectric layer 141 fill the gap between two adjacent first chip pads 111.
In the embodiment, one of the chips 110 may be a central processing unit chip, a logic chip, a graphics processing chip, an input/output chip, a memory chip, a base band chip, a radio frequency (RF) chip, or an integrated circuit chip with a specific function. In other words, the chips 110 may include a combination of the chips of different functional types, so that the electronic package 10 may be used in a chiplet packaging technology, which is similar to system in package (SiP). Since the chips 110 may have different functions, the sizes of the chips 110 may be different. In some embodiments, the chips may be a combination of a central processing unit chip and a logic chip, a combination of a central processing unit chip and an input/output chip, a combination of a graphics processing chip and a memory chip, or a combination of a radio frequency chip and a base band chip. In some embodiments, the chips may also be a combination of two chips with the same function.
In the embodiment, the bridge element 130 may be an active element or a passive element. The material of the bridge element 130 may include an inorganic material (for example, silicon. glass, ceramics) or an organic material. The bridge element 130 may have multiple bridge conductive vias 132, and the chips 110 are electrically connected to the redistribution structure 150 via the bridge conductive vias 132.
In the embodiment, the electronic package 10 may include the circuit carrier 12. The sub-package 100 is installed on the circuit carrier 12. In addition, the electronic package 10 may further include the conductive balls 14. The conductive balls 14 are connected to the circuit carrier 12. In addition, the electronic package 10 may further include the underfill 16. The underfill 16 is filled between the redistribution structure 150 and the circuit carrier 12 and covers the conductive bumps 160.
A manufacturing method of an electronic package according to another embodiment of the disclosure will be described below with reference to
Please refer to
In the embodiment, one of the chips 110 may be a central processing unit chip, a logic chip, a graphics processing chip, an input/output chip, a memory chip, a base band chip, a radio frequency (RF) chip, or an integrated circuit chip with a specific function. In other words, the chips 110 may include a combination of the chips of different functional types, so that the electronic package 10 may be used in a chiplet packaging technology, which is similar to system in package (SiP). Since the chips 110 may have different functions, the sizes of the chips 110 may be different. In some embodiments, the chips may be a combination of a central processing unit chip and a logic chip, a combination of a central processing unit chip and an input/output chip, a combination of a graphics processing chip and a memory chip, or a combination of a radio frequency chip and a base band chip, and may also be a combination of two chips with the same function.
Please refer to
It is worth mentioning that in the known packaging technology, the molding compound is often used to cover the chip, but the coefficient of thermal expansion of the molding compound is much greater than the coefficient of thermal expansion of the chip. Moreover, particles are larger, so it is not easy for the particles to fill the gap, and the molding compound is also prone to stress. However, the disclosure uses a nanoscale material with a coefficient of thermal expansion close to the coefficient of thermal expansion of silicon. The material has smaller molecular particles and improved filling capability, so the material can effectively fill the gap. In the embodiment, the base dielectric layer 121 may fill the gap G between two adjacent chips 110.
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In the embodiment, the chips 110 and the base dielectric layer 121 may be provided by the above steps corresponding to
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In an embodiment, the material of the bridge element 130 may include an inorganic material such as silicon, glass, and ceramics or an organic material. The bridge element 130 may be an active element or a passive element. In addition, in the embodiment, the bridge element 130 is connected to the chips 110 through the first pad pillars 111a. Compared with the prior art, each chip is connected to the bridge element through a redistribution structure (redistribution layer, RDL). The embodiment may further shorten the transmission distance of electrical signals between the chips, and there is less issue of alignment shift. Furthermore, in an embodiment, the size of the first chip pad 111 is not greater than the size of the second chip pad 112. The pitch of two adjacent first chip pads 111 is not greater than the pitch of two adjacent second chip pads 112. and the pitch of two adjacent first chip pads 111 is, for example, less than 10 μm. In addition, the distribution density of the first chip pads 111 may be greater than the distribution density of the second chip pads 112.
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In the embodiment, forming the intermediate conductive vias 142 may include forming multiple through holes in the intermediate dielectric layer 141, and filling a conductive material into the through holes to form the intermediate conductive vias 142.
In the embodiment, the redistribution structure 150 may be formed by adopting a build-up process. The redistribution structure 150 may include the redistribution patterned conductive layers 152, the redistribution dielectric layers 154, and the redistribution conductive vias 156. The redistribution patterned conductive layers 152 are alternately stacked with the redistribution dielectric layers 154. The redistribution conductive vias 156 are respectively connected to the redistribution patterned conductive layers 152. In addition, the under bump metallurgy layers 158 are further formed on the parts of the redistribution patterned conductive layer 152 farthest from the chips 110.
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An electronic package according to another embodiment of the disclosure will be described below with reference to
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The material of the base dielectric layer 121 includes a silicate composite material or a material suitable for chemical-mechanical polishing. The silicate composite material is preferably a silicate nanocomposite material. The material suitable for chemical-mechanical polishing is preferably a composite material or an inorganic compound. It is worth mentioning that known molding compounds are usually polymer materials with filler particles, and are not suitable to be used as the material for chemical-mechanical polishing due to particle issues, so the polymer material (the molding compound) cannot be used as the material of the base dielectric layer 121.
The bridge element 130 partially overlaps with the chips 110 on a projection plane. The bridging pads 131 of the bridge element 130 may be respectively bonded to the first chip pads 111 of the active surfaces 110a of the adjacent chips 110. Specifically, each of the chips 110 has the first pad pillars 111a. The first pad pillars 111a are respectively located on the first chip pads 111 and are surrounded by the base dielectric layer 121. The bridging pads 131 are bonded to the corresponding first chip pads 111 via being respectively bonded to the first pad pillars 111a.
The intermediate dielectric layer 141 is disposed on the chips 110 and the base dielectric layer 121 and surrounds the bridge element 130. The material of the intermediate dielectric layer 141 is a silicate composite material, silicon oxide, derivatives of silicon oxide, silicon oxynitride, silicon carbonitride, polyimide, or benzocyclobutene. The silicate composite material is preferably a silicate nanocomposite material. In an embodiment, the materials of the intermediate dielectric layer 141 and the base dielectric layer 121 may be the same or different and may be determined depending on the requirements of different situations. In addition, the material of the intermediate dielectric layer 141 includes a material suitable for chemical-mechanical polishing, and is preferably a composite material or an inorganic compound. It is worth mentioning that known molding compounds are usually polymer materials with filler particles, and are not suitable to be used as the material for chemical-mechanical polishing due to particle issues, so the polymer material (the molding compound) cannot be used as the material of the intermediate dielectric layer 141.
The intermediate conductive vias 142 pass through the intermediate dielectric layer 141 and are respectively connected to the second chip pads 112 of the active surfaces 110a of the chips 110. Specifically, each of the chips 110 has the second pad pillars 112a. The second pad pillars 112a are respectively located on the second chip pads 112 and are surrounded by the base dielectric layer 121. The intermediate conductive vias 142 are bonded to the corresponding second chip pads 112 via being respectively bonded to the second pad pillars 112a. The redistribution structure 150 is disposed on the intermediate dielectric layer 141 and the intermediate conductive vias 142. The conductive bumps 160 are disposed on the redistribution structure 150.
In the embodiment, the base dielectric layer 121 may fill the gap G between two adjacent chips 110. In addition, the base dielectric layer 121 has a material with a low coefficient of thermal expansion. The coefficient of thermal expansion is, for example, less than 10 ppm/° C., and may be more preferably controlled to be less than 5 ppm/° C. Therefore, the coefficient of thermal expansion of the base dielectric layer 121 is similar to the coefficient of thermal expansion of silicon. In other words, the coefficient of thermal expansion of the base dielectric layer 121 is similar to the coefficient of thermal expansion of the chip 110, so that chip warpage caused by the large difference between the coefficient of thermal expansion of the chip 110 and the base dielectric layer 121 in the past can be prevented.
In the embodiment, the distribution density of the first chip pads 111 may be greater than the distribution density of the second chip pads 112.
In the embodiment, one of the chips 110 may be a central processing unit chip, a logic chip, a graphics processing chip, an input/output chip, a memory chip, a base band chip, a radio frequency (RF) chip, or an integrated circuit chip with a specific function. In other words, the chips 110 may include a combination of the chips of different functional types, so that the electronic package 10 may be used in a chiplet packaging technology, which is similar to system in package (SiP). Since the chips 110 may have different functions, the sizes of the chips 110 may be different. In some embodiments, the chips may be a combination of a central processing unit chip and a logic chip, a combination of a central processing unit chip and an input/output chip, a combination of a graphics processing chip and a memory chip, or a combination of a radio frequency chip and a base band chip. In some embodiments, the chips may also be a combination of two chips with the same function.
In the embodiment, the bridge element 130 may be an active element or a passive element. The material of the bridge element 130 may include an inorganic material (for example, silicon, glass, ceramics) or an organic material. The bridge element 130 may have the bridge conductive vias 132, and the chips 110 are electrically connected to the redistribution structure 150 via the bridge conductive vias 132. In addition, the thickness of the bridge element 130 is less than the thickness of the chips 110.
In the embodiment, the electronic package 10 may include the circuit carrier 12. The sub-package 100 is installed on the circuit carrier 12. In addition, the electronic package 10 may further include the conductive balls 14. The conductive balls 14 are connected to the circuit carrier 12. In addition, the electronic package 10 may further include the underfill 16. The underfill 16 is filled between the redistribution structure 150 and the circuit carrier 12 and covers the conductive bumps 160.
In summary, in the above embodiments, the materials of the base dielectric layer and the intermediate dielectric layer can reduce the interface stress between the material and each chip, especially at the junction of the horizontal and vertical planes of the chip, so that the control of the material and processing is easier to obtain a finished product with high reliability, and direct copper bond also helps to drastically improve transmission performance and power cost performance ratio. The bridging pads of the bridge element are respectively bonded to the first chip pads of the active surfaces of the adjacent chips, which helps to reduce circuit power, increase bridging density, and achieve high-performance computing applications. Under the selected material of the base dielectric layer, when the base dielectric layer is formed by spray coating, spin coating, or deposition, the gap between adjacent chips may be easily filled at low temperature, and the formation of the base dielectric layer is less likely to cause deflection of the chips to maintain alignment precision.
| Number | Date | Country | Kind |
|---|---|---|---|
| 112122519 | Jun 2023 | TW | national |
