Claims
- 1. A voltage regulator for a semiconductor device, comprising:
- a terminal configured to receive a first voltage potential and a second voltage potential;
- an access transistor coupled to said terminal and configured to activate in response to receiving a test mode signal; and
- a connection node coupled to said access transistor and configured to couple to said semiconductor device, wherein said access transistor is interposed between said terminal and said connection node.
- 2. A regulator for an equilibration circuit, comprising:
- a first potential node configured to receive a first voltage source;
- a second potential node configured to receive a second voltage source;
- a common node selectively coupled to said first potential node and to said second potential node;
- a cell plate node configured to receive a cell plate voltage;
- an access device coupled to said common node and to said cell plate node; and
- an output node coupled to said access device and configured to couple to complementary data lines by way of said equilibration circuit.
- 3. The regulator in claim 2, wherein said equilibration circuit has a test mode and a non-test mode, and wherein:
- said common node is coupled to said first potential node during said non-test mode; and
- said common node is selectively coupled to said first potential node and to said second potential node during said test mode.
- 4. A regulator for an equilibration circuit, comprising:
- a first potential node configured to receive a first voltage source;
- a second potential node configured to receive a second voltage source;
- a common node selectively coupled to said first potential node and to said second potential node;
- a cell plate node; and
- a transistor coupled to said common node and to said cell plate node, wherein said transistor is configured to couple to said equilibration circuit and further configured to direct a signal from said cell plate node to said equilibration circuit according to a potential of said common node.
- 5. The regulator in claim 4, wherein said cell plate node is configured to receive a cell plate voltage; and wherein said transistor is configured to direct a signal having a generally constant voltage equal to said cell plate voltage.
RELATED APPLICATION
This application is a continuation of application Ser. No. 09/258,096, filed Feb. 25, 1999; which is a divisional of application Ser. No. 08/855,555, filed May 13, 1997, and issued on Mar. 2, 1999, as U.S. Pat. No. 5,877,993.
US Referenced Citations (16)
Divisions (1)
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855555 |
May 1997 |
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Continuations (1)
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258096 |
Feb 1996 |
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