The disclosed embodiments relate generally to the packaging of semiconductor devices and, more particularly, to a method and system for attaching a die to a substrate using a flame or other heat source.
An integrated circuit (IC) die may be attached, both mechanically and electrically, to a package substrate. The IC die may have an array of bond pads on the die's “front” side, and a solder bump or other lead may be affixed to each of these bond pads. A mating array of lands is disposed on the package substrate, and the die is placed face down on the substrate such that the array of solder bumps extending from the die are aligned with the mating array of lands on the substrate. The solder bumps extending from the IC die are then coupled to their respective lands on the substrate. The package substrate may include multiple layers of conductors (e.g., traces), and these conductors can route electrical signals (running to and from the die) to locations on the package substrate where electrical connections can be established with a next-level component (e.g., a motherboard, a computer system, a circuit board, another IC device, etc.). For example, the substrate circuitry may route all signal lines to a ball-grid array (or, alternatively, a pin-grid array) formed on a lower surface of the package substrate, and this ball- or pin-grid array then electrically couples the packaged IC die to the next-level component, which includes a mating array of terminals (e.g., lands, pin sockets, etc.). The use of an array of solder bumps (or columns, etc.) to couple an IC die to a substrate is often referred to as Controlled Collapse Chip Connect (or C4).
As noted above, an array of solder bumps extends from the front side of the IC die—each of these solder bumps being coupled with a bond pad on the die—and these solder bumps are coupled with a mating array of lands on the package substrate. To couple these solder bumps to the mating array of substrate lands, the assembly (e.g., die and substrate) may be placed in an oven and heated to reflow the solder bumps. For lead-based solder compositions, the reflow temperature may be approximately 225 degrees Celsius, and for lead-free solder compositions the reflow temperature may be approximately 260 degrees Celsius. Upon solidification of the solder bumps, an electrical and mechanical bond is formed between the solder bumps and their mating lands on the package substrate.
During solder reflow, both the die and substrate may be heated to the reflow temperature, which can lead to thermal expansion of these components. However, the coefficient of thermal expansion (CTE) of the IC die may be substantially different than the CTE of the package substrate. For example, a die made of silicon will have a CTE of approximately 3 ppm/° C., whereas an organic substrate may have a CTE of approximately 16 ppm/° C. Upon cool down after reflow, the reflowed solder bumps solidify to form solid interconnects between the die and substrate. At the same time, due to the difference in CTE between the IC die and package substrate, a differential thermal displacement occurs between the die and substrate. Because of this differential thermal displacement, as well as the mechanical stiffness of the solid interconnects that are formed, significant residual stresses may develop. These residual stress may impact both the IC die (e.g., the die's interconnect structure) and the package substrate, as well as the solder interconnects extending between these two components. These residual stresses may, for example, result in die warpage as well as cracking of the die's interconnect structure. The IC die's interconnect structure may be formed from a low-k dielectric material—which generally has lower mechanical strength in comparison to materials having a higher dielectric constant—and an interconnect structure formed from these low-k dielectric materials may be especially sensitive to cracking as a result of the above-described differential thermal displacement.
Illustrated in
Referring to block 110 in
The die 220 may comprise any type of integrated circuit device. In one embodiment, the die 220 comprises a microprocessor, a network processor, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other processing system or device. It should, however, be understood that the disclosed embodiments are not limited to the aforementioned processing devices and, further, that the die 220 may comprise any other type of device (e.g., a wireless communication device, a chip set, a memory device, etc.).
Die 220 includes a “front” side 221 and an opposing “back” side 222. As the reader will appreciate, the labels “front” side and “back” side are arbitrary, and the opposing surfaces 221, 222 of die 220 may be referenced by any other suitable terminology or nomenclature. The die 220 may, in one embodiment, have a layer of metal (or other material) disposed on the back side 222. However, in another embodiment the die back side 222 has no back side metallization. For example, the back side surface may be in the “as is” condition after IC fabrication (e.g., a polished surface).
According to one embodiment, an array of conductive bumps 230 or other conductive leads extends from the front side 221 of die 220, each of the conductive bumps being electrically connected to a bond pad (not shown in figures) on the die. In one embodiment, the conductive bumps 230 comprise solder; however, in other embodiments the conductive bumps may comprise other materials (e.g., copper, aluminum, etc.). The array of conductive bumps 230 mates with a corresponding array of conductive lands (not shown in figures) formed on an upper surface 211 of the substrate 210. When the conductive bumps 230 are connected with their respective lands on substrate 210 (e.g., by a reflow process, as described below), electrical communication can be established between the die and substrate. It should be noted that, in other embodiments, an array of conductive bumps (or other leads) may extend from the substrate 210, and this array of leads mates with a corresponding array of bond pads on the die.
With reference to block 120 in
Referring now to block 130 in
The flame 275 may be produced by any suitable source 270. For example, the flame may be produced by combustion of acetylene, butane, propane, MAPP (methylacetylene propadiene), or other combustible gas. However, in other embodiments, the flame is produced by a combustible liquid (e.g., kerosene) or a combustible solid material. It should also be understood that the disclosed embodiments are not limited to a heat source that produces a flame. For example, in other embodiments, the heat source may comprise super heated air, plasma, or steam.
In one embodiment, the flame 275 (or other heat source) should heat the die 220 to a temperature sufficient to initiate reflow of the solder bumps 230 (or, more generally, to initiate bonding of the die leads to the substrate). According to one embodiment, as a result of heating by flame 275, the temperature at the die front side 221 reaches approximately 225 degrees Celsius, or greater. In a further embodiment, the temperature at the die front side 221 does not exceed approximately 415 degrees Celsius during reflow.
As noted above, the flame 275 (or, more generally, the supplied energy) may be localized at the die 220, which can help to minimize heat transfer to the substrate 210 (and heat shield 250). Heat transfer to, and heating of, the substrate 210 can also be reduced by minimizing the duration of the applied flame (or other energy pulse). Referring to
According to one embodiment, while the die 220 is heated to a temperature sufficient to initiate reflow or bonding, the substrate 210 is not substantially heated (and/or only minimal portions of the substrate 210 are substantially heated). Reduced heating of the substrate 210 results, at least in part, from the use of heat shield 250, from the localized heating of the die 220, and/or from the rapid heating (e.g., short pulse duration) of the die. Because the substrate 210 is not substantially heated, the thermal expansion of this component during die attach is significantly reduced (or, perhaps, eliminated). Thus, the residual stresses—and the resultant damage, such as die cracking or warpage—that can be caused by differential thermal displacement between the die and substrate is minimized.
After reflow and solidification of the solder bump leads 230 (or, more generally, after bonding of the die leads to the substrate), the die 220 is both mechanically and electrically attached to the substrate 210. This is illustrated in
Referring again to
Referring now to
In operation, the pick-and-place machine 490 may position the die 420 on substrate 410, and this machine may also position the heat shield 450 over and/or around the die 420. Either the die 420 or heat shield 450 may first be placed over the substrate 410, and the aperture 455 in heat shield 450 may function to align the die 420 on the substrate. The flame source 470 is also positioned by pick-and-place machine 490 at the desired position relative to the die and substrate. The pick-and-place machine may further be used to place the substrate 410 on holding device 405. With the substrate 410, die 420, heat shield 450, and heat source 470 appropriately positioned, attachment of the die 420 to substrate 410 may be performed using a flame produced by source 470, as described above (see
The foregoing detailed description and accompanying drawings are only illustrative and not restrictive. They have been provided primarily for a clear and comprehensive understanding of the disclosed embodiments and no unnecessary limitations are to be understood therefrom. Numerous additions, deletions, and modifications to the embodiments described herein, as well as alternative arrangements, may be devised by those skilled in the art without departing from the spirit of the disclosed embodiments and the scope of the appended claims.
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Number | Date | Country | |
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20060134830 A1 | Jun 2006 | US |