METHOD FOR FORMING EMBEDDED STRAINED DRAIN/SOURCE REGIONS BASED ON A COMBINED SPACER AND CAVITY ETCH PROCESS

Abstract

By patterning a spacer layer stack and etching a cavity in an in situ etch process, the process complexity, as well as the uniformity, during the formation of embedded strained semiconductor layers may be significantly enhanced. In an initial phase, the spacer layer stack may be patterned on the basis of an anisotropic etch step with a high degree of uniformity, since a selectivity between individual stack layers may not be necessary. Thereafter, a cleaning process may be performed followed by a cavity etch process, wherein a reduced over-etch time during the spacer patterning process significantly contributes to the uniformity of the finally obtained cavities, while the in situ nature of the process also provides a reduced overall process time.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The invention may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:

FIGS. 1 a-1d schematically illustrate cross-sectional views of a semiconductor device at various manufacturing stages during the formation of a recess for receiving a strained silicon/germanium material therein in accordance with conventional process techniques;

FIGS. 2 a-2d schematically illustrate cross-sectional views of a transistor device during the formation of a recess for receiving strained semiconductor material therein on the basis of an in situ patterning process according to illustrative embodiments of the present invention;

FIGS. 3 a-3e schematically illustrate cross-sectional views of a semiconductor device during various manufacturing stages for the formation of different strained semiconductor materials in different transistor types based on an in situ patterning process according to yet other illustrative embodiments of the present invention; and

FIGS. 4 a-4e schematically illustrate cross-sectional views of a semiconductor device during various manufacturing stages for the formation of different strained semiconductor materials based on an in situ patterning process according to yet other illustrative embodiments.

Claims

1. A method, comprising: forming a spacer layer above a semiconductor layer so as to cover a gate electrode of a transistor, said gate electrode being formed above said semiconductor layer and having formed on a top surface thereof a capping layer;performing a sequence of in situ etch processes for etching said spacer layer and said semiconductor layer to form sidewall spacers on sidewalls of said gate electrode and a recess in said semiconductor layer adjacent to said sidewall spacers; andforming a strained semiconductor material in said recess.

2. The method of claim 1, wherein said in situ etch process comprises a first anisotropic etch phase for etching said spacer layer, said first etch phase being stopped upon exposing said semiconductor layer.

3. The method of claim 2, wherein said in situ etch process comprises a cleaning phase after exposing said semiconductor layer, said cleaning phase performed on the basis of an etch chemistry having a high etch selectivity with respect to said sidewall spacers, said capping layer and said exposed semiconductor layer.

4. The method of claim 3, wherein said in situ etch process further comprises a second etch phase for removing material of said exposed semiconductor layer selectively to said sidewall spacer and said capping layer.

5. The method of claim 4, wherein a lateral extension of said recess is controlled by adjusting a degree of anisotropy in said second etch phase on the basis of at least one of an ion flux density and a ratio of reactive halide to a passivation generator.

6. The method of claim 5, wherein said ion flux density is controlled on the basis of at least one of a pressure and a bias power of a plasma ambient used in said second etch phase.

7. The method of claim 2, wherein said first etch phase is performed on the basis of a fluorine and passivation generator containing plasma etch ambient.

8. The method of claim 1, further comprising forming a resist mask for covering a second transistor and exposing said first transistor prior to performing said in situ etch process.

9. The method of claim 8, wherein said resist mask is removed during said in situ etch process.

10. The method of claim 2, wherein forming said spacer layer comprises forming a first sub-layer having a first thickness directly formed on said sidewalls of said gate electrode and on an exposed portion of said semiconductor layer, and forming a second sub-layer having a second thickness on said first sub-layer, said first thickness being less than said second thickness.

11. The method of claim 10, wherein said first thickness ranges from approximately 1-10 nm.

12. A method, comprising: forming a first recess and a first sidewall spacer adjacent to a gate electrode of a first transistor of a first type by a first in situ etch process;forming a second recess and a second sidewall spacer adjacent to a second gate electrode of a second transistor of a second type, said second type being different from said first type;forming a first semiconductor material in said first recess; andforming a second semiconductor material in said second recess.

13. The method of claim 12, wherein said second sidewall spacer and said second recess are formed by a second in situ etch process other than said first in situ etch process.

14. The method of claim 12, wherein said second sidewall spacer and said second recess are formed during said first in situ etch process.

15. The method of claim 14, wherein said first and second semiconductor materials are formed in a common epitaxial growth process.

16. The method of claim 15, further comprising removing said first and second sidewall spacers, forming a spacer layer above said first and second transistors, selectively forming a third sidewall spacer adjacent to said first gate electrode and removing said first semiconductor material from said first recess by a third in situ etch process and forming a third semiconductor material in said first recess.

17. The method of claim 13, wherein said first recess and sidewall spacer are formed prior to forming said second recess and said second sidewall spacer, and said first semiconductor material is formed prior to forming said second recess and said second sidewall spacer.

18. The method of claim 17, wherein forming said second sidewall spacer and said second recess comprises removing a first spacer layer located above said second transistor, said first spacer layer being used for forming said first sidewall spacer and said first recess, and forming a second spacer layer to form said second sidewall spacer during said second in situ etch process.

19. A method, comprising: forming a spacer layer stack including at least two different material layers above a semiconductor layer so as to cover a gate electrode of a transistor, said gate electrode being formed above said semiconductor layer and having formed on a top surface thereof a capping layer;forming a sidewall spacer on a sidewall of said gate electrode by etching said spacer layer stack in a common anisotropic etch process based on a first plasma-based etch ambient;forming a recess adjacent to said gate electrode on the basis of said sidewall spacer; andepitaxially forming a semiconductor material in said recess.

20. The method of claim 19, wherein forming said recess comprises establishing a second plasma-based etch ambient having a higher etch rate for said semiconductor layer compared to said spacer layer stack.

21. The method of claim 20, further comprising cleaning an exposed portion of said semiconductor layer on the basis of a cleaning process prior to establishing said second etch ambient, said cleaning process being based on an etch chemistry that has a reduced etch rate with respect to the exposed semiconductor layer and with respect to the spacer layer stack and said capping layer.

22. The method of claim 21, wherein said first and second etch ambients and said etch chemistry for said cleaning process are established in situ.