Patent Grant
10438923
This invention relates to the field of manufacturing an integrated circuit, in particular, 3D interconnection integration for the manufacturing of an integrated circuit comprising a vertical wall greater than 10 μm.
The current requirements in terms of electronic equipment and systems are primarily linked to the miniaturisation, the improvement in performance, the reduction in electrical consumption and the reduction in costs. All branches of electronics are concerned: communications electronics, automobile electronics and more generally on-board electronics, implantable medical electronics, and of course general public electronics products (IT, game consoles, etc.), to mention only a few examples.
Miniaturisation remains however the main constraint as, on the one hand, it often has positive consequences on the other requirements, and on the other hand, as it makes it possible to respond to the need to integrate an ever-increasing quantity of functions into an ever-decreasing volume. Although up until now the efforts have concerned the developments in technologies for the manufacture of chips on semiconductors, this miniaturisation follows Moore's Law established in 1975 and which stipulates that the number of transistors on a chip doubles every two years. On the other hand, the physical limits will soon be reached by these technologies, and it is becoming necessary to develop new channels that make it possible to go beyond Moore's Law and move into the area of “more than Moore”.
The heterogeneous integration of electronic systems then appears to be a pertinent response in that it makes it possible to choose, for each function of the system, the semi-conductor technology that is best suited, and that it can therefore lead to the integration of a system in a single box of the SiP (System in Package) type that falls in line better with all of the requirements mentioned hereinabove. However, this heterogeneous integration demands the development of new assembly and interconnection technologies suitable for satisfying the needs mentioned hereinabove.
Assembly is a technological method that makes it possible to add and to connect miniature integrated circuits (semiconductor chips) on a host substrate of a system board or of a case. Most solutions for assembling systems are based on the use of micro-soldered wires or on the “flip-chip” technique in order to make the electrical connections between the chips and the substrate. The method of connection via micro-soldered wires is laborious to implement due to the sequential soldering of wires by semi-automated machines. This technique in addition has limits for integration densities linked to the mechanical limits of positioning, as well as for the accessible performances in light of the lengths of the wires processed and the parasites that they introduce. On the other hand, the reliability of the technique of connection via “flip-chip” constitutes a challenge in design and integration due to the defects generated by the thermal stresses.
In addition, producing low-cost and miniaturised radiofrequency (RF) integrated circuits requires the integration of passive elements of high quality, in particular inductive elements such as inductances and transformers. Integrated using conventional technologies, these components are however subjected to stresses that limit their performance. The main limitations come from losses in host substrates (which increase as the resistivity of the substrate decreases, the case in particular with silicon) or in low-thickness metallisations. Likewise, the large surfaces that these integrated components occupy in planar form further increase the losses.
In order to eliminate these disadvantages, it has been proposed to integrate inductive passive elements, such as inductances, above the substrate comprising the active elements of the chip. This technology is known to those skilled in the art under the designation “above-IC”. In order to limit the interactions between the substrate and the inductive passive electronic components for which a high level of quality is sought, it is known to carry out a metal screen on said substrate and to form on said screen thick layers of dielectric material whereon these passive components are carried out. In order to connect the components, for example active, optionally integrated on the surface of the substrate, and the inductive passive components formed above this substrate on the thick layer of the dielectric material, it is necessary to carry out the metallised interconnections passing through the thick layer of dielectric material.
In reference to
Given that the horizontal surfaces and the vertical surface of the metal interconnection are formed simultaneously, 3D interconnection is spoken of in opposition to a 2.5D interconnection for which the various surfaces of the metal interconnection are formed successively.
In a known manner, the metallisation coating 3 is, deposited onto the horizontal substrate 1 and onto the dielectric layer 2 by a physical deposition method. In practice, it is difficult to carry out a deposit on the vertical flank 2b of the dielectric layer 2 given that the metal deposit is applied vertically. To this effect, it is known to apply an initiator, also called a “seed layer enhancement”, on the vertical flank 2b in order to deposit a nanometric layer of metal 3b which makes it possible to improve the deposit of the metallisation coating 3. The preparation of the vertical flank 2b is long and expensive due to the application of the initiator. Furthermore, if the initiator is not applied with great care or if the initiator does not evenly adhere to the various materials present on the substrate, the metallisation coating 3 is applied discontinuously which has as a disadvantage of generating open electric circuits preventing the formation of the metal interconnection 5.
In prior art, it is known from patent application WO 99/14404 A1 a method for forming a coating by metal deposit using a moderate heat treatment. This application aims to anneal a metal which has been deposited in order to reorganise its internal structure and limit is mechanical weaknesses. U.S. Patent application 2003/006493 A1 relates to a method for manufacturing an electronic component wherein electronic chips are superimposed vertically as a pyramid. US application 2009/200686 A1 relates to an electrical connection structure which is suitable for covering a block of elastomer. US application 2004/140549 A1 relates to a method for the electrical connection of a component by depositing metal particles, in particular, via an “inkjet” method. US application 2006/192299 A1 relates to a method for manufacturing a piece of electronic equipment comprising a connection extending from a lower plane to a higher plane.
The invention therefore has for purpose to overcome these disadvantages by proposing a method for carrying out a 3D interconnection which is simple to implement, reliable and of which the cost is low in order to allow for the integration, on the one hand, of miniaturised and high-performance electronic systems without using micro-soldered wires or microwelds and, on the other hand, miniature and high-quality inductive passive 3D components.
To this effect, the invention relates to a method for integrating at least one interconnection for the manufacture of an integrated circuit comprising:
The method is remarkable in that the first wall is vertically angled and has a rising slope from the horizontal surface of the substrate to the high point of said insulating body, with the first wall comprising a horizontal component and a vertical component greater than 10 μm, the ratio of inclination of the horizontal component over the vertical component is between 0.001 and 1.35.
Thanks to such a method, the electrical structure can be applied quickly and practically without the preliminary application of an initiator as in prior art, which procures a savings in time and a reduction in cost. The range of the inclination ratio of the first wall makes it possible, on the one hand, to limit the surface occupied by the interconnection in order to allow for optimum miniaturisation and, on the other hand, to facilitate the electrolytic growth of the electrical structure and/or the depositing of a bond coat on a substantially vertical surface. Thanks to the invention, the structure obtained is one-piece, of quality and fast to form.
Incidentally, it is known from patent application WO2012/045981 a method wherein an electrical structure is formed with a vertical flank, i.e. on a wall not vertically angled, or a flank with undercuts, i.e., of which the slope falls starting from the substrate and which requires the use of seals.
Such an angle of inclination makes it possible to distinguish “natural” slopes from the layers of silicon which are carried out by lithography and wet etching. Such a slope has a high inclination and depends on the crystalline plane of the silicon.
Preferably, the ratio of inclination of the horizontal component over the vertical component is between 0.01 and 1.
Such a first wall makes it possible to facilitate the electrolytic growth of the electrical structure and/or the depositing of a bond coat onto a substantially vertical surface. Thanks to the invention, the structure obtained is one-piece and is quick to form.
Advantageously, the inclination ratio provides a compromise between the surface occupied by the interconnection and the conformity of the latter.
The insulating body can be formed from an insulating material or include a body comprised of conductor and/or semi-conductor and/or magnetic and/or dielectric material which is insulated, i.e., covered with an insulating layer.
According to an aspect, the insulating body is comprised of insulating material.
According to another aspect of the invention, the insulating body comprises a body comprised of conductor and/or semi-conductor and/or magnetic and/or dielectric material, covered by an insulating layer. As such, an insulating body can advantageously be formed by covering a body comprised of a conductor and/or semiconductor and/or magnetic and/or dielectric material by an insulating layer, which makes it possible to electrically insulate the interconnections from said body.
Preferably, said body comprised of a conductor and/or semi-conductor and/or magnetic and/or dielectric material has a first vertical wall or undercuts, with the insulating layer covering the first vertical wall or with undercuts making it possible to obtain the inclination of the first wall of the insulating body.
Advantageously, the insulating layer makes it possible to obtain the inclination ratio sought while the body comprised of a conductor and/or semiconductor and/or magnetic and/or dielectric material comprises a vertical wall or undercuts. In another advantageous manner, the insulating layer makes it possible to provide the physical continuity between the surface of the substrate and said body, which makes it possible to provide the electrical continuity of the bond coat and/or of the electrical structure. The method can as such be applied in many different configurations.
According to another aspect of the invention, said body comprised of conductor and/or semi-conductor and/or magnetic and/or dielectric material has a first wall with undercuts, with the insulating layer covering the first wall with undercuts making it possible to electrically insulate the interconnections from said corps. Advantageously, the insulating layer makes it possible to provide the physical continuity between the surface of the substrate and said body, which makes it possible to provide the electrical continuity of the bond coat and/or of the one-piece electrical structure.
According to a preferred aspect, the first wall of the insulating body is planar which makes it possible to improve the adherence of the conductive layers and to facilitate the method of structuring electrical structures. Preferably, the body has a section in the shape of a trapeze.
According to another aspect, the first wall of the insulating body is curved which makes it possible to improve the electrical and mechanical performance of the electrical structures. Preferably, the insulating body has a section in the shape of a half-ellipse.
According to another aspect, the first wall of the insulating body forms a staircase comprising a plurality of horizontal portions and a plurality of vertical portions.
According to another aspect, the first wall of the insulating body is comprised of a flat portion and of a curved portion which makes it possible to improve the electrical and mechanical performance of the electrical structures. Preferably, the insulating body has a section in the shape of a hysteresis.
Preferably, the first wall is vertically angled and has a rising slope from the horizontal surface of the substrate to the high point of said insulating body, with the first wall comprising a horizontal component and a vertical component greater than 10 μm, the ratio of inclination of the horizontal component over the vertical component is between 0.001 and 1.35, the insulating body comprising a body comprised of conductor and/or semi-conductor and/or magnetic and/or dielectric material, having a vertical wall or with undercuts, which is covered by an insulating layer, the insulating layer covering the vertical wall or with undercuts making it possible to obtain the inclination of the first wall of the insulating body, the method comprises:
As such, the step of applying the insulating layer makes it possible to adjust the inclination of the slope in a practical manner in order to favour the depositing of the electrical structure.
Preferably, as the insulating layer is photosensitive, the method comprises a step of insulating the insulating layer through a mask in such a way as to precisely control the angle of the first wall of the insulating body. As such, even if the step of applying the insulating layer is not precise enough, the step of insulating makes it possible to precisely control the inclination.
Preferably, the mask comprises a zone, configured to insulate the first wall from the insulating body, which comprises a plurality of patterns of variable lengths and widths in such a way as to control the inclination thereof. In other words, thanks to the mask, the insulation is heterogeneous and makes it possible to remove various thicknesses of insulating layer in order as such to control the slope.
More preferably, said zone comprises a plurality of patterns of which the width is decreasing along an axis directed from the top of the first wall of the insulating body downwards. As such, this makes it possible to increase the inclination of the slope formed during the application of the insulating layer.
Preferably, the mask comprises a plurality of different zones in such a way as to individually control the angle of several first walls. It is as such possible to carry out an integrated circuit adapted to the needs.
Preferably, the patterns are positioned parallel to the slope of the first wall of the insulating body in such a way as to create a determined insulation at a predetermined slope height. The insulation is homogenous at a determined height in such a way as to form an even inclination.
According to a preferred aspect, the openings in the insulating layer are carried out during the step of insulating, which accelerates the method of manufacture.
Preferably, the method comprises a step of depositing a layer of resin onto the insulating layer in such a way as to form a mould that limits the extension of the electrically conductive material during the step of depositing the electrical structure. As such, the mould makes it possible to structure the interconnection formed.
Preferably, said mould has a thickness between 10 and 150 μm and has a width/thickness resolution between 1 for 0.5 and 1 for 50, preferably, between 1 for 2 and 1 for 25.
Preferably, the substrate comprising a cavity wherein is positioned the insulating body, said mould extends at least partially into said cavity adjacently to said insulating body. As such, the interconnection fills only a single portion of the cavity, which increases the flexibility.
Preferably, the horizontal component is between 0.1 and 150 μm, preferably, between 1 and 75 μm.
Preferably, the method comprises a step of depositing a bond coat onto said substrate and said vertical surface prior to the step of depositing the electrical structure and/or the layer of resin forming the mould. A bond coat is also used as a base for the electrolytic growth of the electrical structure.
Preferably, the method comprises a step of depositing a plurality of one-piece electrical structures made of an electrically conductive material over a plurality of horizontal surfaces and a plurality of first walls of insulating bodies.
Preferably, the first walls extend in different planes in such a way as to form three-dimensional interconnections.
The invention also relates to an integrated circuit comprising:
The circuit is remarkable in that the first wall is vertically angled and has a rising slope from the horizontal surface of the substrate to the high point of said insulating body, with the first wall comprising a horizontal component and a vertical component greater than 10 μm, the ratio of inclination of the horizontal component over the vertical component is between 0.001 and 1.35, preferably, between 0.01 and 1.
Preferably, the integrated circuit comprises a plurality of a one-piece electrical structure.
Preferably, the insulating body comprises a body comprised of conductor and/or semi-conductor and/or magnetic and/or dielectric material covered with an insulating layer, also called a repassivation layer.
The invention shall be better understood when reading the following description, provided solely by way of example, and in reference to the annexed drawings wherein:
Note that the figures show the invention in a detailed manner in order to implement the invention, said figures able of course to be used to better define the invention where applicable.
The method according to the invention allows for the integration of inductive passive 3D components onto a substrate as well as 3D interconnections that connect one or several active or passive components to a substrate.
A method for manufacturing a monolithic integrated circuit according to a first embodiment of the invention shall now be presented in reference to
Such interconnections are configured in particular for establishing electrical connections between different regions of an active or conductive zone of the substrate, between different active or conductive zones of the substrate or between active or conductive zones of several integrated circuits stacked and/or dispersed over the surface of the substrate. They can also form interconnection elements that can allow for the electrical connection of a discrete electronic component, i.e. not integrated into the monolithic circuit.
In reference to
In a first step, in reference to
In this example, still in reference to
The second right angled wall 7d is decreasing in the system of coordinates X, Y but it however has a rising slope from the upper surface 1a of the substrate 1 to the upper horizontal surface 7c of the insulating body 7. The slopes are, in this example, symmetrical but it goes without saying that they could be different.
The inclination ratio of the horizontal component Cx over the vertical component Cy is between 0.001 and 1.35, preferably, between 0.01 and 1.
In this embodiment, the angled walls 7b, 7d are flat but it goes without saying that they could be different, in particular, curved as will be presented in what follows.
In reference to
Advantageously, given that the walls 7b, 7d of the insulating body 7 are angled, the walls 8b, 8d of the bond coat 8 are also angled as shown in
The bond coat 8, also called electrolytic growth layer, is formed in this example by the depositing of a metal material, in particular of an electrically conductive or semi-conductive material, able to promote the adhesion of the material comprising the electrical structure by electrolytic growth. By way of example, the bond coat 8 is a thin layer, with a thickness between 1 nm and 2 μm made of titanium, chromium, tantalum, tungsten, aluminium, gold, copper, silver, nickel or a metal alloy such as and not limited to titanium/tungsten, nickel/boron or a metal/semi-conductor alloy such as and not limited to aluminium/silicon or other. Advantageously, this layer is carried out as a successive deposit of two or of several layers of metal, such as for example of titanium/copper, titanium/gold, chromium/gold, Titanium/Nickel/gold or other possible configurations.
The bond coat 8 is deposited by a conventional method of “vertical” depositing of a metal material known to those skilled in the art, in particular par cathode pulverisation, by thermal evaporation or by electrografting. During such a depositing, all of the surfaces of the substrate 1 and of the insulating body 7 are cleared and are as such easily reached by the metal material constituting the bond coat 8, and as such these surfaces are covered homogeneously and continuously.
Advantageously, it is not necessary to use an initiator, which reduces the number of technological steps as well as the costs and the time for manufacturing, limits the risk of defects and responds to the various weak points mentioned hereinabove.
In reference to
In this example, the layers of resin 4a, 4e are respectively deposited on the left lower horizontal portion 8a and the right lower horizontal portion 8e as shown in
Each layer of resin 4a, 4e having the structure sought is obtained by any suitable method known to those skilled in the art, in particular by lithography or inkjet printing. In this example, each layer of resin 4a, 4e has a substantial thickness, in particular a thickness between 10 μm and 500 μm. In the example shown, it has a thickness equal to about 150 μm. The resin forming the layer of resin 4a, 4e is in particular a photosensitive resin having a resolution between 1 for 0.5 and 1 for 50, preferably between 1 for 2 and 1 for 25. In the example shown, the resin has a resolution of 1 for 15, i.e. the smallest width of the segments that can be obtained by photolithography is 10 μm thick. It is as such possible to form patterns with a width greater than or equal to 10 μm for a resin thickness of 150 μm.
Advantageously, the mould formed by the layers of resin makes it possible to structure different types of interconnections. So as to allow for the housing of a body 70 (in particular one or several chips) which is thick and which cannot be thinned, it is advantageous to provide a cavity in the substrate for the mounting of said body 70. This makes it possible to limit the overall thickness of the integrated circuit. Thanks to the invention, it is possible to carry out interconnections in the cavity following the mounting of said body 70, in particular, in the adjacent cavities C1, C2 formed between the body 70 and the raised edge of the substrate 70 as shown in
According to a first embodiment, in reference to
According to a second embodiment, in reference to
Such interconnections 9-1, 9-2 make it possible to stack a substantial number of electronic chips in a cavity of the substrate while still having an integrated circuit of low thickness.
In reference to
Advantageously, given that the walls 8b, 8d of the bond coat 8 are angled, the electrolytic growth is improved, which improves the control of the thicknesses.
The electrical structure 9 is made from an electrically conductive material, and able to be deposited by electrolysis. It is advantageously made of copper. Alternatively, it is made from gold or all other metals that allow for an electrolytic depositing.
The electrical structure 9 forms for example all or a portion of an electronic component, in particular of a passive electronic component such as an inductance, a transformer, an antenna, etc. It can also form an interconnection line, configured to connect together different regions of the substrate 1 and/or different regions of the substrate 1 and of the insulating body and/or different regions of the insulating body. The thickness of the electrical structure 9 depends on its electronic function. It also depends on the application of the circuit. By way of example, electrical structures 9 will be provided with higher thicknesses in a power amplifier circuit than in a digital circuit. For the purposes of information, the thickness of an electrical structure 9 is for example between 1 μm and 150 μm. After having formed the electrical structure 9, (
Finally, still in reference to
An integrated circuit such as shown in
A second embodiment of the invention is described in reference to
In reference to
Similar to flat angled walls, the curved angled walls 7f, 7g facilitate the depositing of the bond coat 8 as well as of the electrical structure 9′.
Advantageously, the electrical structure 9 has the shape of a spire. To this effect, as shown in
Preferably, in reference to
Preferably, the insulating body 7 located between the substrate 1 and the bond coat 8 is removed in order to improve the performance of the inductances and of the inductive components at high frequencies, since this body has dielectric losses that are more substantial than those of air 90, 90′.
The method according to the invention makes it possible to obtain, with a reduced number of technological steps, inductive passive components of high quality. Furthermore, it makes it possible to form electrical interconnections 90″ comprising an angled wall 9f′ that connects various active components to a substrate 1 as shown in
A third embodiment of the invention is described in reference to
In the two preceding embodiments, the insulating body 7 was comprised of insulating material. In this third embodiment, the insulating body 7 comprises a body comprised of conductor and/or semi-conductor and/or magnetic and/or dielectric material 70 which is covered by an insulating layer 71 also called passivation or repassivation layer. The body comprised of conductor and/or semi-conductor and/or magnetic and/or dielectric material 70 comprises at least one first wall 70b extending from the horizontal surface of the substrate 1 to a high point of said body 70.
As shown in
Preferably, the insulating layer 71 is deposited by vacuum evaporation, by pulverisation or by spray in order to obtain an insulating layer of thickness that is relatively compliant on all of the walls (not too thin, not too thick).
The insulating layer 71 is deposited onto all of the walls (horizontal, vertical, angled, etc.) of the body 70 as well as on the substrate 1 in such a way as to fully insulate the body 70 comprised of conductor and/or semi-conductor and/or magnetic and/or dielectric material 70. A passivation/insulating of the body 70, in particular of the upper face, makes it possible to separate the interconnections from the connections present on the body 70 as well as from the latter, which reduced the interactions by electromagnetic coupling and consequently, electrical losses. In addition, this makes it possible to route interconnections above the connection pads of the body 70, which makes it possible to increase the routing density and to reduce the number of layers of metallisations required for the interconnection of high-density input-output systems. The cost of manufacturing is then reduced.
In this example, in reference to
In order to control the inclination of the slope, the insulating layer 71 is deposited preferably by spray coating.
Preferably and according to the needs of the application, the method comprises a step of precise adjustment of the inclination of the slope using a technique of photolithography. In reference to
In practice, the thickness of the insulating layer 7, which is removed, is proportional to the dose of insulating received. In this embodiment, the mask 100 comprises a zone 101, configured to insulate the slope from the insulating layer 7, which comprises a plurality of patterns 103 of variable lengths and widths in such a way as to control the inclination of said slope precisely. Preferably, the zone 101 comprises a plurality of patterns 103 of which the width is decreasing according to the axis oriented from the top of the slope towards the bottom of the slope as shown in
After insulating, as shown in
This structuring can be carried out using one or several masks 100 and using one or several steps of insulating.
Very advantageously, the inclination of each slope can as such be adjusted individually, which increases the routing possibilities.
In reference to
The method according to the invention authorises by default the carrying out of multi-level interconnections 9 onto a substrate comprising a plurality of insulating bodies 7 dispersed and/or stacked vertically on the surface thereof (
Thanks to the method according to the invention, an increase in the manufacturing output is obtained and a substantial reduction in costs. The depositing in a single step of the electrical structure without preparation of the flanks makes it possible to obtain a base of continuous electrolytic growth over several levels in a fast manner and at least cost.
The method according to the invention as such allows for the manufacturing of integrated circuits, comprising active and passive components, forming one-piece conductive structures, in particular 3D interconnections and inductive passive components having very low losses. It makes it possible to, design and carry out RF and micro-wave power amplifiers of small size that have a high-power output and that therefore have a reduced consumption. It can also make it possible to implement an antenna directly on the integrated circuit. This method can also be used advantageously to assemble and interconnect on the “Wafer-Level-Packaging” scale miniaturised systems of the “System-in-Package” type. The use of the method is not limited to semiconductor substrates, it can be applied to other types of substrates such as glasses, alumina, polymers, PCB, etc. as well as on the flexible substrates (PET, Polyimide, etc.).
| Number | Date | Country | Kind |
|---|---|---|---|
| 15 58544 | Sep 2015 | FR | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/EP2016/071674 | 9/14/2016 | WO | 00 |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2017/046153 | 3/23/2017 | WO | A |
| Number | Name | Date | Kind |
|---|---|---|---|
| 6969916 | Shizuno | Nov 2005 | B2 |
| 8735205 | Haba | May 2014 | B2 |
| 20030006493 | Shimoishizaka et al. | Jan 2003 | A1 |
| 20040140549 | Miyagawa | Jul 2004 | A1 |
| 20040251525 | Zilber | Dec 2004 | A1 |
| 20050146005 | Shimoishizaka | Jul 2005 | A1 |
| 20060192299 | Hashimoto | Aug 2006 | A1 |
| 20080046080 | Vanden Bulcke | Feb 2008 | A1 |
| 20080099907 | Oganesian | May 2008 | A1 |
| 20090200686 | Tsang et al. | Aug 2009 | A1 |
| 20130065390 | Haba | Mar 2013 | A1 |
| 20160013159 | Kwon | Jan 2016 | A1 |
| Number | Date | Country |
|---|---|---|
| WO 9914404 | Mar 1999 | WO |
| Entry |
|---|
| Search Report from French Intellectual Property Office on corresponding FR application (FR1558544) dated Jun. 6, 2016. |
| International Search Report and Written Opinion on corresponding PCT application (PCT/EP2016/071674) from International Searching Authority (EPO) dated Feb. 28, 2017. |
| Number | Date | Country | |
|---|---|---|---|
| 20180254258 A1 | Sep 2018 | US |
