The subject matter herein generally relates to a circuit technology, especially relates to a circuit board and a method of manufacturing the circuit board.
With the development of the electronic products, sizes of the electronic products are becoming smaller. Correspondingly, an important element in the electronic products, the circuit board needs to be smaller. So that connecting pads and wiring spacings of the circuit board also need to become smaller, which makes coating of solder paste with precisions become more difficult.
Therefore, there is room for improvement within the art.
Implementations of the present disclosure will now be described, by way of embodiments, with reference to the attached figures.
It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein can be practiced without these specific details. In other instances, methods, procedures, and components have not been described in detail so as not to obscure the related relevant feature being described. Also, the description is not to be considered as limiting the scope of the embodiments described herein. The drawings are not necessarily to scale, and the proportions of certain parts may be exaggerated to better illustrate details and features of the present disclosure.
The term “comprising,” when utilized, means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series, and the like.
At block 21, referring to
The carrier 11 may be made of a material selected from a group consisting of metal, hard resin, glass, and any combination thereof. For example, the carrier 11 may be a metal plate or a glass plate.
At block 22, referring to
At block 23, referring to
Preferably, the soler 20 may fully fill in the first opening 161, and a surface of the soler 20 facing away from the carrier 11 may be flush with a surface of the resin layer 15 facing away from the carrier 11.
The solder 20 may be, but is not limited to, solder paste or copper paster.
At block 24, referring to
Preferably, the second opening 163 may be formed with a center of the solder 20 as a center point to surround the solder 20.
At block 25, referring to
The first wiring layer 31 may further include at least one signal line 311 spaced from the connecting pad 313.
The circuit substrate 30 may be a single-layer circuit board, a double-layer circuit board, or a multi-layer circuit board. In at least one embodiment, referring to FIG. 7, the circuit substrate 30 is a double-layer circuit board. Specifically, the circuit substrate 30 may further include a dielectric film 33 and a second wiring layer 35 stacked and spaced along the first direction X. The second wiring layer 35 is electrically connected to the first wiring layer 31, and the dielectric film 33 is interposed between the first wiring layer 31 and the second wiring layer 35.
At block 26, referring to
In at least one embodiment, a height of the solder 20 is greater than a depth of the groove 301, thereby facilitating an electrical connection between the solder 20 and external electronic components (not shown).
The first portion of the resin layer 15 received in the groove 301 may be removed by, but not limited to, laser ablation followed by plasma removal of scum.
At block 27, referring to
In at least one embodiment, the block 27 may be omitted. The second portion of the resin layer 15 may be used as a protective layer of the circuit board 100a (shown in
In at least one embodiment, before the block 25, the method may further include roughening the surface of the soler 20 facing away from the carrier 11, so as to increase an adhesive property between a connecting pad 313 subsequently formed and the solder 20.
At block 251, referring to
The patterned first dielectric layer 331 may further include at least one wiring opening 334 spaced from the third opening 332.
At block 252, referring to
The first wiring layer 31 may include at least one signal line 311 embedded in the at least one wiring opening 334.
At block 253, referring to
In at least one embodiment, the second wiring layer 35 may electrically connected to the connecting pad 313 through a conductive via 36.
In at least one embodiment, a depth of the first opening 161 may be less than or equal to a depth of the second opening 163. The formation of the solder 20 and the formation of the surrounding portion 17 are not limited to the above-mentioned method. In the illustrated embodiment, it is preferable that the depth of the first opening 161 is greater than the depth of the second opening 163.
Depending on the embodiment, certain of the steps of methods described may be removed, others may be added, and the sequence of steps may be altered. It is also to be understood that the description and the claims drawn to a method may include some indication in reference to certain steps. However, the indication used is only to be viewed for identification purposes and not as a suggestion as to an order for the steps.
In at least one embodiment, a height of the solder 20 may preferably be greater than a depth of the groove 301, thereby facilitating an electrical connection between the solder 20 and external electronic components (not shown). In at least one embodiment, the height of the solder 20 may be less than or equal to the depth of the groove 301.
A surface of the solder 20 facing the connecting pad 313 may be roughened, which is beneficial to increase an adhesive property between a connecting pad 313 subsequently formed and the solder 20.
In at least one embodiment, referring to
A surface of the resin layer 18 facing away from the first wiring layer 31 may be flush with a surface of the surrounding portion 17 facing away from the first wiring layer 31.
The circuit substrate 30 may be a single-layer circuit board, a double-layer circuit board, or a multi-layer circuit board. In at least one embodiment, the circuit substrate 30 is a double-layer circuit board. Specifically, the circuit substrate 30 may further include a dielectric film 33 and a second wiring layer 35. The first wiring layer 31 is embedded in the dielectric film 33 from a first side of the dielectric film 33. The second wiring layer 35 is formed on a second side of the dielectric film 33 facing away from the first wiring layer 31, and is electrically connected to the first wiring layer 31.
In at least one embodiment, the second wiring layer 35 may electrically connected to the connecting pad 313 through a conductive via 36.
In the above method of for manufacturing a circuit board and the above circuit board, the solder 20 may be accurately arranged in the groove 301, which is beneficial to improve a stability of the connection between the solder 20 and the connecting pad 313. At the same time, the solder 20 is spaced from the surrounding portion 17, which provide a sufficient space for the solder 20 when the solder 20 is melted, thereby reducing a rish of the solder 20 overflowing and contacting other wirings.
It is to be understood, even though information and advantages of the present embodiments have been set forth in the foregoing description, together with details of the structures and functions of the present embodiments, the disclosure is illustrative only; changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the present embodiments to the full extent indicated by the plain meaning of the terms in which the appended claims are expressed.
Number | Date | Country | Kind |
---|---|---|---|
202110536265.3 | May 2021 | CN | national |
Number | Name | Date | Kind |
---|---|---|---|
7093356 | Imafuji | Aug 2006 | B2 |
8797757 | Kaneko | Aug 2014 | B2 |
8929092 | Yoshioka | Jan 2015 | B2 |
20160225706 | Cho et al. | Aug 2016 | A1 |
Number | Date | Country |
---|---|---|
102076180 | May 2011 | CN |
Number | Date | Country | |
---|---|---|---|
20220369475 A1 | Nov 2022 | US |