Patent Application
20100317136
1. Field of the Invention
The present invention relates to a method for producing a semiconductor light emitting device, a method for producing a semiconductor device, a method for producing a device, a method for growing a nitride type III-V group compound semiconductor layer, a method for growing a semiconductor layer, and a method for growing a layer. In particular, the present invention relates to for example those suitable for producing a semiconductor laser, a light emitting diode, or an electron traveling device using a nitride type III-V group compound semiconductor.
2. Description of the Related Art
Nitride type III-V group compound semiconductors such as GaN, AlGaN, GaInN, and AlGaInN feature in a large band gap Eg and direct transition semiconductor materials in comparison with arsenic type III-V group compound semiconductors such as AlGaInAs and phosphorous type III-V group compound semiconductors such as AlGaInP. Thus, these nitride type III-V group compound semiconductors has attracted considerable attention as materials of semiconductor lasers that can emit short wavelength light ranging from ultraviolet ray to green and materials of semiconductor light emitting devices such as light emitting diodes (LEDs) that can cover a wide range of light emitting wavelength from ultraviolet ray to red and white. These materials are expected for wide applications such as high density optical discs, full color displays, environmental and medical fields.
In addition, these nitride type III-V group compound semiconductors for example GaN feature in a large saturation speed in a high electric field, a high temperature operation of for example up to around 400° C., and continuous crystal growth for a semiconductor layer and an insulation layer using AlN in for example a metal-insulator-semiconductor (MIS) structure. Thus, these nitride type III-V group compound semiconductors are expected for materials that compose radio frequency electronic devices that can operate at high temperature and with a large output.
In addition, these nitride type III-V group compound semiconductors have the following advantages.
(1) Since they have higher thermal conductivities than GaAs type semiconductors, they are suitable for devices that operate at high temperatures and with large outputs.
(2) Since they are chemically stable and hard, they have high reliability.
(3) They are compound semiconductor materials that less contaminate environment. In other words, AlGaInN type semiconductors do not contain environmental pollutants and poisonous substances. In reality, they do not contain arsenic (As) for AlGaAs type semiconductors, cadmium (Cd) for ZnCdSSe type semiconductors, and a material arsine (AsH3).
However, proper substrate materials for devices using nitride type III-V group compound semiconductors that have high reliability are not known.
To obtain high quality crystals, substrate materials for nitride type III-V group compound semiconductors have the following problems and conditions to be solved and satisfied.
(1) Structural materials GaN, AlGaN, and GaInN of the nitride type III-V group compound semiconductors are of full distortion type of which there are different lattice constants. Thus, compositions, thicknesses, and so forth of nitride type III-V group compound semiconductors and substrates should be designed so that they are free from cracks and obtain good crystal films.
(2) A high quality substrate that can lattice-match GaN has not been developed. Like a high quality GaAs substrate that can lattice-match a GaAs type semiconductor and a GaInP type semiconductor and a high quality InP substrate that can lattice-match a GaInAs type semiconductor, for example a high quality GaN substrate is under development. A SiC substrate having a small difference of lattice constants is expensive. In addition, it is difficult to produce a SiC substrate having a large diameter. Since a tensile distortion takes place in a crystal film, it easily cracks. In addition, there is no substrate that can lattice-match GaN.
(3) Necessary conditions of substrate materials for nitride type III-V group compound semiconductors are a high crystal growth temperature of around 1000° C. and no deterioration and no corrosion of V group materials in an ammonium atmosphere.
In consideration of the foregoing reasons, as a substrate of a nitride type III-V group compound semiconductor, a sapphire substrate is often used.
A sapphire substrate is stable at crystal growth temperature of a nitride type III-V group compound semiconductor. Thus, as an advantage, high quality substrates of two inches or three inches can be stably supplied. However, lattice-mismatch of a sapphire substrate to GaN is large (around 13%). Thus, a buffer layer made of GaN or AlN is grown on the sapphire substrate at low temperature. Above the buffer layer, a nitride type III-V group compound semiconductor is grown. As a result, although a single crystal of a nitride type III-V group compound semiconductor can be grown, the defect density is as large as 108 to 109 (cm−2) due to lattice mismatching. Thus, when the nitride type III-V group compound semiconductor is used for a semiconductor laser, it does not have reliability for a long time.
In addition, (1) since a sapphire substrate does not have cleavage, an end plane of a laser cannot be stably formed with specular property. (2) Since sapphire is insulative, it is necessary to take out a p-side electrode and an n-side electrode from the upper surface of the substrate. (3) When a crystal growth film is thick, due to the difference of thermal expansion coefficients of a nitride type III-V group compound semiconductor and sapphire, the substrate largely skews at room temperature. As a result, the device forming process is adversely affected.
To obtain a high quality semiconductor crystal that is grown on a substrate such as a sapphire substrate whose lattice constant is different from the semiconductor crystal, a method using epitaxial lateral overgrowth (ELO) is known. In the ELO, high crystal quality regions (lateral growth regions) and low crystal quality regions (or high defect density regions) (on seed crystals, their boundaries, meeting portions, and so forth) periodically take place. However, when the size of an active region (for example, a light emitting region of a light emitting device or an electron traveling region of an electron traveling device) is not large, the period of the ELO can be greater than the interval of stripes of a semiconductor laser and the interval of emitter region region/collector region (or source region/drain region) of a transistor. For example, the period of the ELO is 10 to 20 μm, whereas the size of the active region of a device is around several μm. Thus, the active region can be designed in the high quality region.
When a device is formed on a sapphire substrate by the ELO, in addition to the foregoing problem of bad cleavage due to characteristics of sapphire, there are for example the following problems.
(1) Since the number of steps necessary for the ELO is large, the yield decreases.
(2) Since the crystal film thickness increases for the ELO, the substrate largely skews due to thermal stress. As a result, the controllabilities of the crystal growing step and wafer process deteriorate.
(3) The device size is restricted. A device such as an LED, a photo detector (PD), or an integrated circuit device that has an active region greater than the ELO period (namely, one side of the active region is for example several hundred μm), since all the device region cannot be formed as high crystal quality regions, the effect of the ELO cannot be fully obtained.
Although the foregoing problems would be solved when a high quality GaN substrate could be obtained. However, so far, a high quality GaN substrate having a large diameter has not been obtained. This is because a good seed crystal cannot be obtained from GaN by hydride vapor phase epitaxy (HVPE), which is high temperature (high pressure) growth. Thus, single crystal growth cannot be stably performed. As a result, a high quality substrate cannot be easily produced.
Japanese Patent Laid-Open Publication No. 2001-102307 has proposed a method for producing a single crystal GaN substrate that allows the foregoing problems to be solved. According to the related art, after a GaN seed substrate having a high defect density is formed, a three-dimensional facet (referred to as core) is formed on a part thereof. A crystal is grown so that the facet is not closed. Crystal dislocations are gathered around the core portion. As a result, a wide substrate having high quality is produced.
However, the technology that has been disclosed in Japanese Patent Laid-Open Publication No. 2001-102307 causes the through-dislocations to be gathered around a region of a growth layer so as to decease the through-dislocations of the other regions. Thus, a low defect density region (core) and high defect density regions coexist in the obtained single crystal GaN substrate. In addition, the location of the high defect density regions cannot be controlled. Instead, the high defect density regions randomly take place. Thus, when a semiconductor device for example a semiconductor laser is produced, a nitride type III-V group compound semiconductor layer is grown on a single crystal GaN substrate. At that point, a high defect density region cannot be prevented from being formed in a light emitting region. As a result, light emitting characteristics and reliability of the semiconductor laser deteriorate.
Therefore, in view of the foregoing, it would be desirable to provide a semiconductor light emitting device that has good characteristics such as good light emitting characteristic, high reliability, and long life and to provide a method for easily producing such a semiconductor light emitting device.
More generally, it would be desirable to provide a semiconductor device that has good characteristics, high reliability, and long life and to provide a method for easily producing such a semiconductor device.
Further more generally, it would be desirable to provide a variety of types of devices that have good characteristics, high reliabilities, and long lives and to provide a method for easily producing such devices.
In addition, it would be desirable to provide a semiconductor light emitting device that has good characteristics such as good light emitting characteristic, high reliability, and long life or methods for growing a nitride type III-V group compound semiconductor layer, a semiconductor layer, and a layer suitable for producing a semiconductor device that has good characteristics, high reliability, and long life or various types of devices that have good characteristics, high reliabilities, and long lives.
The inventors of the present invention intensively studied the foregoing problems and obtained the following result. The obtained result will be described in brief.
The inventors improved the technology disclosed in Japanese Patent Laid-Open Publication No. 2001-102307 and succeeded in controlling the positions of high defect density regions that take place in a low defect density region. In other words, high defect density regions are not gathered while a crystal is being grown. Instead, a seed crystal or the like is artificially, circularly and regularly (for example periodically) formed on a proper substrate such as a GaAs substrate. On the seed crystal, a crystal is grown so as to control the positions of the high defect density regions. As a result, the crystal quality can be improved and a good crystal region can be widened. In this case, by arranging a seed crystal or the like, a pattern of the high defect density regions can be freely changed.
In this case, the seed crystal or the like is for example a polycrystal, an amorphous substance, a single crystal of GaN, a nitride type III-V group compound semiconductor such as AlGaInN other than GaN, or a material other than a nitride type III-V group compound semiconductor. However, as long as the seed crystal or the like is a core that defines the position at which crystal defects gather, the structure of the seed crystal or the like is not restricted.
When a semiconductor light emitting device such as a semiconductor laser, more generally, a semiconductor device is produced using such a substrate, it is necessary to prevent high defect density regions on the substrate from adversely affecting the device. In other words, when a semiconductor layer is grown on a substrate, defects of high defect density regions on a base substrate propagates to the semiconductor layer. Thus, it is necessary to prevent the characteristics of the device and the reliability thereof from deteriorating due to the defects.
In the case that it is difficult to obtain a substrate that has a low defect density and whose material is the same as a semiconductor used for a device, when the semiconductor layer is grown on the substrate, such a problem also takes place. More generally, in the case that it is difficult to obtain a substrate whose material is the same as a device, when a layer is grown on the substrate, such a problem takes place.
The inventors of the present invention studied various techniques and finally found out an effective technique that can solve the foregoing problems. Finally, the inventors devised the present invention.
In other words, to solve the foregoing problem, a first aspect of the present invention is a method for producing a semiconductor light emitting device, comprising the step of growing a nitride type III-V group compound semiconductor layer that forms a light emitting device structure on a principal plane of a nitride type III-V group compound semiconductor substrate on which a plurality of second regions made of a crystal having a second average dislocation density are regularly arranged in a first region made of a crystal having a first average dislocation density so as to produce a semiconductor light emitting device, the second average dislocation density being greater than the first average dislocation density,
wherein the nitride type III-V group compound semiconductor layer does not directly contact the second regions on the principal plane of the nitride type III-V group compound semiconductor substrate.
To prevent the nitride type III-V group compound semiconductor layer from directly contacting the second regions on the principal plane of the nitride type III-V group compound semiconductor substrate, before the nitride type III-V group compound semiconductor layer is grown, at least part of the second regions is removed from the principal plane of the nitride type III-V group compound semiconductor substrate. More practically, before the nitride type III-V group compound semiconductor layer is grown, the second regions are removed from the principal plane of the nitride type III-V group compound semiconductor substrate for a predetermined depth. In this case, the predetermined depth is selected in accordance with the structure of the device composed of the nitride type III-V group compound semiconductor layer, the growing condition of the nitride type III-V group compound semiconductor layer, and so forth. Generally, the predetermined depth is 1 μm or greater. Preferably, the predetermined depth is around the thickness of the device composed of the nitride type III-V group compound semiconductor layer or greater (for example, 10 μm or greater). Before the nitride type III-V group compound semiconductor layer is grown, all the second regions may be removed from the principal plane of the nitride III-V group compound semiconductor substrate. The second regions are removed typically by etching. In reality, the second regions are removed by wet-etching, dry-etching, thermochemically-etching, ion-milling, or the like.
To prevent the nitride type III-V group compound semiconductor layer from directly contacting the second regions on the principal plane of the nitride type III-V group compound semiconductor substrate, before the nitride type III-V group compound semiconductor layer is grown, the front surface of the second regions may be coated with a coating layer. As the coating layer, various types can be used as long as they can withstand the growing temperature. Practically, as the coating layer, an insulation film such as a SiO2 film, a SixNy film, or a SOG (Spin on Glass) film, a metal film having a high melting point such as tungsten (W), molybdenum (Mo), or tantalum (Ta), or a nitride film thereof can be used. In this case, only the coating layer may be formed in the second regions. When the second regions are removed from the principal plane of the nitride type III-V group compound semiconductor substrate for the predetermined depth, the removed portions of the second regions may be filled with the coating layer. In the former, the front surface of the coating layer is higher than the principal plane of the nitride type III-V group compound semiconductor substrate. In the latter, by using an etch-back technique or the like, the front surface of the coating layer may be matched with the principal plane of the nitride type III-V group compound semiconductor substrate.
The interval of two adjacent second regions or the arrangement period of the second regions is selected in accordance with the size of the device. Generally, the interval or arrangement period is 20 μm or greater, 50 μm or greater, or 100 μm or greater. The upper limit of the interval or arrangement period of the second regions is not clearly defined. However, generally, the interval or arrangement period of the second regions is around 1000 μm. The second regions typically pierce a nitride type III-V group compound semiconductor substrate. The second regions are typically formed in an irregular polygonal prism shape. Third regions may be disposed between the first region and the second regions, the third regions having a third average dislocation density that is greater than the first average dislocation density and lower than the second average dislocation density. In this case, the nitride type III-V group compound semiconductor layer does not directly contact the second regions on the principal plane of the nitride type III-V group compound semiconductor substrate. Preferably, the nitride type III-V group compound semiconductor layer does not directly contact the second regions and the third regions on the principal plane of the nitride type III-V group compound semiconductor substrate. In the latter case, practically, before the nitride type III-V group compound semiconductor layer is grown, at least part of the second regions and the third regions is removed from the principal plane of the nitride type III-V group compound semiconductor substrate.
The diameter of each of the second regions is typically 10 μm or greater and 100 μm or smaller. The diameter of each of the second regions is more typically 20 μm or greater and 50 μm or smaller. When the third regions are disposed, the diameter of each of the third regions is typically greater than the diameter of each of the second regions by 20 μm or greater and 200 μm or smaller. The diameter of each of the third regions is more typically greater than the diameter of each of the second regions by 40 μm or greater and 160 μm or smaller. The diameter of each of the third regions is most typically greater than the diameter of each of the second regions by 60 μm or greater and 140 μm or smaller.
The average dislocation density of each of the second regions is generally five times greater than the average dislocation density of the first region.
The average dislocation density of the first region is 2×106 cm−2 or smaller and the average dislocation density of each of the second regions is 1×108 cm−2 or greater. When the third regions are disposed, the average dislocation density of each of the third regions is typically 1×108 cm−2 or smaller and 2×106 cm−2 or greater.
To prevent the second regions that have a high average dislocation density from adversely affecting the light emitting region of the semiconductor light emitting device, the light emitting region is spaced apart from the second regions by 1 μm or greater, preferably 10 μm or greater, more preferably 100 μm or greater. When there are third regions, most preferably the light emitting region of the semiconductor light emitting device does not contain the second regions and the third regions. More practically, the semiconductor light emitting device is a semiconductor laser or a light emitting diode. When the semiconductor light emitting device is a semiconductor laser, a region in which a drive current flows through a stripe shaped electrode is preferably spaced apart from the second regions by 1 μm or greater, more preferably by 10 μm or greater, further more preferably by 100 μm or greater. When there are third regions, most preferably, a region in which the drive current flows through a stripe shaped electrode does not contain the second regions and the third region. The number of stripe shaped electrodes, namely the number of laser stripes, may be one or plurality. The width of the stripe shaped electrode can be selected as required.
The nitride type III-V group compound semiconductor substrate or the nitride type III-V group compound semiconductor layer is most generally made of AlxByGa1-x-y-zInzAsuN1-u-vPv (where 0≦x≦1, 0≦y≦1, 0≦z≦1, 0≦u≦1, 0≦v≦1, 0≦x+y+z<1, 0≦u+v<1). The nitride type III-V group compound semiconductor substrate or the nitride type III-V group compound semiconductor layer is more practically made of AlxByGa1-x-y-zInzN (where 0≦x≦1, 0y≦1, 0≦z≦1, 0≦x+y+z<1). The nitride type III-V group compound semiconductor substrate or the nitride type III-V group compound semiconductor layer is typically made of AlxGa1-x-zInzN (where 0≦x≦1, 0≦z≦1). The nitride type III-V group compound semiconductor substrate is most typically made of GaN.
The description for the first aspect of the present invention applies to the other aspects unless that is contrary to characteristics of the other aspects.
A second aspect of the present invention is a method for producing a semiconductor light emitting device, comprising the step of:
growing a nitride type III-V group compound semiconductor layer that forms a light emitting device structure on a principal plane of a nitride type III-V group compound semiconductor substrate of which a plurality of second regions are regularly arranged in a first region so as to produce a semiconductor light emitting device, the first region being made of a crystal having a first average defect density, the plurality of second regions having a second average defect density that is greater than the first average defect density,
wherein the nitride type III-V group compound semiconductor layer does not directly contact the second regions on the principal plane of the nitride type III-V group compound semiconductor substrate.
The “average defect density” represents an average density of all lattice defects that adversely affect characteristics and reliability of a device. The defects include all types of defects such as dislocation, stacking defect, and point defect (this definition applies to the description that follows).
A third aspect of the present invention is a method for producing a semiconductor light emitting device, comprising the step of:
growing a nitride type III-V group compound semiconductor layer that forms a light emitting device structure on a principal plane of a nitride type III-V group compound semiconductor substrate of which a plurality of second regions made of a crystal are regularly arranged in a first region made of a crystal so as to produce a semiconductor light emitting device, the crystallinity of the second regions being worse than the crystallinity of the first region,
wherein the nitride type III-V group compound semiconductor layer does not directly contact the second regions on the principal plane of the nitride type III-V group compound semiconductor substrate.
Typically, the first region made of a crystal is a single crystal. The second regions whose crystallinity is worse than the first region is a single crystal, an amorphous substance, or a mixture of at least two thereof (this definition applied to the description that follows). This corresponds to the case that the average dislocation density or average defect density of the second regions is greater than that of the first region.
A fourth aspect of the present invention is a method for producing a semiconductor device, comprising the step of:
growing a nitride type III-V group compound semiconductor layer that forms a device structure on a principal plane of a nitride type III-V group compound semiconductor substrate on which a plurality of second regions made of a crystal having a second average dislocation density are regularly arranged in a first region made of a crystal having a first average dislocation density so as to produce a semiconductor device, the second average dislocation density being greater than the first average dislocation density,
wherein the nitride type III-V group compound semiconductor layer does not directly contact the second regions on the principal plane of the nitride type III-V group compound semiconductor substrate.
A fifth aspect of the present invention is a method for producing a semiconductor device, comprising the step of:
growing a nitride type III-V group compound semiconductor layer that forms a device structure on a principal plane of a nitride type III-V group compound semiconductor substrate on which a plurality of second regions made of a crystal having a second average defect density are regularly arranged in a first region made of a crystal having a first average defect density so as to produce a semiconductor device, the second average dislocation density being greater than the first average dislocation density,
wherein the nitride type III-V group compound semiconductor layer does not directly contact the second regions on the principal plane of the nitride type III-V group compound semiconductor substrate.
A sixth aspect of the present invention is a method for producing a semiconductor device, comprising the step of:
growing a nitride type III-V group compound semiconductor layer that forms a device structure on a principal plane of a nitride type III-V group compound semiconductor substrate on which a plurality of second regions made of a crystal are regularly arranged in a first region made of a crystal so as to produce a semiconductor device, the crystallinity of the second regions being worse than the crystallinity of the first region,
wherein the nitride type III-V group compound semiconductor layer does not directly contact the second regions on the principal plane of the nitride type III-V group compound semiconductor substrate.
According to the fourth aspect to sixth aspect of the present invention, the semiconductor device includes a light emitting device such as a light emitting diode, a semiconductor laser, or the like, a photo detector, a field effect transistor (FET) such as a high electron mobility transistor, and an electron traveling device such as a hetero junction bipolar transistor (HBT) (this definition applies to the description that follows).
According to the fourth aspect to sixth aspect of the present invention, the active region of the semiconductor device is spaced apart from the second regions by preferably 1 μm or greater, more preferably 10 μm or greater, further preferably 100 μm or greater so as to prevent the second regions from adversely affecting the active region of the semiconductor device. When there are third regions, most preferably the active region of the semiconductor device does not contain the second regions and the third region. The active region represents a light emitting region of a semiconductor light emitting device, a light receiving region of a semiconductor photo detector, and an electron traveling region of an electron traveling device (this definition applies to the description that follows).
A seventh aspect of the present invention is a method for producing a semiconductor light emitting device, comprising the step of:
growing a semiconductor layer that forms a light emitting device structure on a principal plane of a semiconductor substrate on which a plurality of second regions made of a crystal having a second average dislocation density are regularly arranged in a first region made of a crystal having a first average dislocation density so as to produce a semiconductor light emitting device, the second average dislocation density being greater than the first average dislocation density,
wherein the semiconductor layer does not directly contact the second regions on the principal plane of the semiconductor substrate.
An eighth aspect of the present invention is a method for producing a semiconductor light emitting device, comprising the step of:
growing a semiconductor layer that forms a light emitting device structure on a principal plane of a semiconductor substrate on which a plurality of second regions made of a crystal having a second average defect density are regularly arranged in a first region made of a crystal having a first average defect density so as to produce a semiconductor light emitting device, the second average defect density being greater than the first average dislocation density,
wherein the semiconductor layer does not directly contact the second regions on the principal plane of the semiconductor substrate.
A ninth aspect of the present invention is a method for producing a semiconductor light emitting device, comprising the step of:
growing a semiconductor layer that forms a light emitting device structure on a principal plane of a semiconductor substrate on which a plurality of second regions made of a crystal are regularly arranged in a first region made of a crystal so as to produce a semiconductor light emitting device, the crystallinity of the second regions being worse than the crystallinity of the first region,
wherein the semiconductor layer does not directly contact the second regions on the principal plane of the semiconductor substrate.
A tenth aspect of the present invention is a method for producing a semiconductor device, comprising the step of:
growing a semiconductor layer that forms a device structure on a principal plane of a semiconductor substrate on which a plurality of second regions made of a crystal having a second average dislocation density are regularly arranged in a first region made of a crystal having a first average dislocation density so as to produce a semiconductor device, the second average dislocation density being greater than the first average dislocation density,
wherein the semiconductor layer does not directly contact the second regions on the principal plane of the semiconductor substrate.
An eleventh aspect of the present invention is a method for producing a semiconductor device, comprising the step of:
growing a semiconductor layer that forms a device structure on a principal plane of a semiconductor substrate on which a plurality of second regions made of a crystal having a second average defect density are regularly arranged in a first region made of a crystal having a first average defect density so as to produce a semiconductor device, the second average defect density being greater than the first average dislocation density.
wherein the semiconductor layer does not directly contact the second regions on the principal plane of the semiconductor substrate.
A twelfth aspect of the present invention is a method for producing a semiconductor device, comprising the step of:
growing a semiconductor layer that forms a device structure on a principal plane of a semiconductor substrate on which a plurality of second regions made of a crystal are regularly arranged in a first region made of a crystal so as to produce a semiconductor device, the crystallinity of the second regions being worse than the crystallinity of the first region,
wherein the semiconductor layer does not directly contact the second regions on the principal plane of the semiconductor substrate.
According to the tenth aspect to twelfth aspect of the present invention, the material of the semiconductor substrate or the semiconductor layer is a nitride type III-V group compound semiconductor, another semiconductor having a wurtzit structure, more generally a hexagonal crystal structure for example ZnO, α-ZnS, α-CdS, or α-CdSe, or various types of semiconductors having other crystal structures.
A thirteenth aspect of the present invention is a method for producing a device, comprising the step of:
growing a layer that forms a device structure on a principal plane of a substrate on which a plurality of second regions made of a crystal having a second average dislocation density are regularly arranged in a first region made of a crystal having a first average dislocation density so as to produce a device, the second average dislocation density being greater than the first average dislocation density,
wherein the layer does not directly contact the second regions on the principal plane of the substrate.
A fourteenth aspect of the present invention is a method for producing a device, comprising the step of:
growing a layer that forms a device structure on a principal plane of a substrate on which a plurality of second regions made of a crystal having a second average defect density are regularly arranged in a first region made of a crystal having a first average defect density so as to produce a device, the second average defect density being greater than the first average dislocation density,
wherein the layer does not directly contact the second regions on the principal plane of the substrate.
A fifteenth aspect of the present invention is a method for producing a device, comprising the step of:
growing a layer that forms a device structure on a principal plane of a substrate on which a plurality of second regions made of a crystal are regularly arranged in a first region made of a crystal so as to produce a device, the crystallinity of the second regions being worse than the crystallinity of the first region,
wherein the layer does not directly contact the second regions on the principal plane of the substrate.
According to the thirteenth aspect to fifteenth aspect of the present invention, the device is a semiconductor device (for example, a light emitting device, a photo detector, or an electron traveling device), a piezoelectric device, an electricity collecting device, an optical device (for example, a secondary higher harmonic wave generating device), a dielectric device (including a ferrodielectric device), a superconductive device, or the like. In this case, as the material of the substrate or layer, the foregoing various types of semiconductors can be used. As the material of a piezoelectric device, an electricity collecting device, an optical device, a dielectric device, or a superconductive device, various types of materials (for example, an oxide) can be used. As the material of the oxide, many types of materials for example disclosed in Journal of the Society of Japan, Vol. 103, No. 11 (1995), pp. 1099-1111 and Materials Science and Engineering, B41 (1996) pp. 166-173 can be used.
A sixteenth aspect of the present invention is a method for producing a semiconductor light emitting device, comprising the step of:
growing a nitride type III-V group compound semiconductor layer that forms a light emitting device structure on a principal plane of a nitride type III-V group compound semiconductor substrate on which a plurality of second regions made of a crystal having a second average dislocation density are regularly arranged in a first region made of a crystal having a first average dislocation density so as to produce a semiconductor light emitting device, the second average dislocation density being greater than the first average dislocation density, the second regions being arranged at a first interval in a first direction and at a second interval in a second direction perpendicular to the first direction, the second interval being smaller than the first interval,
wherein the nitride type III-V group compound semiconductor layer does not directly contact the second regions on the principal plane of the nitride type III-V group compound semiconductor substrate.
A seventeenth aspect of the present invention is a method for producing a semiconductor light emitting device, comprising the step of:
growing a nitride type III-V group compound semiconductor layer that forms a light emitting device structure on a principal plane of a nitride type III-V group compound semiconductor substrate on which a plurality of second regions made of a crystal having a second average defect density are regularly arranged in a first region made of a crystal having a first average defect density so as to produce a semiconductor light emitting device, the second average defect density being greater than the first average defect density, the second regions being arranged at a first interval in a first direction and at a second interval in a second direction perpendicular to the first direction, the second interval being smaller than the first interval,
wherein the nitride type III-V group compound semiconductor layer does not directly contact the second regions on the principal plane of the nitride type III-V group compound semiconductor substrate.
An eighteenth aspect of the present invention is a method for producing a semiconductor light emitting device, comprising the step of:
growing a nitride type III-V group compound semiconductor layer that forms a light emitting device structure on a principal plane of a nitride type III-V group compound semiconductor substrate on which a plurality of second regions made of a crystal are regularly arranged in a first region made of a crystal so as to produce a semiconductor light emitting device, the crystallinity of the second regions being worse than the crystallinity of the first region, the second regions being arranged at a first interval in a first direction and at a second interval in a second direction perpendicular to the first direction, the second interval being smaller than the first interval,
wherein the nitride type III-V group compound semiconductor layer does not directly contact the second regions on the principal plane of the nitride type III-V group compound semiconductor substrate.
A nineteenth aspect of the present invention is a method for producing a semiconductor light emitting device, comprising the step of:
growing a nitride type III-V group compound semiconductor layer that forms a light emitting device structure on a principal plane of a nitride type III-V group compound semiconductor substrate on which a plurality of second regions that linearly extend and that are made of a crystal having a second average dislocation density are regularly arranged in parallel in a first region made of a crystal having a first average dislocation density so as to produce a semiconductor light emitting device, the second average dislocation density being greater than the first average dislocation density,
wherein the nitride type III-V group compound semiconductor layer does not directly contact the second regions on the principal plane of the nitride type III-V group compound semiconductor substrate.
A twentieth aspect of the present invention is a method for producing a semiconductor light emitting device, comprising the step of:
growing a nitride type III-V group compound semiconductor layer that forms a light emitting device structure on a principal plane of a nitride type III-V group compound semiconductor substrate on which a plurality of second regions that linearly extend and that are made of a crystal having a second average defect density are regularly arranged in parallel in a first region made of a crystal having a first average defect density so as to produce a semiconductor light emitting device, the second average defect density being greater than the first average defect density,
wherein the nitride type III-V group compound semiconductor layer does not directly contact the second regions on the principal plane of the nitride type III-V group compound semiconductor substrate.
A twenty first aspect of the present invention is a method for producing a semiconductor light emitting device, comprising the step of:
growing a nitride type III-V group compound semiconductor layer that forms a light emitting device structure on a principal plane of a nitride type III-V group compound semiconductor substrate on which a plurality of second regions that linearly extend and that are made of a crystal are regularly arranged in parallel in a first region made of a crystal so as to produce a semiconductor light emitting device, the crystallinity of the second regions being worse than the crystallinity of the first region,
wherein the nitride type III-V group compound semiconductor layer does not directly contact the second regions on the principal plane of the nitride type III-V group compound semiconductor substrate.
A twenty second aspect of the present invention is a method for producing a semiconductor device, comprising the step of:
growing a nitride type III-V group compound semiconductor layer that forms a device structure on a principal plane of a nitride type III-V group compound semiconductor substrate on which a plurality of second regions made of a crystal having a second average dislocation density are regularly arranged in a first region made of a crystal having a first average dislocation density so as to produce a semiconductor device, the second average dislocation density being greater than the first average dislocation density, the second regions being arranged at a first interval in a first direction and at a second interval in a second direction perpendicular to the first direction, the second interval being smaller than the first interval,
wherein the nitride type III-V group compound semiconductor layer does not directly contact the second regions on the principal plane of the nitride type III-V group compound semiconductor substrate.
A twenty third aspect of the present invention is a method for producing a semiconductor device, comprising the step of:
growing a nitride type III-V group compound semiconductor layer that forms a device structure on a principal plane of a nitride type III-V group compound semiconductor substrate on which a plurality of second regions made of a crystal having a second average defect density are regularly arranged in a first region made of a crystal having a first average defect density so as to produce a semiconductor device, the second average defect density being greater than the first average defect density, the second regions being arranged at a first interval in a first direction and at a second interval in a second direction perpendicular to the first direction, the second interval being smaller than the first interval,
wherein the nitride type III-V group compound semiconductor layer does not directly contact the second regions on the principal plane of the nitride type III-V group compound semiconductor substrate.
A twenty fourth aspect of the present invention is a method for producing a semiconductor device, comprising the step of:
growing a nitride type III-V group compound semiconductor layer that forms a device structure on a principal plane of a nitride type III-V group compound semiconductor substrate on which a plurality of second regions made of a crystal are regularly arranged in a first region made of a crystal so as to produce a semiconductor device, the crystallinity of the second regions being worse than the crystallinity of the first region, the second regions being arranged at a first interval in a first direction and at a second interval in a second direction perpendicular to the first direction, the second interval being smaller than the first interval,
wherein the nitride type III-V group compound semiconductor layer does not directly contact the second regions on the principal plane of the nitride type III-V group compound semiconductor substrate.
A twenty fifth aspect of the present invention is a method for producing a semiconductor device, comprising the step of:
growing a nitride type III-V group compound semiconductor layer that forms a device structure on a principal plane of a nitride type III-V group compound semiconductor substrate on which a plurality of second regions that linearly extend and that are made of a crystal having a second average dislocation density are regularly arranged in parallel in a first region made of a crystal having a first average dislocation density so as to produce a semiconductor device, the second average dislocation density being greater than the first average dislocation density,
wherein the nitride type III-V group compound semiconductor layer does not directly contact the second regions on the principal plane of the nitride type III-V group compound semiconductor substrate.
A twenty sixth aspect of the present invention is a method for producing a semiconductor device, comprising the step of:
growing a nitride type III-V group compound semiconductor layer that forms a device structure on a principal plane of a nitride type III-V group compound semiconductor substrate on which a plurality of second regions that linearly extend and that are made of a crystal having a second average defect density are regularly arranged in parallel in a first region made of a crystal having a first average defect density so as to produce a semiconductor device, the second average defect density being greater than the first average defect density,
wherein the nitride type III-V group compound semiconductor layer does not directly contact the second regions on the principal plane of the nitride type III-V group compound semiconductor substrate.
A twenty seventh aspect of the present invention is a method for producing a semiconductor device, comprising the step of:
growing a nitride type III-V group compound semiconductor layer that forms a device structure on a principal plane of a nitride type III-V group compound semiconductor substrate on which a plurality of second regions that linearly extend and that are made of a crystal are regularly arranged in parallel in a first region made of a crystal so as to produce a semiconductor device, the crystallinity of the second regions being worse than the crystallinity of the first region,
wherein the nitride type III-V group compound semiconductor layer does not directly contact the second regions on the principal plane of the nitride type III-V group compound semiconductor substrate.
A twenty eighth aspect of the present invention is a method for producing a semiconductor light emitting device, comprising the step of:
growing a semiconductor layer that forms a light emitting device structure on a principal plane of a semiconductor substrate on which a plurality of second regions made of a crystal having a second average dislocation density are regularly arranged in a first region made of a crystal having a first average dislocation density so as to produce a semiconductor light emitting device, the second average dislocation density being greater than the first average dislocation density, the second regions being arranged at a first interval in a first direction and at a second interval in a second direction perpendicular to the first direction, the second interval being smaller than the first interval,
wherein the semiconductor layer does not directly contact the second regions on the principal plane of the semiconductor substrate.
A twenty ninth aspect of the present invention is a method for producing a semiconductor light emitting device, comprising the step of:
growing a semiconductor layer that forms a light emitting device structure on a principal plane of a semiconductor substrate on which a plurality of second regions made of a crystal having a second average defect density are regularly arranged in a first region made of a crystal having a first average defect density so as to produce a semiconductor light emitting device, the second average defect density being greater than the first average defect density, the second regions being arranged at a first interval in a first direction and at a second interval in a second direction perpendicular to the first direction, the second interval being smaller than the first interval,
wherein the semiconductor layer does not directly contact the second regions on the principal plane of the semiconductor substrate.
A thirtieth aspect of the present invention is a method for producing a semiconductor light emitting device, comprising the step of: growing a semiconductor layer that forms a light emitting device structure on a principal plane of a semiconductor substrate on which a plurality of second regions made of a crystal are regularly arranged in a first region made of a crystal so as to produce a semiconductor light emitting device, the crystallinity of the second regions being worse than the crystallinity of the first region, the second regions being arranged at a first interval in a first direction and at a second interval in a second direction perpendicular to the first direction, the second interval being smaller than the first interval,
wherein the semiconductor layer does not directly contact the second regions on the principal plane of the semiconductor substrate.
A thirty first aspect of the present invention is a method for producing a semiconductor light emitting device, comprising the step of:
growing a semiconductor layer that forms a light emitting device structure on a principal plane of a semiconductor substrate on which a plurality of second regions that linearly extend and that are made of a crystal having a second average dislocation density are regularly arranged in parallel in a first region made of a crystal having a first average dislocation density so as to produce a semiconductor light emitting device, the second average dislocation density being greater than the first average dislocation density,
wherein the semiconductor layer does not directly contact the second regions on the principal plane of the semiconductor substrate.
A thirty second aspect of the present invention is a method for producing a semiconductor light emitting device, comprising the step of:
growing a semiconductor layer that forms a light emitting device structure on a principal plane of a semiconductor substrate on which a plurality of second regions that linearly extend and that are made of a crystal having a second average defect density are regularly arranged in parallel in a first region made of a crystal having a first average defect density so as to produce a semiconductor light emitting device, the second average defect density being greater than the first average defect density,
wherein the semiconductor layer does not directly contact the second regions on the principal plane of the semiconductor substrate.
A thirty third aspect of the present invention is a method for producing a semiconductor light emitting device, comprising the step of:
growing a semiconductor layer that forms a light emitting device structure on a principal plane of a semiconductor substrate on which a plurality of second regions that linearly extend and that are made of a crystal are regularly arranged in parallel in a first region made of a crystal so as to produce a semiconductor light emitting device, the crystallinity of the second regions being worse than the crystallinity of the first region,
wherein the semiconductor layer does not directly contact the second regions on the principal plane of the semiconductor substrate.
A thirty fourth aspect of the present invention is a method for producing a semiconductor device, comprising the step of:
growing a semiconductor layer that forms a device structure on a principal plane of a semiconductor substrate on which a plurality of second regions made of a crystal having a second average dislocation density are regularly arranged in a first region made of a crystal having a first average dislocation density so as to produce a semiconductor device, the second average dislocation density being greater than the first average dislocation density, the second regions being arranged at a first interval in a first direction and at a second interval in a second direction perpendicular to the first direction, the second interval being smaller than the first interval,
wherein the semiconductor layer does not directly contact the second regions on the principal plane of the semiconductor substrate.
A thirty fifth aspect of the present invention is a method for producing a semiconductor device, comprising the step of:
growing a semiconductor layer that forms a device structure on a principal plane of a semiconductor substrate on which a plurality of second regions made of a crystal having a second average defect density are regularly arranged in a first region made of a crystal having a first average defect density so as to produce a semiconductor device, the second average defect density being greater than the first average defect density, the second regions being arranged at a first interval in a first direction and at a second interval in a second direction perpendicular to the first direction, the second interval being smaller than the first interval,
wherein the semiconductor layer does not directly contact the second regions on the principal plane of the semiconductor substrate.
A thirty sixth aspect of the present invention is a method for producing a semiconductor device, comprising the step of:
growing a semiconductor layer that forms a device structure on a principal plane of a semiconductor substrate on which a plurality of second regions made of a crystal are regularly arranged in a first region made of a crystal so as to produce a semiconductor device, the crystallinity of the second regions being worse than the crystallinity of the first region, the second regions being arranged at a first interval in a first direction and at a second interval in a second direction perpendicular to the first direction, the second interval being smaller than the first interval,
wherein the semiconductor layer does not directly contact the second regions on the principal plane of the semiconductor substrate.
A thirty seventh aspect of the present invention is a method for producing a semiconductor device, comprising the step of:
growing a semiconductor layer that forms a device structure on a principal plane of a semiconductor substrate on which a plurality of second regions that linearly extend and that are made of a crystal having a second average dislocation density are regularly arranged in parallel in a first region made of a crystal having a first average dislocation density so as to produce a semiconductor device, the second average dislocation density being greater than the first average dislocation density,
wherein the semiconductor layer does not directly contact the second regions on the principal plane of the semiconductor substrate.
A thirty eighth aspect of the present invention is a method for producing a semiconductor device, comprising the step of:
growing a semiconductor layer that forms a device structure on a principal plane of a semiconductor substrate on which a plurality of second regions that linearly extend and that are made of a crystal having a second average defect density are regularly arranged in parallel in a first region made of a crystal having a first average defect density so as to produce a semiconductor device, the second average defect density being greater than the first average defect density,
wherein the semiconductor layer does not directly contact the second regions on the principal plane of the semiconductor substrate.
A thirty ninth aspect of the present invention is a method for producing a semiconductor device, comprising the step of:
growing a semiconductor layer that forms a device structure on a principal plane of a semiconductor substrate on which a plurality of second regions that linearly extend and that are made of a crystal are regularly arranged in parallel in a first region made of a crystal so as to produce a semiconductor device, the crystallinity of the second regions being worse than the crystallinity of the first region,
wherein the semiconductor layer does not directly contact the second regions on the principal plane of the semiconductor substrate.
A fortieth aspect of the present invention is a method for producing a device, comprising the step of:
growing a layer that forms a device structure on a principal plane of a substrate on which a plurality of second regions made of a crystal having a second average dislocation density are regularly arranged in a first region made of a crystal having a first average dislocation density so as to produce a device, the second average dislocation density being greater than the first average dislocation density, the second regions being arranged at a first interval in a first direction and at a second interval in a second direction perpendicular to the first direction, the second interval being smaller than the first interval,
wherein the layer does not directly contact the second regions on the principal plane of the substrate.
A forty first aspect of the present invention is a method for producing a device, comprising the step of:
growing a layer that forms a device structure on a principal plane of a substrate on which a plurality of second regions made of a crystal having a second average defect density are regularly arranged in a first region made of a crystal having a first average defect density so as to produce a device, the second average defect density being greater than the first average defect density, the second regions being arranged at a first interval in a first direction and at a second interval in a second direction perpendicular to the first direction, the second interval being smaller than the first interval,
wherein the layer does not directly contact the second regions on the principal plane of the substrate.
A forty second aspect of the present invention is a method for producing a device, comprising the step of:
growing a layer that forms a device structure on a principal plane of a substrate on which a plurality of second regions made of a crystal are regularly arranged in a first region made of a crystal so as to produce a device, the crystallinity of the second regions being worse than the crystallinity of the first region, the second regions being arranged at a first interval in a first direction and at a second interval in a second direction perpendicular to the first direction, the second interval being smaller than the first interval,
wherein the layer does not directly contact the second regions on the principal plane of the substrate.
A forty third aspect of the present invention is a method for producing a device, comprising the step of:
growing a layer that forms a device structure on a principal plane of a substrate on which a plurality of second regions that linearly extend and that are made of a crystal having a second average dislocation density are regularly arranged in parallel in a first region made of a crystal having a first average dislocation density so as to produce a device, the second average dislocation density being greater than the first average dislocation density,
wherein the layer does not directly contact the second regions on the principal plane of the substrate.
A forty fourth aspect of the present invention is a method for producing a device, comprising the step of:
growing a layer that forms a device structure on a principal plane of a substrate on which a plurality of second regions that linearly extend and that are made of a crystal having a second average defect density are regularly arranged in parallel in a first region made of a crystal having a first average defect density so as to produce a device, the second average defect density being greater than the first average defect density,
wherein the layer does not directly contact the second regions on the principal plane of the substrate.
A forty fifth aspect of the present invention is a method for producing a device, comprising the step of:
growing a layer that forms a device structure on a principal plane of a substrate on which a plurality of second regions that linearly extend and that are made of a crystal are regularly arranged in parallel in a first region made of a crystal so as to produce a device, the crystallinity of the second regions being worse than the crystallinity of the first region,
wherein the layer does not directly contact the second regions on the principal plane of the substrate.
According to the sixteenth aspect to forty fifth aspect of the present invention, the interval (first interval) of the second regions in the first direction or the interval of the second regions that linearly extend is the same as the interval of the second regions or the arrangement interval of the second regions according to the first aspect of the present invention. In addition, the interval (first interval) of the second regions in the first direction or the interval of the second regions that linearly extend is the same as the interval of the second regions or the arrangement interval of the second regions according to the first aspect of the present invention except that the former is typically 50 μm or greater. According to the sixteenth aspect to eighteenth aspect, the twenty second aspect to twenty fourth aspect, the twenty eighth aspect to thirty aspect, the thirty fourth aspect to thirty sixth aspect, and the fortieth aspect to forty second aspect, the interval of the second regions in the second direction can be freely selected so that the interval of the second regions is smaller than the first interval. The interval of the second regions depends on the size of each of the second regions, generally 10 μm or greater and 1000 μm or smaller, typically, 20 μm or greater and 200 μm or smaller. In addition, in a chip region (hereinafter referred to as device region) that is formed by scrubbing the substrate, the number of rows of second regions in the second direction or the number of second regions that linearly extend is substantially not greater than seven. The maximum number of rows of second regions in the second direction or the maximum number of second regions that linearly extend is seven because the device region may contain seven second regions depending on the relation between the number of rows of second regions in the second direction or the interval of second regions that linearly extend and the chip size of the device. The number of rows of second regions in the second direction or the number of second regions that linearly extend of a semiconductor light emitting device is typically three or less.
The description for the first aspect to fifteenth aspect of the present invention applies to the sixteenth aspect to forty fifth aspect unless that is contrary to characteristics thereof.
A forty sixth aspect of the present invention is a method for growing a nitride type III-V group compound semiconductor layer on a principal plane of a nitride type III-V group compound semiconductor substrate on which a second region made of a crystal having a second average dislocation density is contained in a first region made of a crystal having a first average dislocation density, the second average dislocation density being greater than the first average dislocation density,
wherein the nitride type III-V group compound semiconductor layer does not directly contact the second region on the principal plane of the nitride type III-V group compound semiconductor substrate.
A forty seventh aspect of the present invention is a method for growing a nitride type III-V group compound semiconductor layer on a principal plane of a nitride type III-V group compound semiconductor substrate on which a second region made of a crystal having a second average defect density is contained in a first region made of a crystal having a first average defect density, the second average defect density being greater than the first average defect density,
wherein the nitride type III-V group compound semiconductor layer does not directly contact the second region on the principal plane of the nitride type III-V group compound semiconductor substrate.
A forty eighth aspect of the present invention is a method for growing a nitride type III-V group compound semiconductor layer on a principal plane of a nitride type III-V group compound semiconductor substrate on which a second region made of a crystal is contained in a first region made of a crystal, the crystallinity of the second region being worse than the crystallinity of the first region,
wherein the nitride type III-V group compound semiconductor layer does not directly contact the second region on the principal plane of the nitride type III-V group compound semiconductor substrate.
A forty ninth aspect of the present invention is a method for growing a semiconductor layer on a principal plane of a semiconductor substrate on which a second region made of a crystal having a second average dislocation density is contained in a first region made of a crystal having a first average dislocation density, the second average dislocation density being greater than the first average dislocation density,
wherein the semiconductor layer does not directly contact the second region on the principal plane of the semiconductor substrate.
A fiftieth aspect of the present invention is a method for growing a semiconductor layer on a principal plane of a semiconductor substrate on which a second region made of a crystal having a second average defect density is contained in a first region made of a crystal having a first average defect density, the second average defect density being greater than the first average defect density,
wherein the semiconductor layer does not directly contact the second region on the principal plane of the semiconductor substrate.
A fifty first aspect of the present invention is a method for growing a semiconductor layer on a principal plane of a semiconductor substrate on which a second region made of a crystal is contained in a first region made of a crystal, the crystallinity of the second region being worse than the crystallinity of the first region,
wherein the semiconductor layer does not directly contact the second region on the principal plane of the semiconductor substrate.
A fifty second aspect of the present invention is a method for growing a layer on a principal plane of a substrate on which a second region made of a crystal having a second average dislocation density is contained in a first region made of a crystal having a first average dislocation density, the second average dislocation density being greater than the first average dislocation density,
wherein the layer does not directly contact the second region on the principal plane of the substrate.
A fifty third aspect of the present invention is a method for growing a layer on a principal plane of a substrate on which a second region made of a crystal having a second average defect density is contained in a first region made of a crystal having a first average defect density, the second average defect density being greater than the first average defect density,
wherein the layer does not directly contact the second region on the principal plane of the substrate.
A fifty fourth aspect of the present invention is a method for growing a layer on a principal plane of a substrate on which a second region made of a crystal is contained in a first region made of a crystal, the crystallinity of the second region being worse than the crystallinity of the first region,
wherein the layer does not directly contact the second region on the principal plane of the substrate.
According to the forty sixth aspect to fifty fourth aspect of the present invention, the materials of the nitride type III-V group compound semiconductor substrate, the nitride type III-V group compound semiconductor layer, the semiconductor substrate, the semiconductor layer, the substrate, and the layer are the same as those according to the first aspect to fifteenth aspect of the present invention.
According to the present invention, since the nitride type III-V group compound semiconductor layer, the semiconductor layer, or the layer made of various types of materials that forms a light emitting device structure or a device structure does not directly contact the second regions on the principal plane of the nitride type III-V group compound semiconductor substrate, the semiconductor substrate, or the substrate, respectively, the average dislocation density, the average defect density, or the crystallinity of the second regions being greater or worse than that of the first region. As a result, the nitride type III-V group compound semiconductor layer, the semiconductor layer, or the layer made of various types of materials that forms the light emitting device structure or device structure can be prevented from being adversely affected by the second regions.
These and other objects, features and advantages of the present invention will become more apparent in light of the following detailed description of a best mode embodiment thereof, as illustrated in the accompanying drawings.
Next, with reference to the accompanying drawings, embodiments of the present invention will be described. In all drawings showing the embodiments of the present invention, same or corresponding portions will be denoted by same reference numerals.
The arrangement period of the regions B (for example, the interval between the centers of the most adjacent regions B) is for example 400 μm and the diameter thereof is for example 20 μm. The average dislocation density of the region A is for example 2×106 cm−2. The average dislocation density of the regions B is for example 1×108 cm−2.
The GaN substrate 1 can be produced by a crystal growing technology as follows.
The GaN substrate 1 is produced by the following crystal growing mechanism. A crystal is grown on a facet plane that is an inclined plane. The crystal is continuously grown on the inclined facet plane so as to propagate dislocations and gather them to a predetermined position. The region in which the crystal has been grown on the facet plane and from which dislocations have been propagated becomes a low density defect region. At a lower portion of the inclined facet plane, the crystal is grown and becomes a high density defect region having a clear boundary. The dislocations gather at the boundary of the high density defect region or the inside thereof. As a result, the dislocations disappear or stay at the boundary of the high density defect region or the inside thereof.
The shape of the facet plane depends on the shape of the high density defect region. When the defect region is formed in a dot shape, the facet plane surrounds the bottom of the dot and forms a pit. When the defect region is formed in a stripe shape, the facet plane is formed in a triangular prism shape of which the stripe is placed at the bottom and inclined facet planes are placed on both the sides of the stripe.
Thereafter, the front surface of the grown layer is ground and abraded. As a result, the front surface of the grown layer is smoothened so that the GaN substrate 1 can be used as a substrate.
The foregoing high density defect region may have several states. For example, the high density defect region may be made of a polycrystal. Alternatively, the high density defect region may be made of a single crystal that is slightly inclined against the adjacent low density defect region. Alternatively, the high density defect region may have an inverted C axis against the adjacent low density defect region. Thus, since the high density defect region has a clear boundary against the low density defect region, they are distinguished from each other.
By growing the crystal with the high density defect region, the crystal can be grown with the adjacent facet plane that is not buried.
When a crystal of GaN is grown on a base substrate, the high density defect region can be formed with a seed. The seed is for example a layer of an amorphous substance or a layer of a polycrystal. By growing GaN on the seed, the high density defect region can be formed.
The GaN substrate 1 can be practically produced in the following manner. First of all, a base substrate is prepared. As the base substrate, various types of substrates can be used. Although a sapphire substrate may be used, since it is not easily removed at a later step, it is preferable to use a GaAs substrate that can be easily removed. Thereafter, a seed made of for example a SiO2 film is formed on the base substrate. The seed can be formed in a dot shape or a stripe shape. Many seeds can be regularly formed. More practically, in this case, seeds are formed in accordance with the arrangement of the regions B shown in
Thereafter, the base substrate is removed. The thick film layer of GaN is ground and abraded so as to flatten the front surface thereof. As a result, the GaN substrate 1 can be produced. The thickness of the GaN substrate 1 can be freely designated.
The GaN substrate 1 produced in the foregoing manner has a principal plane that is the C plane. On the principal plane, a dot shaped (or stripe shaped) high density defect region that has a predetermined size, namely regions B, are regularly formed. The dislocation density of the single crystal region other than the regions B, namely the region A, is lower than that of the regions B.
To solve such a problem, according to the first embodiment, as shown in
The regions B can be etched in the following manner. Generally, nitride type III-V group compound semiconductors such as GaN are chemically stable. Thus, except for strong alkalis such as sodium hydroxide and acids such as strong hydrochloric acid and phosphoric acid at high temperature, the nitride type III-V group compound semiconductor semiconductors are not wet-etched at room temperature. However, generally, the dislocation density of the regions B of the GaN substrate 1 is much greater than that of the region A thereof. The bonding state of atoms of the crystal of the regions B that have a high defect density is imperfect in comparison with that of the region A. Thus, the etching speed of the regions B is greater than that of the region A that is nearly a perfect crystal. Thus, the regions B can be selectively etched against the region A. The regions B may be etched by masking the front surface of the region. Alternatively, by fully etching the front surface of the GaN substrate 1, only the regions B can be selectively etched. To increase the etching speed, the temperature of the etching solution may be raised. The etching solution may be potassium hydroxide (KOH) as an alkali solution or phosphoric acid as an acid. As a practical example of the etching method, a KOH solution placed in an etching tank is heated and kept at 75° C. A GaN substrate 1 is soaked in the KOH solution for 10 minutes. After the GaN substrate 1 has been etched, the GaN substrate 1 is removed from the etching tank. The GaN substrate 1 is rinsed with pure water. The GaN substrate 1 is dried by blowing dried nitrogen. By the etching, the regions B can be removed for a depth of around 5 μm. At that point, to prevent the rear surface of the GaN substrate 1 from being etched and becoming rough, a Ti/Pt film of which a Ti film for 20 nm and a Pt film for 300 nm have been laminated may be formed as a protection film by the vacuum evaporation method or the like. Thereafter, the GaN substrate 1 may be etched. The Ti/Pt film may be etched out by for example aqua regia.
The regions B may be etched by dry etching such as reactive ion etching (RIE) as well as the foregoing wet etching. Alternatively, the regions B may be thermo-chemically etched by heating and keeping the regions B at a temperature of 800° C. or higher in a hydrogen atmosphere, an ammonium atmosphere, or the like.
Next, a practical example of a process for producing a GaN type semiconductor laser using a GaN substrate 1 shown in
As shown in
The thickness of the n-type GaN buffer layer 5 is for example 0.05 μm. Si is doped as n-type impurities in the n-type GaN buffer layer 5. The thickness of the n-type AlGaN clad layer 6 is for example 1.0 μm. Si is doped as n-type impurities in the n-type AlGaN clad layer 6. The composition of Al of the n-type AlGaN clad layer 6 is for example 0.08. The thickness of the n-type GaN optical waveguide layer 7 is for example 0.1 μm. Si is doped as n-type impurities in the n-type GaN optical waveguide layer 7. The undoped Ga1-xInxN/Ga1-yInyN multiple quantum well structure active layer 8 has an InxGa1-xN layer as a well layer and an InyGa1-yN layer as a barrier layer. The InxGa1-xN layer has a thickness of 3.5 nm. x of InxGa1-xN is 0.14. The InyGa1-yN layer has a thickness of 7 nm. y of InyGa1-yN is 0.02. The InyGa1−yN layer has three wells.
The undoped InGaN deterioration protection layer 9 has a grated structure of which the In composition gradually decreases from the plane that is in contact with the active layer 8 to the plane that is in contact with the undoped InGaN deterioration protection layer 9. The composition of In of the plane that is in contact with the active layer 8 accords with the composition y of In of the InyGa1-yN layer as the barrier layer of the active layer 8. The composition of In of the plane that is in contact with the p-type AlGaN cap layer 10 is 0. The thickness of the undoped InGaN deterioration protection layer 9 is for example 20 nm.
The thickness of the p-type AlGaN cap layer 10 is for example 10 nm. For example, magnesium (Mg) is doped as p-type impurities in the p-type AlGaN cap layer 10. The composition of Al of the p-type AlGaN cap layer 10 is for example 0.2. The p-type AlGaN cap layer 10 prevents In from being removed from the active layer 8 when the p-type GaN optical waveguide layer 11, the p-type AlGaN clad layer 12, and the p-type contact layer 13 are grown. In addition, the p-type AlGaN cap layer 10 prevents carriers (electrons) from overflowing from the active layer 8. The thickness of the p-type GaN optical waveguide layer 11 is for example 0.1 μm. For example, Mg is doped as p-type impurities in the p-type GaN optical waveguide layer 11. The thickness of the p-type AlGaN clad layer 12 is for example 0.5 μm. For example, Mg is doped as p-type impurities in the p-type AlGaN clad layer 12. The composition of Al of the p-type AlGaN clad layer 12 is for example 0.08. The thickness of the p-type contact layer 13 is for example 0.1 μm. For example, Mg is doped as p-type impurities in the p-type contact layer 13.
The growing temperatures of the n-type GaN buffer layer 5, the n-type AlGaN clad layer 6, the n-type GaN optical waveguide layer 7, the p-type AlGaN cap layer 10, the p-type GaN optical waveguide layer 11, the p-type AlGaN clad layer 12, and the p-type contact layer 13, which do not contain In, are for example around 1000° C. The growing temperature of the Ga1-xInxN/Ga1-yInyN multiple quantum well structure active layer 8, which includes In, is for example in the range from 700 to 800° C., preferably for example 730° C. The growing temperature at which the undoped InGaN deterioration protection layer 9 starts growing is set to for example 730° C., which is the same as the growing temperature of the active layer 8. Thereafter, the growing temperature is linearly raised. The growing temperature at which the undoped InGaN deterioration protection layer 9 ends growing is set to for example 835° C., which is the same as the growing temperature of the p-type AlGaN cap layer 10.
With respect to growing materials of the GaN type semiconductor layer, as a material of Ga, trimethyl gallium ((CH3)3Ga, TMG) is used; as a material of Al, trimethyl aluminum ((CH3)3Al, TMA) is used; as a material of In, trimethyl indium ((CH3)3In, TMI) is used; as a material of N, NH3 is used. As a carrier gas, for example H2 is used. With respect to dopants, as an n-type dopant, for example mono-silane is used. As a p-type dopant, for example bis (methylcyclopentyl) magnesium ((CH3C5H4)2Mg) or bis (cyclopentyl) magnesium ((C5H5)2Mg) is used.
Thereafter, the GaN substrate 1 on which the GaN type semiconductor layer has been grown in the foregoing manner is removed from the MOCVD apparatus. Thereafter, an SiO2 film (not shown) is fully formed for a thickness of for example 0.1 μm on the surface of the p-type contact layer 13 by the CVD method, vacuum evaporating method, spattering method or the like. Thereafter, a resist pattern (not shown) is formed in a predetermined shape in accordance with the shape of the ridge portion on the SiO2 film by lithography. With a mask of the resist pattern, the SiO2 film is etched by wet etching using for example hydrochloric acid type etching solution or RIE method using an etching gas containing fluorine for example CF4 or CHF3.
Next, with a mask of the SiO2 film, the p-type AlGaN clad layer 12 is etched for a predetermined thickness. As a result, a ridge 14 that extends in a <1-100> direction is formed. The width of the ridge 14 is for example 3 μm. As an etching gas for the RIE, for example a chlorine type gas is used.
Thereafter, the SiO2 film as the etching mask is removed. Thereafter, an insulation film 15 made of a SiO2 film having a thickness of for example 0.3 μm is fully formed on the substrate by the CVD method, vacuum evaporating method, spattering method, or the like. The insulation film 15 serves to electrically insulate the substrate and protect the front surface thereof.
Thereafter, a resist pattern (not shown) that covers the front surface of the insulation film 15 excluding a p-type electrode forming region is formed by lithography.
Thereafter, with a mask of the resist pattern, the insulation film 15 is etched. As a result, an opening 15a is formed.
While the resist pattern is left, for example a Pd film, a Pt film, and an Au film are successively formed fully on the surface of the substrate by the vacuum evaporating method. Thereafter, the resist pattern is removed from the substrate along with the Pd film, the Pt film, and the Au film formed on the resist pattern (lift-off process). As a result, a p-type electrode 16 that is in contact with the p-type contact layer 13 is formed through the opening 15a of the insulation film 15. The thicknesses of the Pd film, the Pt film, and the Au film that compose the p-type electrode 16 are 10 nm, 100 nm, and 300 nm, respectively. Thereafter, an alloy process is performed for the substrate so as to ohmic-contact the p-side electrode 16 thereto.
Thereafter, for example a Ti film, a Pt film, and an Au film are successively formed on the rear surface of the GaN substrate 1 by for example vacuum evaporating method. As a result, an n-side electrode 17 having a Ti/Pt/Au structure is formed. The thicknesses of the Ti film, the Pt film, and the Au film that compose the n-side electrode 17 are for example 10 nm, 50 nm, and 100 nm, respectively. Thereafter, an alloy process is performed for the substrate so as to ohmic-contact the n-side electrode 17 thereto.
Thereafter, as shown in
In
In the example shown in
In this case, since the regions B exist on the end planes of the longer sides of each GaN type semiconductor laser, when a device is designed so that the laser stripe 3 is positioned near a straight line that connects the center points of the shorter sides of the laser stripe 3, the light emitting region can be prevented from being affected by the regions B.
By scrubbing, for example, cleaving the substrate along the straight line in the lengthwise direction shown in
Thus, as shown in
As described above, according to the first embodiment of the present invention, in the GaN substrate 1 of which the regions B having a high average dislocation density are periodically arranged in a hexagonal lattice shape in the region A having a low average dislocation density, the upper portions of the regions B are etched out so that the front surfaces of the regions B are spaced apart from the principal plane of the GaN substrate 1. In addition, a GaN type semiconductor layer that forms a laser structure is grown on the GaN substrate 1. As a result, the GaN type semiconductor layer that forms the laser structure can be prevented from being adversely affected by the regions B. Thus, a GaN type semiconductor laser that has good light emitting characteristics, good reliability, and long life can be accomplished.
In addition, according to the first embodiment, the undoped InGaN deterioration protection layer 9 is disposed adjacent to the active layer 8. In addition, the p-type AlGaN cap layer 10 is disposed adjacent to the undoped InGaN deterioration protection layer 9. Thus, the undoped InGaN deterioration protection layer 9 can remarkably suppress a stress of the active layer 8 by the p-type AlGaN cap layer 10. In addition, the undoped InGaN deterioration protection layer 9 can effectively prevent Mg as a p-type dopant of a p-type layer from diffusing in the active layer 7.
Next, a second embodiment of the present invention will be described.
As shown in
Except for the foregoing portion, the second embodiment is the same as the first embodiment. Thus, the description of the other portions of the second embodiment is omitted.
According to the second embodiment, the same advantage as the first embodiment can be obtained.
Next, a third embodiment of the present invention will be described.
As shown in
Except for the foregoing portion, the third embodiment is the same as the first embodiment. Thus, the description of the other portions of the third embodiment is omitted.
According to the third embodiment, the same advantage as the first embodiment can be obtained.
Next, a fourth embodiment of the present invention will be described.
As shown in
Except for the foregoing portion, the fourth embodiment is the same as the first embodiment. Thus, the description of the other portions of the fourth embodiment is omitted.
According to the fourth embodiment, the same advantage as the first embodiment can be obtained.
Next, a fifth embodiment of the present invention will be described.
As shown in
Except for the foregoing portion, the fifth embodiment is the same as the first embodiment. Thus, the description of the other portions of the fifth embodiment is omitted.
According to the fifth embodiment of the present invention, the same advantage as the first embodiment can be obtained.
Next, a sixth embodiment of the present invention will be described.
As shown in
Except for the foregoing portion, the sixth embodiment is the same as the first embodiment. Thus, the description of the other portions of the sixth embodiment is omitted.
According to the sixth embodiment, the same advantage as the first embodiment can be obtained.
Next, a seventh embodiment of the present invention will be described.
As shown in
Except for the foregoing portion, the seventh embodiment is the same as the first embodiment. Thus, the description of the other portions of the seventh embodiment is omitted.
According to the seventh embodiment, the same advantage as the first embodiment can be obtained.
Next, an eighth embodiment of the present invention will be described.
As shown in
Except for the foregoing portion, the eighth embodiment is the same as the first embodiment. Thus, the description of the other portions of the eighth embodiment is omitted.
According to the eighth embodiment, the same advantage as the first embodiment can be obtained.
Next, a ninth embodiment of the present invention will be described.
As shown in
Except for the foregoing portion, the ninth embodiment is the same as the first embodiment. Thus, the description of the other portions of the ninth embodiment is omitted.
According to the ninth embodiment, the same advantage as the first embodiment can be obtained.
Next, a tenth embodiment of the present invention will be described.
As shown in
Except for the foregoing portion, the tenth embodiment is the same as the first embodiment. Thus, the description of the other portions of the tenth embodiment is omitted.
According to the tenth embodiment, the same advantage as the first embodiment can be obtained.
Next, an eleventh embodiment of the present invention will be described.
As shown in
Unlike with the first embodiment of which the upper portions of the regions B of the GaN substrate 1 are etched out, according to the eleventh embodiment, the upper portions of both the regions B and the regions C of the GaN substrate 1 are etched out.
Except for the foregoing portion, the eleventh embodiment is the same as the first embodiment. Thus, the description of the other portions of the eleventh embodiment is omitted.
According to the eleventh embodiment, the same advantage as the first embodiment can be obtained.
Next, a twelfth embodiment of the present invention will be described.
Unlike with the second embodiment of which all the regions B of the GaN substrate 1 are etched out, according to the twelfth embodiment, all regions B and regions C of a GaN substrate 1 are etched out.
Except for the foregoing portion, the twelfth embodiment is the same as the first embodiment. Thus, the description of the other portions of the twelfth embodiment is omitted.
According to the twelfth embodiment, the same advantage as the first embodiment can be obtained.
Next, a thirteenth embodiment of the present invention will be described.
Unlike with the third embodiment of which the upper portions of the regions B of the GaN substrate 1 are etched out, according to the thirteenth embodiment, upper portions of both regions B and regions C of a GaN substrate 1 are etched out.
Except for the foregoing portion, the thirteen embodiment is the same as the first embodiment and the eleventh embodiment. Thus, the description of the other portions of the thirteenth embodiment is omitted.
According to the thirteenth embodiment, the same advantage as the first embodiment can be obtained.
Next, a fourteenth embodiment of the present invention will be described.
Unlike with the fourth embodiment of which the upper portions of the regions B of the GaN substrate 1 are etched out, according to the fourteenth embodiment, upper portions of both regions B and regions C of a GaN substrate 1 are etched out.
Except for the foregoing portion, the fourteenth embodiment is the same as the first embodiment and the eleventh embodiment. Thus, the description of the other portions of the fourteenth embodiment is omitted.
According to the fourteenth embodiment, the same advantage as the first embodiment can be obtained.
Next, a fifteenth embodiment of the present invention will be described.
Unlike with the fifth embodiment of which the regions B of the GaN substrate 1 are coated with the insulation film 18, according to the fifteenth embodiment, regions B and regions C of a GaN substrate 1 are coated with an insulation film 18.
Except for the foregoing portion, the fifteenth embodiment is the same as the first embodiment, the fifth embodiment, and the eleventh embodiment. Thus, the description of the other portions of the fifteenth embodiment is omitted.
According to the fifteenth embodiment, the same advantage as the first embodiment can be obtained.
Next, a sixteenth embodiment of the present invention will be described.
Unlike with the sixth embodiment of which the regions B of the GaN substrate 1 are coated with the insulation film 18, according to the sixteenth embodiment, both regions B and regions C of a GaN substrate 1 are coated with an insulation film 18.
Except for the foregoing portion, the sixteenth embodiment is the same as the first embodiment, the fifth embodiment, and the eleventh embodiment. Thus, the description of the other portions of the sixteenth embodiment is omitted.
According to the sixteenth embodiment, the same advantage as the first embodiment can be obtained.
Next, a seventeenth embodiment of the present invention will be described.
Unlike with the seventh embodiment of which the upper portions of the regions B of the GaN substrate 1 are etched out, according to the seventeenth embodiment, upper portions of regions B and regions C of a GaN substrate 1 are etched out.
Except for the foregoing portion, the seventeenth embodiment is the same as the first embodiment, the fifth embodiment, and the eleventh embodiment. Thus, the description of the other portions of the seventeenth embodiment is omitted.
According to the seventeenth embodiment, the same advantage as the first embodiment can be obtained.
Next, an eighteenth embodiment of the present invention will be described.
Unlike with the eighth embodiment of which the upper portions of the regions B of the GaN substrate 1 are etched out, according to the eighteenth embodiment, upper portions of both regions B and regions C of a GaN substrate 1 are etched out.
Except for the foregoing portion, the eighteenth embodiment is the same as the first embodiment, the fifth embodiment, and the eleventh embodiment. Thus, the description of the other portions of the eighteenth embodiment is omitted.
According to the eighteen embodiment, the same advantage as the first embodiment can be obtained.
Next, a nineteenth embodiment of the present invention will be described.
Unlike with the ninth embodiment of which the upper portions of the regions B of the GaN substrate 1 are etched out, according to the nineteenth embodiment, upper portions of both regions B and regions C of the GaN substrate 1 are etched out.
Except for the foregoing portion, the nineteenth embodiment is the same as the first embodiment, the fifth embodiment, and the eleventh embodiment. Thus, the description of the other portions of the nineteenth embodiment is omitted.
According to the nineteenth embodiment, the same advantage as the first embodiment can be obtained.
Next, a twentieth embodiment of the present invention will be described.
Unlike with the tenth embodiment of which the upper portions of the regions B of the GaN substrate 1 are etched out, according to the twentieth embodiment, upper portions of regions B and regions C of a GaN substrate 1 are etched out.
Except for the foregoing portion, the twentieth embodiment is the same as the first embodiment, the fifth embodiment, and the eleventh embodiment. Thus, the description of the other portions of the twentieth embodiment is omitted.
According to the twentieth embodiment, the same advantage as the first embodiment can be obtained.
Next, a twenty first embodiment of the present invention will be described.
As shown in
Unlike with the first embodiment, according to the twenty first embodiment, the device region 2 is scrubbed by cleaving along the contour lines that connect the centers of the regions B. As a result, a mirror of a resonator is formed.
Since there are many dislocations in the regions B, it is thought that the regions B are more easily broken than the region A. Thus, when the device region 2 is scrubbed along straight lines that connect the regions B, since they function as perforations, the region can be neatly cleaved. At that point, since there are many dislocations on end planes of the regions B, although the end planes thereof do not always become flat, the end planes of the region A become flat.
The end planes of the laser stripe 3 should be flat. However, in the arrangement shown in
Except for the foregoing portion, the twenty first embodiment is the same as the first embodiment. Thus, the description of the other portions of the twenty first embodiment is omitted.
According to the twenty first embodiment, the same advantage as the first embodiment can be obtained.
Next, a twenty second embodiment of the present invention will be described.
Except for the foregoing portion, the twenty second embodiment is the same as the first embodiment. Thus, the description of the other portions of the twenty second embodiment is omitted.
According to the twenty second embodiment, the same advantage as the first embodiment can be obtained.
Next, a twenty third embodiment of the present invention will be described.
According to the twenty third embodiment, as shown in
Except for the foregoing portion, the twenty third embodiment is the same as the first embodiment. Thus, the description of the other portions of the twenty third embodiment is omitted.
According to the twenty third embodiment, the same advantage as the first embodiment can be obtained.
Next, a twenty fourth embodiment of the present invention will be described.
As shown in
Except for the foregoing portion, the twenty fourth embodiment is the same as the twenty third embodiment and the first embodiment. Thus, the description of the other portions of the twenty fourth embodiment is omitted.
According to the twenty fourth embodiment, the same advantage as the first embodiment can be obtained.
Next, a twenty fifth embodiment of the present invention will be described.
As shown in
Except for the foregoing portion, the twenty fifth embodiment is the same as the twenty third embodiment and the first embodiment. Thus, the description of the other portions of the twenty fifth embodiment is omitted.
According to the twenty fifth embodiment, the same advantage as the first embodiment can be obtained.
Next, a twenty sixth embodiment of the present invention will be described.
As shown in
Except for the foregoing portion, the twenty sixth embodiment is the same as the twenty third embodiment and the first embodiment. Thus, the description of the other portions of the twenty sixth embodiment is omitted.
According to the twenty sixth embodiment, the same advantage as the first embodiment can be obtained.
Next, a twenty seventh embodiment of the present invention will be described.
As shown in
Except for the foregoing portion, the twenty seventh embodiment is the same as the twenty third embodiment and the first embodiment. Thus, the description of the other portions of the twenty seventh embodiment is omitted.
According to the twenty seventh embodiment, the same advantage as the first embodiment can be obtained.
Next, a twenty eighth embodiment of the present invention will be described.
As shown in
Except for the foregoing portion, the twenty eighth embodiment is the same as the twenty third embodiment and the first embodiment. Thus, the description of the other portions of the twenty eighth embodiment is omitted.
According to the twenty eighth embodiment, the same advantage as the first embodiment can be obtained.
Next, a twenty ninth embodiment of the present invention will be described.
According to the twenty ninth embodiment, as shown in
Except for the foregoing portion, the twenty ninth embodiment is the same as the first embodiment. Thus, the description of the other portions of the twenty ninth embodiment is omitted.
According to the twenty ninth embodiment, the same advantage as the first embodiment can be obtained.
Next, a thirtieth embodiment of the present invention will be described.
As shown in
Except for the foregoing portion, the thirtieth embodiment is the same as the twenty ninth embodiment and the first embodiment. Thus, the description of the other portions of the thirtieth embodiment is omitted.
According to the thirtieth embodiment, the same advantage as the first embodiment can be obtained.
Next, a thirty first embodiment of the present invention will be described.
As shown in
Except for the foregoing portion, the thirty first embodiment is the same as the twenty ninth embodiment and the first embodiment. Thus, the description of the other portions of the thirty first embodiment is omitted.
According to the thirty first embodiment, the same advantage as the first embodiment can be obtained.
Next, a thirty second embodiment will be described.
As shown in
Except for the foregoing portion, the thirty second embodiment is the same as the twenty ninth embodiment and the first embodiment. Thus, the description of the other portions of the thirty second embodiment is omitted.
According to the thirty second embodiment, the same advantage as the first embodiment can be obtained.
Next, a thirty third embodiment of the present invention will be described.
As shown in
Except for the foregoing portion, the thirty third embodiment is the same as the twenty ninth embodiment and the first embodiment. Thus, the description of the other portions of the thirty third embodiment is omitted.
According to the thirty third embodiment, the same advantage as the first embodiment can be obtained.
Next, a thirty fourth embodiment of the present invention will be described.
As shown in
Except for the foregoing portion, the thirty fourth embodiment is the same as the twenty ninth embodiment and the first embodiment. Thus, the description of the other portions of the thirty fourth embodiment is omitted.
According to the thirty fourth embodiment, the same advantage as the first embodiment can be obtained.
Although the present invention has been shown and described with respect to a best mode embodiment thereof, it should be understood by those skilled in the art that the foregoing and various other changes, omissions, and additions in the form and detail thereof may be made therein without departing from the spirit and scope of the present invention.
For example, numeric values, structures, substrates, materials, processes, and so forth of the foregoing embodiments are just examples. When necessary, different numeric values, structures, substrates, materials, processes, and so forth can be used.
In reality, in the foregoing embodiments, the present invention was applied to a method for producing a GaN type semiconductor laser having a SCH structure. In addition, the present invention can be applied to a method for producing a GaN type light emitting diode having a double heterostructure (DH). Moreover, the present invention can be also applied to a method for producing a GaN type light emitting diode. In addition, the present invention can be applied to an electron traveling device using a nitride type III-V group compound semiconductor such as a GaN type FET or a GaN type hetero-junction bipolar transistor (HBT).
According to the foregoing embodiments, the GaN substrate 1 may be disposed on a different type substrate such as a sapphire substrate.
In addition, according to the foregoing embodiments, the MOCVD method is used to grow a GaN type semiconductor layer. Alternatively, a GaN type semiconductor laser may be grown by hydride vapor phase epitaxial growth method, halide vapor phase epitaxial growth (HVPE) method, molecular ray epitaxy (MBE) method, or the like.
In addition, according to the foregoing embodiments, as a carrier gas with which a crystal is grown by the MOCVD method, H2 gas is used. When necessary, another carrier gas for example a mixed gas of H2 and N2 or a mixed gas of He and Ar may be used.
In addition, according to the foregoing embodiment, end planes of a resonator are formed by cleaving. Alternatively, end planes of a resonator may be formed by a dry-etching method such as RIE.
As described above, according to the present invention, a nitride type III-V group compound semiconductor layer, a semiconductor layer, or a layer made of various types of materials that forms a light emitting device structure or a device structure is formed on a principal plane of a nitride type III-V group compound semiconductor substrate, a semiconductor substrate, or a layer made of various types of materials in such a manner that a first region does not directly contact second regions that have a higher average dislocation density, a higher average defect density, or worse crystallinity than the first region, the nitride type III-V group compound semiconductor layer, the semiconductor layer, or the layer made of the variety of materials that form the light emitting device structure or device structure can be prevented from being adversely affected by the second regions. Thus, a semiconductor device having good characteristics such as good light emitting characteristic, good reliability, and long life or various types of devices having good characteristics, good reliability, and long life can be accomplished.
This application is a division of U.S. patent application Ser. No. 11/279,709, filed Apr. 13, 2006, which is a division of U.S. patent application Ser. No. 10/813,371, filed Mar. 30, 2004, both of which are incorporated herein by reference to the extent permitted by law.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 11279709 | Apr 2006 | US |
| Child | 12824593 | US | |
| Parent | 10813371 | Mar 2004 | US |
| Child | 11279709 | US |
