Patent Application
20140030893
The invention relates to a method of forming semiconductor devices on a semiconductor wafer. More specifically, the invention relates to etching features with reduced CD.
In forming semiconductor devices, some devices may be formed by etching an etch layer.
To achieve the foregoing and in accordance with the purpose of the present invention, a method for etching with CD reduction an etch layer disposed below a silicon containing mask layer under a patterned organic mask with features with a first CD. Features are opened in the silicon containing mask layer using the patterned organic mask, comprising providing an opening gas with an etchant component and polymerizing component, forming the opening gas into a plasma, and providing a pulsed bias with a pulse frequency between 10 Hz and 1 kHz, which etches features through the silicon containing mask layer with a second CD, which is less than half the first CD, forming a pattern in the silicon containing mask layer. The pattern of the silicon containing mask layer is transferred to the etch layer.
In another manifestation of the invention, a method for etching with CD reduction, an etch layer disposed below an organic underlayer disposed below a silicon containing mask layer under a patterned organic mask with features with a first CD is provided. Features are opened in the silicon containing mask layer using the patterned organic mask, comprising providing an opening gas with an etchant component and polymerizing component, forming the opening gas into a plasma, and providing a pulsed bias with a pulse frequency between 10 Hz and 1 kHz, which etches features through the silicon containing mask layer with a second CD, which is less than half the first CD, forming a pattern in the silicon containing mask layer. The pattern of the silicon containing mask layer is transferred to the organic underlayer. The pattern of the organic underlayer is transferred to the etch layer.
These and other features of the present invention will be described in more details below in the detailed description of the invention and in conjunction with the following figures.
The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
The present invention will now be described in detail with reference to a few preferred embodiments thereof as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well known process steps and/or structures have not been described in detail in order to not unnecessarily obscure the present invention.
Due to lithography resolution limits, etch-introduced critical dimension (CD) shrinkage is required for patterning of trench/via beyond 20 nm technology. Conventionally, this is achieved by increasing the ratio of polymerizing fluorocarbon gas in a chemistry or reducing electrostatic chuck (ESC) temperature in etch recipes. As scaling continues, plasma etch processes become more challenging. The high demand for CD shrinkage constrains tunability of gas chemistry or ESC temperature, which is very critical for managing other etch performances in terms of process and productivity requirements.
In a preferred embodiment of the invention, a substrate with an etch layer of silicon oxide disposed under organic underlayer disposed under a silicon containing antireflective coating (SiARC) disposed below patterned organic mask of 193 nm photoresist with features with CD greater than 40 nm is placed in an etch chamber (step 104).
The plasma power supply 506 and the wafer bias voltage power supply 516 may be configured to operate at specific radio frequencies such as, for example, 13.56 MHz, 27 MHz, 2 MHz, 400 kHz, or combinations thereof. Plasma power supply 506 and wafer bias power supply 516 may be appropriately sized to supply a range of powers in order to achieve desired process performance. For example, in one embodiment of the present invention, the plasma power supply 506 may supply the power in a range of 500 to 10000 Watts, and the wafer bias voltage power supply 516 may supply a bias voltage in a range of 10 to 2000 V. In addition, the TCP coil 510 and/or the electrode 520 may be comprised of two or more sub-coils or sub-electrodes, which may be powered by a single power supply or powered by multiple power supplies.
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Information transferred via communications interface 614 may be in the form of signals such as electronic, electromagnetic, optical, or other signals capable of being received by communications interface 614, via a communication link that carries signals and may be implemented using wire or cable, fiber optics, a phone line, a cellular phone link, a radio frequency link, and/or other communication channels. With such a communications interface, it is contemplated that the one or more processors 602 might receive information from a network, or might output information to the network in the course of performing the above-described method steps. Furthermore, method embodiments of the present invention may execute solely upon the processors or may execute over a network such as the Internet in conjunction with remote processors that shares a portion of the processing.
The term “non-transient computer readable medium” is used generally to refer to media such as main memory, secondary memory, removable storage, and storage devices, such as hard disks, flash memory, disk drive memory, CD-ROM and other forms of persistent memory and shall not be construed to cover transitory subject matter, such as carrier waves or signals. Examples of computer code include machine code, such as produced by a compiler, and files containing higher level code that are executed by a computer using an interpreter. Computer readable media may also be computer code transmitted by a computer data signal embodied in a carrier wave and representing a sequence of instructions that are executable by a processor.
Features are opened in the silicon containing mask layer using the patterned organic mask (step 108), where the opened features in the silicon containing layer have a CD less than half the CD of the features in the organic mask. An opening gas is flowed into the etch chamber (step 204). In an example of a recipe, the opening gas is 100 sccm CHF3, 300 sccm CF4, 160 sccm N2, and 100 sccm He. The pressure is maintained at 12 mTorr. The opening gas is formed into a plasma (step 208). 900 watts of RF is provided by the TCP coil to form the opening gas into a plasma. A pulsed bias is provided (step 212). In this example, the bias voltage is 190 volts at an RF frequency of 13.56 MHz. A duty cycle of 25% is provided at a pulse frequency 200 Hz. The process is maintained for 100 seconds. The flow of the opening gas is stopped (step 216).
Using the features with reduced CD in the silicon containing layer as a mask, features with reduced CD are etched into the organic underlayer (step 112). An etch gas is flowed into the etch chamber (step 304). The etch gas is formed into a plasma (step 308). The flow of the etch gas is stopped (step 312).
An example of a recipe for etching the organic underlayer provides a pressure of 5 mTorr. An etch gas is flowed into the chamber (step 304) comprising 20 sccm Cl2, 50 sccm HBr, 90 sccm O2, and 50 sccm N2. The etch gas is formed into a plasma by providing 300 watts TCP power (step 308). A bias of 250 volts is provided. The process is maintained for 45 seconds.
The reduced CD features in the organic underlayer 412 are used to etch reduced CD features into the etch layer 408 (step 116), where the reduced CD features have a CD less than half the CD of the features in the organic mask.
In an example of a recipe for etching the etch layer 412, which in this embodiment is silicon oxide, a pressure of 3 mTorr is provided. An etching gas comprising 90 sccm CF4 and 45 sccm CHF3 is flowed into the chamber. The etch gas is formed into a plasma by providing 600 watts TCP power. A bias voltage is of 160 volts is provided. The process is maintained for 42 seconds.
This embodiment of the invention allows for shrinkage of both trenches and vias. Other embodiments of the invention may use other fluorocarbon opening gases with an etching component and polymerizing component. Preferably, the opening gas has a ratio of etching component to polymerizing component of between 4:1 to 1:3, by volume. In addition, various embodiments of the invention have a pulse bias with a duty cycle of between 20% to 90% at a pulse frequency between 10 Hz to 1 kHz with a bias voltage amplitude of between 100 to 400 volts with an RF frequency between 2 to 60 MHz. In other embodiments, the etch layer may be a conductive layer, which uses a silicon containing mask.
Other embodiments of the invention may use tri-layer masks, with a top layer of photoresist above a SiARC above an organic layer above a cap layer. A layer, such as a titanium nitride (TiN) layer, may be below the cap layer. A silicon oxide layer may be below the TiN layer. In such an embodiment, the SiARC layer may be used as an etch mask for the organic layer, cap layer, TiN layer, or silicon oxide layer. In other embodiments, other layers may be used as masks for layers below.
Current conventional lithography provides photoresist features with CD of around 40 nm or 60 nm. Embodiments of the invention allow such photoresist features to provide etch layer features as low as 12 nm to 18 nm. Some embodiments of the invention provide a shrink so that the shrunk CD is less than one third the original CD, which for example may shrink a 60 nm photoresist mask feature to 18 nm at the bottom of the silicon containing mask layer.
Without being bound by theory it is believed that the off part of the duty cycle of the bias pulsing causes a net polymer deposition, which causes the tapering, while the on part of the duty cycle of the bias pulsing cause a net removal of the polymer deposition or a reduced polymer deposition. The longer the percentage that the duty cycle is off, the more the taper of the etch. As a result, the duty cycle may be used as a control of the etch taper, with an increase in the off duty cycle causing an increase in the taper.
In other embodiments of the invention other hydrofluorocarbons or fluorocarbons may be used as a polymerizing component. In addition, other halogen containing components, such as hydrofluorocarbons or fluorocarbons may be used as the etchant component. Other embodiments of the invention have etch layers that are other dielectric layers, such as a layer comprising silicon oxide.
While this invention has been described in terms of several preferred embodiments, there are alterations, permutations, and various substitute equivalents, which fall within the scope of this invention. It should also be noted that there are many alternative ways of implementing the methods and apparatuses of the present invention. It is therefore intended that the following appended claims be interpreted as including all such alterations, permutations, and various substitute equivalents as fall within the true spirit and scope of the present invention.
