Patent Application
20110287620
1. Field of Invention
The present invention relates to semiconductor technique, and more particularly, to a method of adjusting a metal gate work function of an NMOS device, which can be used for fabricating a high performance complementary metal-oxide-semiconductor (CMOS) device of 45 nanometers and beyond.
2. Description of Prior Art
As the characteristic size of the CMOS device reaches 45 nm and beyond, it is well known in the art that a conventional SiO2/poly-Si (polycrystalline silicon) stack structure needs to be replaced with a high K (dielectric constant)/metal gate stack structure, so as to significantly reduce tunneling current and resistance of the gate, to eliminate depletion effect of the polycrystalline silicon gate, to improve reliability of the device, and to alleviate Fermi level pinning effect However, there are many challenges in integration of the metal gate with the high K dielectric, such as thermal stability and interfacial states, and specifically, the Fermi level pinning effect results in a big challenge for nano CMOS device to achieve an appropriately low threshold voltage.
An object of the present invention is to provide a method of adjusting a metal gate work function of an NMOS device to obtain an appropriate work function, so as to achieve an appropriate threshold voltage.
To achieve the above object, there provides a method of adjusting a metal gate work function of an NMOS device, comprises:
step 1) forming an interfacial oxide layer of SiOx or SiON after formation of a device isolation, wherein the interfacial oxide layer of SiOx or SiON is formed by rapid thermal oxidation at a temperature of 600-900° C. for 20-120 s;
step 2) forming a high dielectric constant gate dielectric film by a PVD process, wherein, a HfLaON film is deposited by alternately sputtering a Hf—La target and a Hf target, or a HfSiON gate dielectric is deposited by alternately sputtering a Hf target and a Si target, by means of magnetic-controlled reactive sputtering;
step 3) performing rapid thermal annealing after depositing of the high dielectric constant gate dielectric film, wherein the rapid thermal annealing is performed at a temperature of 600-1050° C. for 10-120 s;
step 4) forming a metal gate electrode by a PVD process, wherein a metal nitride gate is sputtered and deposited by magnetic-controlled reactive sputtering;
step 5) doping the metal nitride gate by implanting N-type metal ions;
step 6) etching to form the metal gate electrode;
step 7) performing thermal annealing at a temperature of 350-1050° C.;
step 8) forming a back ohmic contact by a PVD process, wherein an Al—Si film is deposited at the back side by direct current sputtering;
step 9) forming alloy, in which annealing for alloying is performed in an oven filled with N2 at a temperature of 380-450° C. for 30-60 minutes.
In step 1) of the adjusting method, after the formation of the device isolation and before the formation of the interfacial oxide layer, the wafers are cleaned by a conventional cleaning method, and then immersed into a mixed solution of hydrofluoric acid/isopropyl alcohol/water at room temperature, following by washing with deionized water and spin drying, and the interfacial oxide layer formation is immediately performed.
In step 1) of the adjusting method, the mixed solution of hydrofluoric acid/isopropyl alcohol/water has a volume ratio of about 0.2-1.5%:0.01-0.10%:1%, and the immersion time is 2-10 minutes.
In step 2) of the adjusting method, the interfacial oxide layer of SiON is formed by implanting nitrogen into silicon substrate before performing rapidly thermal oxidation, or by performing oxidation followed by plasma nitridation.
In step 2) of the adjusting method, the high dielectric constant gate dielectric film is sputtered in a mixed gas of N2/Ar; and the ratio of respective elements and the film thickness can be adjusted by changing power and time for alternately sputtering the Hf—La target and the Hf target, or the Hf target and the Si target.
In step 4) of the adjusting method, when depositing the metal nitride gate, the metal nitride gate of TiN, or TaN, or MoN is formed respectively by reactive sputtering a Ti target, a Ta target or a Mo target, respectively, in the mixed gas of N2/Ar.
In step 5) of the adjusting method, the implanting metal ions for an NMOS device are selected from the group comprising Tb, Er, Yb and Sr.
In step 6) of the adjusting method, the metal gate electrode of TiN or TaN is formed by Cl-based reaction ion etching, or by chemical wet etching.
In step 7) of the adjusting method, the thermal annealing may be performed by annealing adapted for a gate-first process, for example, a rapid thermal annealing, or a spike annealing, or a laser annealing at a temperature of 950-1200° C. for 5 ms-30 s, or by annealing adapted for a gate-last process, for example, an annealing in an oven at a temperature of 350-550° C. for 20-60 minutes.
In step 8) of the adjusting method, the thickness of the Al—Si film deposited at the back side by sputtering is 80-120 nm.
The present invention utilizes the ion implantation method to implant metal ions into the metal gate electrode. After the rapid thermal annealing, the ions accumulate on the interface between the metal gate and the high K gate dielectric, or dipoles are generated by interface reaction on the interface between the high K gate dielectric and SiO2, so as to adjust the metal gate work function and achieve an appropriate low threshold voltage. The method is very simply, and has good thermal stability and good capability of adjusting the metal gate work function, and is completely compatible with the CMOS process. Thus, the method is convenient for the industrialization of the integrated circuit.
As shown in
In the present invention, the physical vapor deposition (PVD) method is utilized to deposit a layer of metal nitride film or metal film on the high K dielectric, such as HfLaOH, HfSiON, as the metal gate electrode. And, the ion implantation method is used to dope the metal gate electrode. The implanted metal ions for the NMOS device are selected from the group comprising Tb, Er, Yb and Sr. Then, the doped metal ions can be driven to and accumulate on the interface between the metal gate electrode and the high K gate dielectric by a high temperature annealing, or dipoles may be generated by interface reaction on the interface between the high K gate dielectric and SiO2. As a result, the gate work function can be changed, dependent on the types of the metal gate material and the doped ions, profile of the concentration, and the interface reaction status. An appropriate gate work function can be obtained by optimizing energy, dose and heat treatment condition for the ion implantation, so as to provide an appropriate threshold voltage. This method is simple and convenient to be implemented, and may be widely used. Also, the method has strong capability of adjusting the metal gate work function, and is well-compatible with CMOS process.
The method according to the present invention comprises:
step 1): cleaning, in which the wafers are cleaned after the formation of the device isolation and before the formation of the interface oxide layer. Firstly, the conventional cleaning method is used. Then, the wafers are immersed into the solution of hydrofluoric acid/isopropyl alcohol/water at room temperature, followed by deionized water washing and spin drying, and then the wafers are moved into an oven. The solution of hydrofluoric acid/isopropyl alcohol/water has a volume ratio of about 0.2-1.5%:0.01-0.10%:1%. The immersion time is 0.5-8 minutes;
step 2): forming an interfacial layer of SiOx or SiON, wherein the rapid thermal annealing is performed at a temperature of 600-900° C. for 20-120 seconds;
step 3): forming a high dielectric constant (K) gate dielectric film by a PVD process, wherein a HfLaON film is deposited by alternately sputtering a Hf—La target and a Hf target, or a HfSiON gate dielectric film is deposited by alternately sputtering a Hf target and a Si target, by magnetic-controlled reactive sputtering, and the sputtering power or time for the alternate sputtering is changed to provide the high K dielectric films different concentration ratios and thickness;
step 4): performing rapid thermal annealing at a temperature of 600-1050° C. for 4-120 seconds after the depositing of the high k dielectric;
step 5): forming a metal gate electrode by a PVD process, in which a metal nitride gate, such as TiN, TaN, MoN, and the like, is deposited by magnetic-controlled reactive sputtering;
step 6): doping the metal nitride gate by implanting N-type metal ions, such as Tb, Er, Yb or Sr;
step 7): forming the metal gate electrode by Cl-based reactive ion etching;
step 8): performing high temperature rapid thermal annealing at a temperature of 500-1050° C. for 2-30 seconds;
step 9): forming a back ohmic contact by a PVD process, wherein an Al—Si film on the back side is deposited by direct current sputtering, the thickness of the film is 80-120 nm; and
step 10): alloying, wherein an annealing for alloying is performed in N2 or (N2+10% H2) in an oven at a temperature of 380-450° C. for 30-60 minutes.
Hereinafter, the method will be further described in detail in conjunction with embodiments of the present invention.
In step 1 of cleaning, the wafers are cleaned after the formation of the device isolation and before the formation of the interface oxide layer. Firstly, a conventional cleaning method is used. Then, the wafers are immersed into a mixed solution of hydrofluoric acid/isopropyl alcohol/water having a volume ratio of about 0.3-0.8%:0.01-0.08%:1% at room temperature for 2-10 minutes, then are washed in deionized water, and then dried by spinning in N2 and moved into an oven immediately.
In step 2 of forming the interfacial layer of SiOx, rapid thermal annealing (RTA) is performed at a temperature of 600-800° C. for 20-120 seconds, to provide an oxide layer having a thickness of 5-7 angstroms.
In step 3 of forming the high dielectric constant (K) gate dielectric film by a PVD process, HfLaON is formed by alternately sputtering a Hf—La target and a Hf target in a mixed gas of N2/Ar, by magnetic-controlled reactive sputtering, wherein the operation pressure for the sputtering is 5×10−3 torr, the sputtering power is 100-500 W, and the thickness of the deposited high k gate dielectric film of HfLaON is 10-40 angstroms.
In step 4 of cleaning, the wafers are cleaned by ultrasonic waves in acetone and absolute alcohol for 5-10 minutes, respectively, then are washed in deionized water, and then are dried by spinning in N2.
In step 5 of performing rapid thermal annealing after the depositing of the high k dielectric, after being dried by spinning, the wafers are moved into an oven immediately at a temperature of 600-1000° C. for 10-120 seconds.
In step 6 of the metal nitride gate film deposition, the TiN metal gate film is formed by sputtering the Ti target in the mixed gas of N2/Ar by magnetic-controlled reactive sputtering, wherein the operation pressure is 5×10−3 torr, the flow rate of N2 is 2-8 seem, the sputtering power is 600-1000 W, and the thickness of the TiN film is 5-100 nm.
In step 7 of ion implantation of Tb, the implantation energy is 10 Kev-120 Kev, and the implantation dose is 2×1014−6×1015/cm2.
In step 8 of etching metal gate electrode of TiTbN, the Cl-based reactive ion etching is used for forming patterns of metal gate electrode of TiTbN, wherein the RF power is 100-400 W.
In step 9 of rapid thermal annealing, the rapid thermal annealing is performed at a temperature of 700-1050° C. for 2-30 seconds with the protection of N2 for a gate-first process.
In step 10 of forming a back ohmic contact by a PVD process, the Al—Si film having a thickness of 60-100 nm is deposited on the back side by direct current sputtering in an Ar gas.
In step 11 of alloying, the alloying process is performed at a temperature of 380-450° C. for 30-60 minutes, with the protection of N2 gas.
Table 1 shows variations of the flat band voltage with the change of the Tb implantation dose. When the Tb implantation dose is less than 5.5E14 cm−2, the flat band voltage is significantly moved towards the negative direction by 0.38V compared with the case without Tb doping. The method of the present invention is effective and well satisfies the requirements of the NMOS device.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201010183450.0 | May 2010 | CN | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/CN2010/001457 | 9/21/2010 | WO | 00 | 2/3/2011 |
