Claims
- 1. A method of altering a margin between a potential of a charge stored in a memory cell and a common potential of a digit line pair, wherein said memory cell and said digit line pair are configured to receive an equilibrate signal, comprising:
- allowing a defect to change said common potential of said digit line pair; and
- substantially isolating said digit line pair from said equilibrate signal.
- 2. A method of altering a margin between a potential of a charge stored in a memory cell and a common potential of a digit line pair, wherein said memory cell and said digit line pair are configured to receive an equilibrate signal, comprising:
- allowing a defect to change said common potential of said digit line pair, wherein said defect is a short from said digit line pair to ground
- substantially isolating said digit line pair from said equilibrate signal.
- 3. A method of altering a margin between a potential of a charge stored in a memory cell and a potential of a shorted digit line pair, wherein said digit line pair is configured to receive an equilibrate signal, and wherein said digit line pair comprises a first digit line having a first initial potential and a second digit line having a second initial potential, comprising:
- allowing a defect to change said first initial potential of said first digit line;
- shorting said first digit line to said second digit line; and
- substantially isolating said digit line pair from said equilibrate signal.
- 4. A method of altering a margin between a potential of a charge stored in a memory cell and a potential of a shorted digit line pair, wherein said digit line pair is configured to receive an equilibrate signal, and wherein said digit line pair comprises a first digit line having a first initial potential and a second digit line having a second initial potential, comprising:
- allowing a defect to change said first initial potential of said first digit line, wherein:
- said defect is a short between an equilibrate signal node and said first digit line, and
- said equilibrate signal node is configured to transmit said equilibrate signal; shorting said first digit line to said second digit line; and substantially isolating said digit line pair from said equilibrate signal.
- 5. A method of altering a margin between a potential of a charge stored in a memory cell and a potential of a digit line, wherein said memory cell and said digit line are configured to receive an equilibrate signal having a voltage, comprising:
- changing said voltage of said equilibrate signal;
- allowing said potential of said charge in said memory cell to change due to a defect and said equilibrate signal; and
- substantially isolating said digit line from said equilibrate signal.
- 6. A method of altering a margin between a potential of a charge stored in a memory cell and a potential of a digit line, wherein said memory cell and said digit line are configured to receive an equilibrate signal having a voltage, comprising:
- changing said voltage of said equilibrate signal;
- allowing said potential of said charge in said memory cell to change due to a defect and said equilibrate signal, wherein said defect is a short within a storage capacitor of said memory cell; and
- substantially isolating said digit line from said equilibrate signal.
- 7. The method in claim 6, wherein said defect is a defect of a dielectric layer between two cell plates of said storage capacitor.
- 8. The method in claim 7, wherein said defect is a nitride defect.
RELATED APPLICATION
This application is a divisional of application Ser. No. 08/855,555, filed May 13, 1997, and issued on Mar. 2, 1999, as U.S. Pat. No. 5,877,993.
US Referenced Citations (16)
Divisions (1)
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Number |
Date |
Country |
Parent |
855555 |
May 1997 |
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