Claims
- 1. A method of detecting a leak within a storage capacitor of a memory cell affiliated with a digit line, wherein a cell plate generator is coupled to said storage capacitor and to said digit line, and said cell plate generator is further configured to generate a voltage, comprising:
- charging said storage capacitor with an input potential corresponding to a logic 0 value;
- initiating a static refresh pause;
- increasing said voltage generated by said cell plate generator;
- limiting electrical communication between said cell plate generator and said digit line;
- discharging an output potential of said storage capacitor to said digit line; and
- comparing said input potential with said output potential.
- 2. The method in claim 1, wherein initiating a static refresh pause further comprises preventing electrical communication between said digit line and said storage capacitor.
- 3. The method in claim 2, wherein initiating a static refresh pause further comprises allowing electrical communication between said digit line and said cell plate generator.
- 4. The method in claim 3, further comprising allowing said leak to change said input potential to said output potential, wherein said allowing occurs during said static refresh pause.
- 5. The method in claim 4, further comprising ending said static refresh pause before discharging.
RELATED APPLICATION
This application is a divisional of application Ser. No. 08/855,555, filed May 13, 1997, and issued on Mar. 2, 1999, as U.S. Pat. No. 5,877,993.
US Referenced Citations (16)
Divisions (1)
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Number |
Date |
Country |
Parent |
855555 |
May 1997 |
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