Patent Application
20060283716
1. Field of the Invention
Embodiments of the present invention generally relate to a method to deposit a metal layer with electrochemical plating and more particularly, to the direct plating of a copper layer onto a ruthenium alloy barrier or adhesion layer.
2. Description of the Related Art
Metallization for sub-quarter micron sized features is a foundational technology for present and future generations of integrated circuit manufacturing processes. In devices such as ultra large scale integration-type devices, i.e., devices having integrated circuits with more than a million logic gates, the multilevel interconnects that lie at the heart of these devices are generally formed by filling high aspect ratio interconnect features with a conductive material (e.g., copper or aluminum). Conventionally, deposition techniques such as chemical vapor deposition (CVD) and physical vapor deposition (PVD) have been used to fill these interconnect features. However, as interconnect sizes decrease and aspect ratios of device features increase, void-free filling of interconnect features via conventional metallization techniques becomes increasingly difficult. As a result, plating techniques, such as electrochemical plating (ECP) and electroless plating have emerged as viable processes for filling sub-quarter micron sized, high aspect ratio interconnect features in integrated circuit manufacturing processes.
In an ECP process, sub-quarter micron sized high aspect ratio features formed into the surface of a substrate may be efficiently filled with a conductive material, such as copper. Most ECP processes generally involve two stage processes, wherein a seed layer is first formed over the surface features of the substrate (this process may be performed in a separate system), and then the substrate surface features are exposed to an electrolyte solution while an electrical waveform is simultaneously applied between the substrate and an anode positioned within the electrolyte solution. The electrolyte solution is generally rich in metal ions to be plated onto the surface of the substrate. Therefore, the application of the electrical waveform drives a reductive reaction to reduce the metal ions and precipitate the respective metal. Upon precipitating, the metal plates onto the seed layer to form a film.
The process requirements for copper interconnects are becoming more stringent, as the critical dimensions for modern microelectronic devices shrink to 0.1 μm or less. As a result thereof, conventional plating processes will likely be inadequate to support the demands of future interconnect technologies. Conventional plating practices include depositing a copper seed layer via physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD) onto a diffusion barrier layer (e.g., tantalum or tantalum nitride). However, it is extremely difficult to have adequate seed step coverage with PVD techniques, as discontinuous islands of copper are often obtained close to the feature bottom in high aspect ratio features with PVD techniques. In addition, for PVD techniques a relatively thick copper layer (e.g., >200 Å) over the field is generally needed to have continuous sidewall coverage throughout the depth of a small (e.g. <0.1 μm) high aspect ratio feature, which during subsequent copper plating often causes the throat of the feature to close before the feature sidewalls are covered. For CVD processes, copper purity is generally questionable due to difficult complete precursor-ligand removal. ALD techniques, though capable of giving generally conformal deposition with good adhesion to the barrier layer, suffer from very low deposition rates for depositing a continuous copper film on the sidewalls of adequate thickness to serve as a seed layer.
As noted above, PVD has been a preferred technique to deposit a copper seed layer. Also, electroless plating techniques for depositing a seed layer onto a barrier layer of tantalum or tantalum nitride are known. However, these techniques have suffered from several problems, such as adhesion failure between the copper seed layer and the barrier layer, as well as the added complexity of a complete electroless deposition system and the associated difficulties of process control. In addition, for interconnect features as small as 32 to 45 nm, it is beneficial to perform the copper seed layer deposition and the gapfill deposition uninterrupted to prevent formation of oxide or other contamination of the seed layer. Also, the copper seed supports the subsequently deposited bulk copper and improves adhesion to the barrier layer. Adhesion of a copper layer is very important for electronic device manufacturing to prevent device features from being damaged during subsequent CMP processes. Good adhesion between a barrier layer and a subsequently deposited copper layer also prevents stress migration failures in the device. A stress migration failure is a highly localized delamination failure that takes place in an electronic device during the thermal cycling associated with normal usage. This thermal cycling may create voids that coalesce over time into points of failure. Hence, adhesion between a copper and barrier layers is an important factor to be considered for the manufacture of electronic devices.
Methods known in the art for determining the adhesion of a deposited film include the tape-pull test, or “pull test” and the scribe-hatch test, or “scribe test”. The pull test involves applying a standard adhesive tape to the surface of a substrate on which the layers to be tested have been deposited. The tape is then removed and a film that is weakly adhered to the substrate will also be removed. The scribe test is a more rigorous version of the pull test, in which the surface of the substrate is first cross-hatched with a scribe prior to application of the adhesive tape. Although each of these tests are somewhat qualitative, it is known in the art that deposited films that pass these tests reliably will generally not show adhesion-related problems later, such as pull-out during CMP or stress migration failures during electronic device use. A deposited film with poor adhesion to the underlying surface will routinely fail the pull test and may even spontaneously spall off the underlying surface. A deposited film with marginal adhesion may pass the pull test but may fail the scribe test. Another instance of marginal film adhesion is when the film passes both the pull and scribe tests, but not reliably. For example, the deposited film may only fail the scribe test at certain locations on the substrate, or it may only fail on intermittent substrates, or both. Hence, a deposited film that is “adherent” or has “good adhesion”, as used herein, is defined as a deposited film or layer that reliably passes the pull test and scribe test on all regions of the substrate and for all substrates.
Because other methods of depositing a copper seed layer onto a barrier layer are problematic, direct electroplating of a copper layer onto barrier materials has been considered. “Direct plating”, as used herein, is defined as the method of electrochemically plating a more conductive metal layer, such as a copper seed layer, onto a substantially less conductive layer, such as a barrier or barrier/adhesion layer, to facilitate the subsequent uniform and void-free deposition of a gapfill layer and/or an overfill layer. Direct electroplating onto conventional barrier materials, such as tantalum or tantalum nitride, is difficult, since these traditional barrier materials generally have insulating native oxides across the surface. The presence of tantalum oxides result in very little adhesion between an electroplated copper layer and the barrier layer. Pre-plating treatments, such as thermal anneal in a reducing gas and cathodic reduction, have been attempted on tantalum-based barrier layers but have not improved adhesion. Thus, adhesion of direct-electroplated copper layers is still poor on tantalum-based barrier layers that have undergone pre-plating treatments to reduce tantalum oxide present on the surface of the barrier layer. This is because fresh tantalum surfaces are re-passivated so quickly in an aqueous electrolyte, i.e., on the order of 1 second, that adherent copper deposits cannot be obtained.
Therefore, there is a need for a process for directly plating a copper seed layer onto a barrier or adhesion layer. The process should deposit the copper seed layer with a strong adhesion to the underlying layer and with good uniformity over the entire substrate surface. Also, the process should be applicable for a range of barrier layer materials, including tantalum (Ta), titanium, zirconium, hafnium, niobium, molybdenum and tungsten. Further, the barrier or adhesion layer should be maintained with little or no oxidation during seed layer deposition and also should not be chemically reduced during the deposition process. Finally, the process should allow the deposition of a seed layer and a gapfill layer sequentially in the same plating bath.
Embodiments of the present invention provide a method for depositing a copper seed layer onto a substrate surface, generally onto a barrier layer that is an alloy of a group VIII metal and a refractory metal. The “term group VIII metals” (i.e., old CAS system notation) is generally intended to describe group 8, 9 and 10 elements, such as ruthenium (Ru), rhodium, palladium, cobalt, nickel, osmium, iridium, and platinum. Refractory metals may include tantalum, titanium, zirconium, hafnium, niobium, molybdenum, tungsten and combinations thereof. In one aspect, the alloy is an alloy consisting of at least 50 atomic % ruthenium and the balance tantalum. A copper layer is electroplated on the alloy directly.
In one aspect, the substrate surface is immersed in an acidic plating bath and a nucleation waveform—to achieve critical overpotential nucleation density—is initially applied to the barrier layer to form a continuous and conformal copper seed layer. A gapfill waveform may then be applied to the substrate surface to electrochemically plate a copper gapfill layer on the substrate surface. In another aspect, the substrate is immersed in a neutral or alkaline (pH≧7.0) copper solution that includes complexed copper ions and a current or bias is applied across the substrate surface. The complexed copper ions include a carboxylate ligand, such as oxalate or tartrate, or ethylenediamine (ED), EDTA and/or acetate. The complexed copper ions are reduced to deposit a continuous and conformal copper seed layer onto the barrier layer. A gapfill waveform may then be applied to the substrate surface to electrochemically plate a copper gapfill layer on the substrate surface. In another aspect, a continuous copper seed layer is formed on the alloy barrier layer in a neutral or alkaline copper solution as described above, but the gapfill layer is plated onto the copper seed layer in an acidic plating solution. In yet another aspect, the surface of the barrier layer is conditioned prior to plating to improve adhesion and reduce the critical current density for plating on the barrier layer. The conditioning may include cathodic pre-treatment in an acid-containing solution that is free of copper ions or a plasma pre-treatment in a hydrogen or hydrogen/helium mixture.
So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
For clarity, identical reference numerals have been used, where applicable, to designate identical elements that are common between figures.
The present invention teaches a method for depositing a copper layer onto a substrate surface, generally onto a barrier layer that is an alloy of a group VIII metal and a refractory metal. A cathodic electrochemical pre-treatment or a plasma treatment may be used to condition the surface of the barrier layer prior to plating a copper layer directly onto barrier layer. The copper layer may be plated on the barrier layer in an acidic electrolyte using a nucleation voltage pulse or in an alkaline bath containing a copper complexing agent.
Ruthenium thin films, deposited by CVD, ALD or PVD, are a potential candidate for an adhesion layer between intermetal dielectric (IMD) layers and copper interconnect layers for ≦45 nm technology. Ruthenium is a group VIII metal that has a relatively low electrical resistivity (resistivity ˜7 μΩ-cm) and high thermal stability (high melting point ˜2300° C.). It is relatively stable even in the presence of oxygen and water at ambient temperature. The thermal and electrical conductivities of ruthenium are twice those of tantalum. Ruthenium also does not form an alloy with copper below 900° C. and shows good adhesion to copper. Therefore, the semiconductor industry has shown an interest in using ruthenium as an interlayer layer or adhesion layer. The relatively low resistivity of ruthenium can be an advantage when trying to fill ruthenium-coated features with copper without a seed layer. However, because ruthenium layers are often very thin (10-100 Å) and have over three times the electrical resistivity of copper, ruthenium layers still exhibit high sheet resistances, e.g. >20 ohm/square for 100 Å thick ruthenium films. The terminal effect associated with trying to plate onto materials that have a high sheet resistance can make obtaining uniform, void-free copper films on 200 and 300 mm substrates problematic. In addition, ruthenium layers are unable to act as copper diffusion barrier layers alone. Therefore, it has been necessary for a ruthenium adhesion layer to be used in combination with a conventional tantalum-based barrier layer to provide the benefits of copper layer adhesion and preventing copper ion diffusion. For interconnect features as small as 32 to 45 nm, however, separate adhesion and barrier layers may occupy a significant portion of an interconnect feature, impacting device performance.
Aspects of the invention contemplate the use of a combined barrier/adhesion layer, wherein the barrier/adhesion layer is comprised of an alloy of at least 50 atomic % ruthenium and wherein the balance of the alloy is comprised of a copper diffusion barrier material, such as tantalum. In other examples, the barrier material of the alloy may be other refractory metals, such as titanium, zirconium, hafnium, niobium, molybdenum, tungsten and combinations thereof. Adherent copper layers may then be electrochemically plated directly onto the barrier/adhesion layer without the need of an additional barrier or adhesion layer. Methods thereof are described below in conjunction with
A barrier/adhesion layer 106 may be formed in the apertures 120 formed on the dielectric layer 102. As noted above, the barrier/adhesion layer 106 is a thin film of a metal alloy, wherein the alloy is comprised of at least 50 atomic % of a group VIII metal, such as ruthenium, and the balance is a barrier metal, such as tantalum or other refractory metal. The alloy is selected to provide good adhesion to the dielectric layer 102, to act as a diffusion barrier to copper and to allow subsequent direct plating of copper thereon. The barrier/adhesion layer 106 may be formed using a suitable deposition process, such as ALD, chemical vapor deposition or physical vapor deposition. In a preferred aspect, the barrier/adhesion layer 106 is deposited in apertures 120 by a PVD process. The thickness of the barrier/adhesion layer 106 along the sidewalls 120a may be between about 5 Å to about 50 Å and preferably less than about 30 Å. A Ru—Ta alloy, when used as a barrier/adhesion layer 106 as shown in
A PVD-deposited barrier/adhesion layer 106 is preferred because it is then possible to deposit a Ru—Ta alloy layer that can be inhomogeneous, i.e. the concentration of the alloy can be made to vary controllably. For example it may be beneficial to minimize the concentration of tantalum at the interface between the barrier/adhesion layer 106 and copper layer 110 (copper layer 110 is illustrated in
Referring to
In addition to reducing CCD, conditioning of the surface of a barrier/adhesion layer 106 has been shown to improve the adhesion of plated copper layers directly plated thereon. As stated above, the reduction of tantalum oxides on conventional tantalum-based barrier layers—via cathodic reduction or thermal anneal in a reducing gas—has proven to be ineffective in improving adhesion of plated copper layers. Conversely, cathodic electrochemical pre-treatment of Ru—Ta alloys has been shown to improve the adhesion of subsequently plated copper layers. Hence, it is believed that certain pre-treatments of Ru—Ta alloys may not simply be reducing tantalum oxides present on the surface of the alloy but may instead be preferentially removing small quantities of tantalum—perhaps as little as one atomic monolayer. During deposition of a Ru—Ta alloy—especially during PVD deposition—agglomerations or islands of pure tantalum may form, possibly in regions as thin as a monolayer. This may result from a lack of PVD target homogeneity, preferential deposition of each component of the alloy during alternating plasma pulses, preferential re-sputtering of the alloy surface, or even metal atom mobility and like-atom agglomeration after being sputtered onto a substrate surface. Any of these mechanisms may create significant regions on the surface of a nominally homogeneous alloy that consist of pure tantalum and, once exposed to atmosphere, tantalum oxides.
In any event, cathodic reduction has been shown to improve the adhesion of directly plated copper layers on Ru—Ta alloy surfaces, whereas such a pre-treatment has proven ineffective for conventional tantalum and TaN surfaces. For example, only marginal adhesion is present for copper directly plated on a 90/10 ruthenium-tantalum alloy, whereas good adhesion of plated copper has been obtained after a cathodic electrochemical pre-treatment, even when the alloy surface is rinsed and dried after the cathodic pre-treatment. It is believed that cathodic reduction is successful on Ru—Ta alloy surfaces for one of several reasons. The oxide generated on the alloy may be a mixed Ru—Ta alloy more amenable to cathodic reduction than tantalum oxide. The area-fraction of tantalum-rich areas may be small enough for some Ru—Ta alloys that a high enough copper nucleation density may be present on the surface for an adherent copper layer to be formed. Or, the re-passivation kinetics of a Ru—Ta alloy may be slow enough to maintain the activated regions for a sufficient time to alloy copper plating.
It is also important to note that the pre-treatment of a barrier/adhesion layer does not permanently improve the adhesion of a subsequently plated copper layer. A long wait time between pre-treatment and direct plating has been shown to negate the benefits of pre-treatment of the barrier/adhesion layer. For good adhesion, the directly plated copper layer should be plated onto the barrier/adhesion layer less than about 150 minutes after the pre-treatment has taken place, preferably less than about 120 minutes and ideally less than about 2 to 5 minutes. After a wait time between pre-treatment and plating of about 4 hours, improved adhesion has been shown to be substantially diminished.
Embodiments of the invention further contemplate different electroplating methods for the deposition of copper layer 110. Referring to
In one embodiment, after conditioning of the substrate surface via cathodic pre-treatment or plasma treatment, a seed layer 111 is electrochemically plated onto conductive substrate surface 114 using a complex alkaline bath and plating process described below in conjunction with
In another embodiment, after conditioning of the substrate surface via cathodic electrochemical pre-treatment or plasma treatment, a seed layer 111 is electrochemically plated onto conductive substrate surface 114 using an acidic plating bath wherein a nucleation pulse is initially applied to the conductive substrate surface 114 when forming seed layer 111. Nucleation pulse for direct plating of a seed layer onto a barrier layer is described below in conjunction with
Conditioning Processes
Cathodic Electrochemical Pre-Treatment
Aspects of the invention contemplate a cathodic electrochemical pre-treatment of a substrate surface consisting of a Ru—Ta alloy prior to electrochemical plating of copper onto the alloy. Such pre-treatment has been demonstrated to enhance the adhesion of the electroplated copper layer onto the alloy.
The plating current for a typical ECP process onto a copper seed layer is typically in the range from about 2 mA/cm2 to about 10 mA/cm2 for filling copper into submicron trench and/or via structures, such as apertures 120 (illustrated in
It is well known that the kinetics of nucleation and crystal growth for electro-deposition is intimately related to the local electrochemical over-potential at the nucleation/growth sites as well as the condition of the surface whereon crystal growth takes place. Over-potential is defined as the difference between the actual potential and the zero-current (open-circuit) potential. A high over-potential favors new crystal nucleation by lowering the critical nucleus size and increasing the density of nuclei, while a low electrochemical over-potential favors growth on existing crystallites. Since the plating current density depends on the electrochemical over-potential for a given bath, the copper deposit structure/morphology is therefore affected by the plating current density. Further, nucleation is also dependent on the “activity” of the substrate surface, i.e., the concentration of “active sites” on the substrate. Any kind of surface imperfection, such as a crystal dislocation, crystal boundary or incorporated alien atom may serve as the active site. At the same overvoltage, or at the same applied current density, the amount of nuclei formed will be much higher if the barrier layer is free from unwanted deposits, such as ruthenium oxides and some organic compounds, that block the active sites and, hence, inhibit nucleation.
As predicted by theory and confirmed by scanning electron microscopic (SEM) images, a substrate with a copper film plated on a 100 Å ruthenium film in a 10 g/l sulfuric acid containing plating solution with a plating current of 3 mA/cm2 had large crystallites and poor film deposition in the center region of the substrate. Measured at the edge of the substrate, the thickness of the copper plated film was 1000 Å. According to the results shown in
Simply increasing plating current density to allow plating of a void-free, continuous film onto a ruthenium surface also has disadvantages; generally, a high plating current density tends to result in poor gap fill. Plating current densities of less than about 10 mA/cm2 have been found to encourage bottom-up deposition of trenches and vias, such as apertures 120, with a gap fill layer 112, shown in
One of the reasons for the CCD dependence on bath acidity is related to the local electrochemical over-potential discussed above. In addition, higher acidity plating solutions may remove unwanted deposits from the surface and increase the activity of the plating surface. Increasing acid concentration to lower the CCD introduces other problems, however. Because the intention of direct plating is to form a uniform, conformal metal layer on a barrier layer, electrical conductivity of the bath should be reduced as much as is practicable. A more conductive plating bath, such as a bath containing a high concentration of acid, degrades the uniformity of the resultant film.
Recent research presented by Chyan, et al. from University of North Texas in American Chemical Society National Meeting in New Orleans, La., held in Mar. 23 to Mar. 27, 2003, shows that ruthenium oxide (RuO2) has a metal-like conductivity, and copper also plates and adheres strongly to ruthenium oxide or surface that is primarily ruthenium oxide. The high CCD's observed on a ruthenium surface could be the result of unwanted deposits on the ruthenium surface. “Unwanted deposits”, as used herein, is defined to include unwanted oxidation of a deposited surface as well as organic contaminants that accumulate on the fresh metallic surface after deposition. A Ru/Ta alloy surface that is free of unwanted deposits is believed to be more active for copper nucleation. Hence, removing the unwanted deposits by a pre-treatment process before copper plating may greatly reduce the plating current and the plating bath acidity required to form a continuous copper layer and avoid voids at the copper/ruthenium interface. Embodiments of the invention contemplate a pre-treatment process that includes a cathodic electrochemical pre-treatment of a barrier/adhesion layer, such as barrier/adhesion layer 106, as shown in
The cathodic treatment mentioned above is an electrochemical treatment of a substrate surface in a copper-ion-free acid solution. An oxidized metallic surface, particularly a Ru—Ta—Ox surface that has formed on a freshly deposited Ru/Ta barrier/adhesion layer on a substrate, may be cathodically reduced. Additionally, weakly-bound organic surface contaminants may be expelled from the surface by the cathodic polarization. The removal of these unwanted deposits on the substrate surface prior to electrochemical plating has been demonstrated to reduce the CCD of the barrier/adhesion layer. One possible reduction reaction is shown in equation (1):
RuO2+4H*+4e−----->Ru+2H2O (1)
The cathodic treatment may be performed in an electrochemical plating cell similar to the copper plating cell described below in association with
The cathodic treatment can be realized through potential control or current control. With the potential control approach, a reference electrode is needed to monitor the wafer potential, in addition to the working electrodes, which are the thin as-deposited ruthenium film on the wafer surface, and an anode. Potential control can be realized through a potentiostat. The controlled ruthenium electrode potential, with respect to the reference electrode, is in the range of about 0 volt to about −1.0 volt, preferably about −0.8 volt vs. AgCl. In addition to RuOx reduction to ruthenium, H2 evolution may occur on the ruthenium film surface, hence, it is important to avoid applying a reduction potential to the substrate that is too high. With the current control approach, a cathodic current will be passed between the substrate, coated with a ruthenium film for example, and an anode.
It is important to note that unlike direct plating on a highly resistive layer, such as barrier/adhesion layer 106 illustrated in
The experimental results and discussion related to ruthenium are merely used as examples. The inventive concept may also be applied to other group VIII metals, such as rhodium, osmium and iridium. Further, the cathodic reduction process is not limited to the exemplary process parameters described above. For example, the cathodic reduction process may also take place in a solution that does not contain an acid and instead is neutral or alkaline, i.e. the solution may have a pH≧7.0.
Plasma Treatment
Aspects of the invention contemplate performing a plasma surface treatment on a substrate prior to electrochemical plating of copper onto the surface, wherein the surface consists of an alloy, such as barrier/adhesion layer 106. As described above in conjunction with
Generally, the pre-clean chamber 310 has a substrate support member 312 disposed in a chamber enclosure 314 under a quartz dome 316. The substrate support member 312 may include a central pedestal plate 318 disposed within a recess 320 on a quartz insulator plate 322. In some aspects, substrate support member 312 may be a heated substrate support member, to allow heating of the substrate during the plasma treatment process. The upper surface of the central pedestal plate 318 typically extends above the upper surface of the quartz insulator plate 322. A gap 324, typically between about 5 mils and 15 mils, is formed between a bottom surface of the substrate 326 and the top surface of the quartz insulator plate 322. During processing, the substrate 326 is placed on the central pedestal plate 318 and may be located thereon by positioning pin 332. The peripheral portion of the substrate 326 may extend over the quartz insulator plate 322 and overhang the upper edge of the quartz insulator plate 322. A beveled portion 328 of the quartz insulator plate 322 is disposed below this overhanging peripheral portion of the substrate 326, and a lower annular flat surface 330 extends from the lower outer edge of the beveled portion 328. The insulator plate 322 and the dome 316 may comprise other dielectric materials, such as aluminum oxide and silicon nitride.
The plasma surface treatment process for substrate 326 in pre-clean chamber 310 generally involves a sputter-etching process using the substrate 326 as the sputtering target. A cleaning gas, such as hydrogen or a helium/hydrogen mixture, is flowed through the chamber 310. Plasma is struck in the chamber by applying RF power to the chamber through coils 317 disposed outside of the chamber. A DC bias may be applied to the substrate 326 to accelerate ions in the plasma toward the substrate 326.
In one exemplary plasma surface treatment process for a 300 mm diameter substrate, a hydrogen gas flow of between about 100 sccm and about 1200 sccm is used. A 95% helium-5% hydrogen gas mixture may also be used at a gas flow up to about 500 sccm. Pressure in the chamber 310 is maintained between about 1 mTorr and about 50 mTorr during processing, RF power is between about 1000 W and about 3000 W, and the substrate temperature is maintained between about 20° C. and about 350° C. Process time varies depending on alloy composition and may be determined easily by one skilled in the art for a given alloy surface.
In another exemplary plasma surface treatment process for a 300 mm diameter substrate, a 95% helium-5% hydrogen gas mixture is used at a gas flow of between about 50 sccm to about 200 sccm. RF power during processing is between about 300 W and about 1000 W, and the substrate temperature is maintained between about 20° C. and about 350° C. In this example, a substrate bias of between about 0 W and about 100 W is applied. Process time varies depending on alloy composition and may be determined easily by one skilled in the art for a given alloy surface.
It has been demonstrated that thermal pre-treatment in forming gas, such as a 250° C. anneal in a 4% hydrogen-96% nitrogen mixture, is not effective for improving plated copper adhesion to a tantalum-based barrier layer. The thermal anneal process is unable to successfully reduce tantalum oxides because it is believed that tantalum oxides are thermodynamically stable at anneal temperatures that are low enough to avoid integration issues. However, the more aggressive hydrogen-only or helium-hydrogen treatment, coupled with RF plasma and/or substrate bias, may reduce any tantalum oxides present on an alloy surface, enabling adherent copper film deposition on the alloy surface.
Electrochemical Plating Processes
Direct Plating on a Barrier/Adhesion Layer with a Complex Alkaline Electrolyte
Embodiments of the invention teach the use of complexed copper sources contained within an alkaline plating solution for the direct plating of copper layers on a barrier/adhesion layer. This process may be performed in a plating cell similar to the electrochemical processing cell described below in conjunction with
A plating solution containing complexed copper sources has a significantly more negative deposition potential than does a plating solution containing free copper ions. Generally, complexed copper ions have a deposition potential from about −1.1 V to about −0.5 V, depending on the particular complexing agent. Free copper ions have deposition potentials in the range from about −0.3 V to about −0.1 V, when referenced to Ag/AgCl (1M KCl), which has a potential of 0.235 V verses a standard hydrogen electrode. For example:
Cu2(C6H4O7)+2H2O→2Cu0+C6H8O7+O2Δε=−0.7 V
Cu+2+2e−→Cu0Δε=−0.2 V.
Further, the current dependence on potential for the complex bath is substantially reduced when compared to a bath with free copper ions. Therefore, the local current density variation across the substrate surface will be improved, even in the presence of a large potential gradient across the substrate surface due to the low electrical conductivity of thin barrier metals. This leads to better deposition uniformity across the substrate surface. A more detailed description of electrochemical polarization of copper complex baths may be found in commonly owned U.S. patent application Ser. No. 10/616,097 [APPM 8241], filed Jul. 8, 2003, which is hereby incorporated by reference in its entirety to the extent not inconsistent with the claimed invention.
Suitable plating solutions that may be used with the processes described herein to plate copper include at least one copper source compound, at least one chelating or complexing compound, optional wetting agents or suppressors, optional pH adjusting agents, and a solvent.
The plating solutions contain at least one copper source compound complexed or chelated with at least one of a variety of ligands. Complexed copper includes a copper atom in the nucleus and surrounded by ligands, functional groups, molecules or ions with a strong affinity to the copper, as opposed to free copper ions with very low affinity, if any, to a ligand (e.g., water). Complexed copper sources are either chelated before being added to the plating solution or are formed in situ by combining a free copper ion source with a complexing agent. The copper atom may be in any oxidation state, such as 0, 1 or 2, before, during or after complexing with a ligand. Therefore, throughout the disclosure, the use of the word copper or elemental symbol Cu includes the use of copper metal (Cu0), cupric (Cu+1) or cuprous (Cu+2), unless otherwise distinguished or noted.
Examples of suitable copper source compounds include copper citrate, copper ED, copper EDTA, among others. A particular copper source compound may have ligated varieties. For example, copper citrate may include at least one cupric atom, cuprous atom or combinations thereof and at least one citrate ligand and include Cu(C6H7O7), Cu2(C6H4O7), Cu3(C6H5O7), or Cu(C6H7O7)2. In another example, copper EDTA may include at least one cupric atom, cuprous atom or combinations thereof, and at least one EDTA ligand and include Cu(C10H15O8N2), Cu2(C10H14O8N2), Cu3(C10H13O8N2), Cu4(C10H12O8N2), Cu(C10H14O8N2), or Cu2(C10H12O8N2). Examples of suitable copper source compounds include copper sulphate, copper pyrophosphate, and copper fluoroborate.
The plating solution contains one or more chelating or complexing compounds that include compounds having one or more functional groups selected from the group of carboxylate groups, hydroxyl groups, alkoxyl groups, oxo acids groups, mixture of hydroxyl and carboxylate groups, and combinations thereof. Further examples of suitable chelating compounds include compounds having one or more amine and amide functional groups, such as ethylenediamine (ED), diethylenetriamine, diethylenetriamine derivatives, hexadiamine, amino acids, ethylenediaminetetraacetic acid (EDTA), methylformamide, and combinations thereof. The plating solution may include one or more chelating agents at a concentration in the range from about 0.02 M to about 1.6 M.
The one or more chelating compounds may also include salts of the chelating compounds described herein, such as lithium, sodium, potassium, cesium, calcium, magnesium, ammonium, and combinations thereof. The salts of chelating compounds may completely or only partially contain the aforementioned cations (e.g., sodium) as well as acidic protons, such as Nax(C6H8-xO7) or NaxEDTA, whereas X=1-4. Such salt combines with a copper source to produce NaCu(C6H5O7). Examples of suitable inorganic or organic acid salts include ammonium and potassium salts or organic acids, such as ammonium oxalate, ammonium citrate, ammonium succinate, monobasic potassium citrate, dibasic potassium citrate, tribasic potassium citrate, potassium tartrate, ammonium tartrate, potassium succinate, potassium oxalate, and combinations thereof. The one or more chelating compounds may also include complexed salts, such as hydrates (e.g., sodium citrate dihydrate).
Wetting agents or suppressors may be added to the solution in a range from about 10 ppm to about 2,000 ppm, preferably in a range from about 50 ppm to about 1,000 ppm. Suppressors include polyacrylamide, polyacrylic acid polymers, polycarboxylate copolymers, polyethers or polyesters of ethylene oxide and/or propylene oxide (EO/PO), coconut diethanolamide, oleic diethanolamide, ethanolamide derivatives, and combinations thereof.
One or more pH-adjusting agents are optionally added to the plating solution to achieve a pH≧7.0, preferably between about 7.0 and about 9.5. The amount of pH adjusting agent can vary as the concentration of the other components is varied in different formulations. Different compounds may provide different pH levels for a given concentration, for example, the composition may include between about 0.1% and about 10% by volume of a base, such as potassium hydroxide, ammonium hydroxide, or combinations thereof, to provide the desired pH level. The one or more pH adjusting agents may also include acids, including carboxylic acids, such as acetic acid, citric acid, oxalic acid, phosphate-containing components including phosphoric acid, ammonium phosphates, potassium phosphates, inorganic acids, such as sulfuric acid, nitric acid, hydrochloric acid, and combinations thereof.
In an exemplary direct plating process using a Cu-ED alkaline electrolyte, a constant cathodic current is applied to the substrate resulting in a constant current density which may be in a range between about 1 mA/cm2 to about 10 mA/cm2 for a time period between about 0.1 seconds and 5.0 seconds. This results in the formation of a copper seed layer between about 50 Å and about 300 Å thick on the barrier layer.
Direct Plating on a Barrier/Adhesion Layer with a Acidic Electrolyte
Alternately, embodiments of the invention teach direct plating of a copper layer on a barrier/adhesion layer in an acidic plating solution, wherein a “nucleation waveform” or “nucleation pulse” may be used when the substrate surface is first brought in contact with the plating solution. “Nucleation waveform” or “nucleation pulse,” as used herein, is defined as an initial higher plating current level intended to help the nucleation of the copper deposition on the substrate surface, wherein the initial plating current is at least equal to, or ideally greater than, the CCD. This plating current may exceed the maximum plating current that typically allows for bottom-up gapfill of substrate features and therefore is only applied for a short time to prevent incomplete filling, e.g. voids, in high aspect ratio features on the substrate. The nucleation pulse is initially applied to the substrate surface to ensure that a uniform, well adhering, void-free layer, such as seed layer 111 illustrated in
Plating on Copper Seed with a Complex Alkaline Electrolyte
Aspects of the invention teach the use of a complex alkaline electrolyte for plating a gapfill layer, such as gapfill layer 112 (see
This process is similar to that described above for direct plating on a barrier layer with a complex alkaline electrolyte. Process parameters are believed to enhance the bottom-up gapfill process, however, including plating current and deposition time. Generally, higher deposition rates and, hence, plating current densities, may be utilized for this process.
The bath used for this process is also similar to that used for direct plating. The complex alkaline bath for gapfill contains at least one copper source compound and at least one complexing compound, as detailed previously. The one or more complexing compounds may also include salts of the chelating compounds, listed above. The bath also may contain wetting agents and one or more pH-adjusting agents (see above). Concentrations of the bath's components are believed to enhance the bottom-up gapfill process.
Additionally, the use of a nucleation pulse is unnecessary for the formation of a uniform, void-free metal layer to be formed on the seed layer.
Plating on Copper Seed with an Acidic Electrolyte
Aspects of the invention teach the use of a conventional acid electrolyte for plating a gap fill layer onto a seed layer that has been directly deposited on a barrier layer via an alkaline solution ECP process. ECP gapfill deposition of copper onto a copper seed layer using an acidic plating solution is well known in the art and may be performed in an electrochemical plating cell similar to the copper plating cell described below in conjunction with
A conventional, i.e., non-complex, electrochemical plating solution for ECP generally includes a copper source, an acid source, a chlorine ion source, and at least one plating solution additive, i.e., levelers, suppressors, accelerators, antifoaming agents, etc. For example, the plating solution may contain between about 30 g/l and about 60 g/l of copper, between about 10 g/l to about 50 g/l of sulfuric acid, between about 20 and about 100 ppm of chlorine ions, between about 5 and about 30 ppm of an additive accelerator, between about 100 and about 1000 ppm of an additive suppressor, and between about 1 and about 6 ml/l of an additive leveler. The plating current may be in the range from about 2 mA/cm2 to about 10 mA/cm2 for filling about 300 Å to about 3000 Å copper into the sub-micron trench and/or via structure. Examples of copper plating chemistries and processes can be found in commonly assigned U.S. patent application Ser. No. 10/616,097, titled “Multiple-Step Electrodeposition Process For Direct Copper Plating On Barrier Metals”, filed on Jul. 8, 2003, and U.S. patent application No. 60/510,190, titled “Methods And Chemistry For Providing Initial Conformal Electrochemical Deposition Of Copper In Sub-Micron Features”, filed on Oct. 10, 2003.
Exemplary Plating Apparatus
Electrochemical Processing System
The ECPS 400 further includes a factory interface, or FI 430. The FI 430 generally includes at least one FI robot 432 positioned adjacent one side of the FI 430 that is adjacent to the processing platform 413. The FI robot 432 is positioned to access a substrate 426 from substrate cassettes 434. The FI robot 432 delivers the substrate 426 to one of processing locations 414 and 416 to initiate a processing sequence. Similarly, FI robot 432 may be used to retrieve substrates from one of the processing locations 414 and 416 after a substrate processing sequence is complete. In this situation FI robot 432 may deliver the substrate 426 back to one of the cassettes 434 for removal from the system 400. Further, robot 432 also extends into a link tunnel 415 that connects factory interface 430 to processing mainframe or platform 413. Additionally, FI robot 432 is configured to access a processing chamber 435 positioned in communication with the FI 430. For aspects of the invention including plasma treatment, it is preferred that processing chamber 435 acts as the plasma treatment chamber 310, as described above in conjunction with
Electrochemical Plating Cell
The plating head assembly 600 includes a receiving member 601 for supporting and rotating a substrate during immersion into the electrochemical processing solution and during electrochemical processing. In this example, receiving member 601 includes a contact ring 602 and a thrust plate assembly 604 that are separated by a loading space 606. The contact ring 602 may be adapted to make electrical contact around the periphery of the substrate so that the necessary electrical waveform may be applied to the substrate. The contact ring 602 may be further adapted to include a reference electrode that is located close to the substrate surface. A more detailed description of the contact ring 602 and thrust plate assembly 604 may be found in commonly assigned U.S. patent application Ser. No. 10/278,527, filed on Oct. 22, 2002 and entitled “Plating Uniformity Control By Contact Ring Shaping”, and commonly assigned U.S. Pat. No. 6,251,236 entitled Cathode Contact Ring for Electrochemical Deposition, both of which are hereby incorporated by reference in their entirety to the extent not inconsistent with the present invention.
The frame member 503 of plating cell 500 supports an annular base member 504 on an upper portion thereof. Since frame member 503 is elevated on one side, the upper surface of base member 504 is generally tilted from the horizontal at an angle that corresponds to the tilt angle of frame member 503 relative to a horizontal position. Base member 504 includes a disk-shaped anode 505. Plating cell 500 may be positioned at a tilt angle, i.e., the frame portion 503 of plating cell 500 may be elevated on one side such that the components of plating cell 500 are tilted between about 3° and about 30°.
Inner basin 502 is generally configured to contain a processing solution, such as a plating solution or a cathodic electrochemical pre-treatment solution, during electrochemical processing of substrates. During processing, the processing solution is generally continuously supplied to inner basin 502, and therefore, the processing solution continually overflows the uppermost point 502a, generally termed a “weir”, of inner basin 502 and is collected by outer basin 501 and drained therefrom for chemical management and recirculation. The exemplary electrochemical processing cell is further illustrated in commonly assigned U.S. patent application Ser. No. 10/268,284, filed on Oct. 9, 2002, and entitled “Electrochemical Processing Cell”, claiming priority to U.S. Provisional Application Ser. No. 60/398,345, which was filed on Jul. 24, 2002, both of which are incorporated herein by reference in their entireties.
In an exemplary electrochemical process, such as substrate process sequence 610, described below in conjunction with
Process Sequences
During pre-treatment 611, a pre-treatment of the substrate surface, such as conductive substrate surface 114 in
For either cathodic electrochemical pre-treatment or plasma-pre-treatment, it is beneficial for the pre-treatment 611 to be performed on the same electrochemical processing system on which seed layer deposition 612 is subsequently performed, such as ECPS 400, described above in conjunction with
Next, seed layer deposition 612 takes place on the substrate, wherein a seed layer, such as seed layer 111 illustrated in
Gapfill layer deposition 613 then takes place on the substrate, wherein a gapfill layer, such as gapfill layer 112 in
In one aspect, an electrochemical gapfill process with a complex alkaline bath is used for gapfill layer deposition 613. This process is described above under Electrochemical Plating Processes. In this aspect, it is beneficial for seed layer deposition 612 to take place in a complex alkaline bath, since seed layer deposition 612 and gapfill layer deposition 613 may then be performed sequentially in the same substrate processing chamber. Because a single plating cell and solution are used for both process steps, the surface of the seed layer is never exposed to atmosphere prior to gapfill layer deposition 613, eliminating the possibility of unwanted oxidation. Further, there is virtually no time for organic contaminants to accumulate on the seed layer surface since the seed layer deposition 612 may be followed immediately by the gapfill layer deposition 613. This is especially useful for gapfill of interconnect features smaller than 65 nm; such small interconnect features are particularly sensitive to the formation of voids during gapfill as well as to the presence of unwanted deposits at the interface between the seed layer and the gapfill layer. Lastly, this method increases the productivity of electrochemical processing systems by combining two process steps into a single plating cell.
In another aspect, an electrochemical gapfill process with an acidic electrolyte is used for gapfill layer deposition 613. This process is described above under Electrochemical Plating Processes. In this aspect, it is beneficial for seed layer deposition 612 to take place sequentially in the same acidic electrolyte for the same reasons detailed in the previous aspect, i.e. when seed layer deposition 612 and gapfill layer deposition 613 are both conducted sequentially in a complex alkaline plating solution.
In another aspect, a direct plating process with a complex alkaline bath is used for seed layer deposition 612 and a conventional acidic electrolyte is used for gapfill layer deposition 613. In this aspect, an additional rinsing step is performed on the substrate between seed layer deposition 612 and gapfill layer deposition 613 to prevent cross-contamination of the incompatible plating solutions. The additional rinsing step may be performed in a dedicated rinsing chamber, preferably located on the same electrochemical processing system wherein the substrate process sequence 610 may be performed. The substrate is rinsed with an aqueous solution while rotating at a rate from about 20 to about 100 rpm and subsequently dried via gas flow and/or spin-drying. Due to the inherent incompatibility of acidic and basic solutions, as well as the serious problems associated with cross-contamination of organic additives between plating solutions, rigorous cleaning of the plating cell would have to be performed between seed layer deposition 612 and gapfill layer deposition 613 for each substrate processed therein. Instead, it is preferred that two separate ECP cells are used to complete the formation of copper layer 110 in apertures 120 on a substrate: one cell dedicated to an alkaline-based plating process, i.e., seed layer deposition 612, and one cell dedicated to acid-based plating processes, i.e., gapfill layer deposition 613. To minimize waiting time and the associated oxidation and contamination of the seed layer prior to gapfill deposition 613, both ECP cells are preferably situated on the same substrate processing platform, such as the exemplary plating system described below in conjunction with
Although several preferred embodiments which incorporate the teachings of the present invention have been shown and described in detail, those skilled in the art can readily devise many other varied embodiments that still incorporate these teachings.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
This application is a continuation-in-part of co-pending U.S. patent application Ser. No. 11/255,368 [APPM 8241.P01], filed Oct. 21, 2005, which claims benefit of U.S. Provisional Patent Application Ser. No. 60/621,173 [APPM 9762L], filed Oct. 21, 2004. This application is a continuation-in-part of co-pending U.S. patent application Ser. No. 11/007,857 [APPM 9200], filed Dec. 9, 2004, which claims benefit of U.S. Provisional Patent Application Ser. No. 60/579,129, filed Jun. 10, 2004. This application is also a continuation-in-part of co-pending U.S. patent application Ser. No. 11/012,965 [APPM 9201], filed Dec. 15, 2004, which claims benefit of U.S. Provisional Patent Application Ser. No. 60/579,129, filed Jun. 10, 2004, and U.S. Provisional Patent Application Ser. No. 60/621,215, filed Oct. 21, 2004. This application is also a continuation-in-part of co-pending U.S. patent application Ser. No. 10/616,097 [APPM 8241], filed Jul. 8, 2003. Each of the aforementioned related patent applications is herein incorporated by reference.
| Number | Date | Country | |
|---|---|---|---|
| 60621173 | Oct 2004 | US | |
| 60579129 | Jun 2004 | US | |
| 60579129 | Jun 2004 | US | |
| 60621215 | Oct 2004 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 11255368 | Oct 2005 | US |
| Child | 11373635 | Mar 2006 | US |
| Parent | 11007857 | Dec 2004 | US |
| Child | 11373635 | Mar 2006 | US |
| Parent | 11012965 | Dec 2004 | US |
| Child | 11373635 | Mar 2006 | US |
| Parent | 10616097 | Jul 2003 | US |
| Child | 11373635 | Mar 2006 | US |
