The present invention generally relates to a method of forming a semiconductor memory device, and more particularly to a planarization process of a dynamic random access memory (DRAM) device.
For years the trend in the memory industry as well as the semiconductor industry has been to scale down the size of memory cells in order to increase the integration level and thus the memory capacity of DRAM chips. In a DRAM cell with a buried gate, the current leakage caused by a capacitor is often reduced or avoided thanks to a relatively long channel length beneath the buried gate. Therefore, more and more DRAM cells are equipped with buried gates rather than with a conventional planar gate structure due to their superior performances.
In general, the DRAM cells with a buried gate include a transistor device and a charge storage device, which is able to accept signals from a bit line and a word line during the operation. However, due to limitations in fabrication technologies, many defects are formed in the DRAM cell with the buried gate. Therefore, there is still a need to provide an improved memory cell with a buried gate to gain enhanced performance and reliability of the corresponding memory device.
One object of the present invention is to provide a method of forming a semiconductor memory device, in which, a sacrificial layer with a predetermined thickness is formed to cover various regions of the semiconductor memory device, followed by performing a planarization process. That is, a preferable planarization of the semiconductor memory device may be achieved under a convenient process flow by using fewer masks.
To achieve the purpose described above, the present invention provides a method of forming semiconductor memory device including following steps. Firstly, a substrate is provided, and the substrate has a memory cell region and a peripheral region. Then, a first semiconductor layer is formed on the substrate, within the periphery region, and an insulating layer and a second semiconductor layer are sequentially formed on the substrate. Next, a sacrificial layer is formed on the second semiconductor layer, with a top surface thereof within the memory cell region and the peripheral region being coplanar. Following these, a removing process is performed to remove the sacrificial layer, a portion of the second semiconductor layer and a portion of the insulating layer to expose the first semiconductor layer. After the removing process, a top surface of the first semiconductor layer is then coplanar with a top surface of the second semiconductor layer.
The present invention provides a method of forming a semiconductor memory device, in which, the sacrificial layer having a predetermined thickness is formed to simultaneously cover on various regions of the semiconductor memory device, for improving the issues caused by non-coplanar top surfaces among those various regions. Thus, through the method of the present invention, the top surfaces of the sacrificial layer are coplanar within those various regions, so that the subsequent planarization process may be directly performed without firstly forming any mask layer, so as to simplify the planarization process of the semiconductor memory device.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
To provide a better understanding of the present invention, preferred embodiments will be described in detail. The preferred embodiments of the present invention are illustrated in the accompanying drawings with numbered elements.
Referring to
On the other hand, at least one gate, preferably a plurality of buried gates 114 as shown in
Next, a gate dielectric layer 120 is formed on the substrate 100, only within the periphery region 104, and then, a semiconductor layer 122 such as an amorphous silicon (A-Si) layer or a polysilicon (poly-Si) layer is formed on the gate dielectric layer 120, both within the memory cell region 102 and the periphery region 104. In one embodiment, the formation of the semiconductor layer 122 is for example accomplished through a chemical vapor deposition (CVD) process, and the semiconductor layer 122 includes a thickness about 300 angstroms and has a preferably dopant, such as a dopant with a first conductive type, but not limited thereto. Then, a mask layer 200 is formed to cover the periphery region 104, followed by performing an etching process, to remove the semiconductor layer 122 exposed from the mask layer 200. That is, a semiconductor layer 123 only disposed within the periphery region 102 is obtained on the gate dielectric layer 120, as shown in
As following, an insulating layer 124 such as including an oxide-nitride-oxide (ONO) structure is formed on the entire substrate 100, and which directly contacts the semiconductor layer 123 within the periphery region 104, and the top surface of the substrate 100 and the word lines 110 underneath, within the memory cell region 102. Then, a mask layer such as a photoresist layer with a tri-layered structure is formed on the substrate 100, the mask layer for example includes a sacrificial layer 126 such as an organic dielectric layer (ODL), a silicon-containing hard mask (SHB) 128, and a patterned photoresist (not shown in the drawings) stacked one over another on the substrate 100. The patterned photoresist includes at least one opening pattern (not shown in the drawings) for defining contact slots, so that, a plurality of openings 129 may be formed in the SHB 128 and the sacrificial layer 128 as shown in
As shown in
A semiconductor layer 162 is then formed on the substrate 100, both within the memory cell region 102 and the periphery region 104, through another CVD process, and the semiconductor layer 162 formed within the memory cell region 102 further fills in the contact slots 130, as shown in
Following these, a planarization process of the semiconductor layer 162 is performed. In the present embodiment, the planarization process of the semiconductor layer 162 includes a two-stepped removing process. In the first-stepped removing process, a mask layer 220 is firstly formed, to cover the memory cell region 102 and a portion of the periphery region 104, followed by removing the semiconductor layer 162 through the mask layer 220. Precisely, the semiconductor layer 162 is originally formed both on the memory cell region 102 (only having the insulating layer 124 formed thereon) and the periphery region 104 (having the gate dielectric layer 120, the semiconductor layer 123 and the insulating layer 124), so that, a top surface of the semiconductor layer 162 within the periphery region 104 is relative higher than a top surface of the semiconductor layer 162 within the memory cell region 102, as shown in
The second-stepped removing process such as a etching process or a chemical mechanical polishing (CMP) process is next performed, by using the insulating layer 124 on the semiconductor layer 123 as an etching stop layer, to simultaneous remove the semiconductor layer 162 both within the memory cell region 102 and the periphery region 104. That is, the semiconductor layer 162 may obtain a top surface which is leveled with the insulating layer 124, as shown in
Then, another planarization process such as an etching process or a CMP process is performed, to partially remove the semiconductor layer 162 within the memory cell region 102, and to completely remove the insulating layer 124 disposed on the semiconductor layer 123 to expose the semiconductor layer 123 underneath. Though this performance, a semiconductor layer 161 disposed only within the memory cell region 102 and a portion of the periphery region 104 is obtained, and which includes a top surface which is leveled with the top surface of the semiconductor layer 123, as shown in
According to above, a method of forming semiconductor memory device according to the first preferred embodiment is accomplished. In the present embodiment, for improving the non-coplanar top surfaces of the semiconductor layer 162 within the memory cell region 102 and the periphery region 104, the two-stepped removing process is performed. In the first-stepped removing process, the higher portion of the semiconductor layer 162, within the periphery region 104 is firstly removed by using the mask layer 220, and then, the second-stepped removing process is performed after removing the mask layer 220. After the two-stepped removing process, the semiconductor layer 123 and the semiconductor layer 161 disposed respectively in the memory cell region 102 and the periphery region 104 may therefore obtain coplanar top surfaces, so as to simplify the planarization process of the semiconductor memory device. Thus, the uniformity among different regions of the semiconductor memory device in the present invention is improved thereby.
People well skilled in the art shall realize the method of forming semiconductor memory device in the present invention is not limited to be achieved through the aforementioned flow, and may also include other forming steps. The following description will detail the different embodiments of the forming method of semiconductor memory device in the present invention. To simplify the description, the following description will detail the dissimilarities among the different embodiments and the identical features will not be redundantly described. In order to compare the differences between the embodiments easily, the identical components in each of the following embodiments are marked with identical symbols.
Refers to
The organic dielectric layer 170 includes a predetermined thickness t1, and the predetermined thickness t1 is preferably about two times or two times and half greater than that of the semiconductor layer 162, such as being about 2000 angstroms to 2300 angstroms. In this way, under the coverage of the organic dielectric layer 170, the stacked layers within the memory cell region 102 and the periphery region 104 may substantially have a coplanar top surface, as shown in
In the present embodiment, the planarization process of the semiconductor layer 162 also includes a two-stepped removing process. In the first-stepped removing process, an etching back process is performed by using an etchant like fluoroform (CHF3) or methane (CH4), for specifically removing the organic dielectric layer 170 within the memory cell region 102 and the periphery region 104, till the organic dielectric layer 170 within the periphery region 104 being completely removed to expose the semiconductor layer 162 underneath. In other words, after completely removing the organic dielectric layer 170 within the periphery region 104 and partially removing the organic dielectric layer 170 within the memory cell region 102 in the first-stepped removing process, the organic dielectric layer 170 remains within the memory cell region 102 may therefore obtain a top surface leveled with the top surface of the semiconductor layer 162 disposed within the periphery region 104, as shown in
Next, the second-stepped removing process such as another etching back process is performed, by using an etchant without any etching selectivity, such as fluoroform or methane, to simultaneously remove the organic dielectric layer 170 disposed in the memory cell region 102 and the semiconductor layer 162 disposed in the periphery region 104. In this way, the planarization of the organic dielectric layer 170 and the semiconductor layer 162 disposed in two different regions (the memory cell region 102 and the periphery region 104) are synchronously removed with the same etching rate, till the semiconductor layer 162 within the periphery region 104 being completely removed to expose the insulating layer 124 underneath. Subsequently, the processes as shown in
According to above, a method of forming semiconductor memory device according to the second preferred embodiment is accomplished. In the present embodiment, for improving the non-coplanar top surfaces of the semiconductor layer 162 within the memory cell region 102 and the periphery region 104, another two-stepped removing process, such as a two-stepped etching back process, is used without firstly forming any mask layer. After the two-stepped etching back process of the present embodiment, the semiconductor layer 123 and the semiconductor layer 161 disposed respectively in the memory cell region 102 and the periphery region 104 may therefore obtain coplanar top surfaces, so as to further simplify the planarization process of the semiconductor memory device. Furthermore, the organic dielectric layer 170 used in the present embodiment preferably includes the same or similar etching selectivity/polishing selectivity relative to the semiconductor layer 162, so that, the two-stepped etching back process are allowable to be performed by using the same etchant, for further simplify the process flow thereof.
After performing the method of the aforementioned first or second embodiments, a barrier layer 163 for example a titanium (Ti) layer or a titanium nitride (TiN) layer, a metal conductive layer 163 for example including a low resistant metal like tungsten (W), aluminum (Al) or copper (Cu), and a mask layer 167 for example including silicon oxide, silicon nitride or silicon carbonitride (SiCN) stacked one over another may be further formed on the semiconductor layer 161 in the subsequent process. Following these, a patterning process may be performed on those stacked layers, to form a plurality of bit lines (BLs) 160 on the substrate 100, within the memory cell region 102. Meanwhile, at least one active element, such as a transistor 180, is formed as well within the periphery region 104, as shown in
According to the above, a DRAM device 10 as shown in
Overall speaking, the present invention provides a method of forming a semiconductor memory device, in which, the sacrificial layer having a predetermined thickness is formed to simultaneously cover on various regions of the semiconductor memory device, for improving the issues caused by non-coplanar top surfaces among those various regions. Thus, through the method of the present invention, the top surfaces of the sacrificial layer are coplanar within those various regions, so that the subsequent planarization process may be directly performed without firstly forming any mask layer, so as to simplify the planarization process of the semiconductor memory device.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Number | Date | Country | Kind |
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2016 1 1244788 | Dec 2016 | CN | national |
Number | Name | Date | Kind |
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20150064812 | Patzer et al. | Mar 2015 | A1 |
20160064285 | Moriwaki | Mar 2016 | A1 |
Number | Date | Country | |
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20180190665 A1 | Jul 2018 | US |