Patent Application
20240355805
In recent years, owing to the need in miniaturizing the semiconductor chips, the requirements of wafer thinning process become more severe in semiconductor manufacturing process. Generally, during the wafer thinning process, the grinding process performed on the backside of the semiconductor wafer may cause the wafer edge to be damaged. Subsequently, an edge trimming process may be performed to remove the outer edge of the wafer.
However, the trimmed surface leads to un-recoverable damage on the semiconductor wafer, and the edge step height due to trimming will limits the backside process window. The trimming itself also induce stress on the wafer edge, and potentially impact bonding litho-overlay.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.
In accordance with some embodiments, a wet-cleanable sealant used in the thinning process of the stacked wafer structure can provide the mechanical support at the edge of the stacked wafer structure during the thinning process and also protect the underlying carrier wafer from damage due to the thinning process. In this case, the edge trimming process can be skipped or omitted. That is, the method is trim-free and the sealant acts as protection layer during thin-down, thus the wafer edge integrity is kept. On the other hand, the trim-free process reduces the edge stress damage, the grinding peeling issue, and the edge bonding litho-overlay impact.
Referring to
In some embodiments, the first wafer 100 may be a semiconductor wafer such as a silicon bulk wafer or a gallium arsenide wafer. In some embodiments, the first wafer 100 may include, for example, silicon, strained silicon, silicon alloy, silicon carbide, silicon-germanium, silicon-germanium carbide, germanium, a germanium alloy, germanium-arsenic, indium-arsenic, group III-V semiconductors. In some embodiments, the first wafer 100 includes glass or ceramic materials. In the present embodiment, the first wafer 100 is a carrier wafer. That is, the carrier wafer may be a bare silicon wafer which is substantially free of active, devices, passive devices, or any functional devices. However, the embodiments of the present invention are not limited thereto. In some alternative embodiments, the first wafer 100 is a device wafer. The device wafer may include active and passive devices. A wide variety of devices such as transistors, capacitors, resistors, combinations of these, and the like may be used to generate the structural and functional requirements of the design for the device stack. The device wafer may also include an interconnect structure which includes metallization layers and vias formed over the active and passive devices and are designed to connect the various devices to form functional circuitry.
As shown in
In some embodiments, the second wafer 200 may be a semiconductor wafer such as a silicon bulk wafer or a gallium arsenide wafer. In some embodiments, the second wafer 200 may include, for example, silicon, strained silicon, silicon alloy, silicon carbide, silicon-germanium, silicon-germanium carbide, germanium, a germanium alloy, germanium-arsenic, indium-arsenic, group III-V semiconductors. In some embodiments, the second wafer 200 includes glass or ceramic materials. In the present embodiment, the second wafer 200 is different from the first wafer 100. For example, the first wafer 100 is a carrier wafer, while the second wafer 200 is a device wafer. The device wafer may include active and passive devices. A wide variety of devices such as transistors, capacitors, resistors, combinations of these, and the like may be used to generate the structural and functional requirements of the design for the device stack. The device wafer may also include an interconnect structure which includes metallization layers and vias formed over the active and passive devices and are designed to connect the various devices to form functional circuitry.
The first wafer 100 and the second wafer 200 may be bonded to each other to form a stacked wafer structure 10. In some embodiments, the first wafer 100 is bonded to the second wafer 200 through a directly bonding method. Specifically, the second wafer 200 is turned upside down, so that the first surface 200a of the second wafer faces toward the first surface 100a of the first wafer 100, the first surface 200a of the second wafer is in direct contact with the first surface 100a of the first wafer 100, and then bonded together by the application of pressure and heat. In some embodiments, the first wafer 100 and the second wafer 200 have the same diameter. In other embodiments, the first wafer 100 and the second wafer 200 may have different diameters. The dimension of the first wafer 100 and the second wafer 200 may depend on the design requirement and construe no limitation in the disclosure. When bonding the first wafer 100 and the second wafer 200, the molecular bonding technique may be employed. For example, bringing the first surface 100a of the first wafer 100 and the top surface 200a of the second wafer 200 into direct contact, and the first wafer 100 and the second wafer 200 are bonded through Van der Waals force without using a specific bonding material or an adhesive. The bonding process will be discussed in the following paragraphs.
Referring to
The first bonding dielectric layer 110 is formed to cover the surface of the first substrate 102. In some embodiments, the first bonding dielectric layer 110 includes silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The first bonding dielectric layer 110 may be formed by depositing a dielectric material through a suitable process such as a thermal oxidation, a chemical vapor deposition (CVD) or the like, and then performing a planarization process on the dielectric material. In some embodiments, the planarization process includes a chemical mechanical polish (CMP) process, an etching back process, or a combination thereof.
In some embodiments, the second wafer 200 at least includes a second substrate 202, a stop layer 204, a device layer 206, a buffer layer 208, and a second bonding dielectric layer 210. In some embodiments, the second substrate 202 may be made of silicon or other semiconductor materials. For example, the second substrate 202 may be a silicon substrate. Alternatively, or additionally, the second substrate 202 may include other elementary semiconductor materials such as germanium. In some embodiments, the second substrate 202 is made of a compound semiconductor such as silicon carbide, gallium arsenic, indium arsenide or indium phosphide. In some embodiments, the second substrate 202 is made of an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. Furthermore, the second substrate 202 may be a semiconductor on insulator such as silicon on insulator (SOI) or silicon on sapphire.
The stop layer 204 may be formed on the second substrate 202. In some embodiments, the stop layer 204 may be made of a semiconductor material such as SiGe or the like, and may be formed by any suitable process such as an epitaxial growth process, an atomic layer deposition (ALD) process, a CVD process or the like.
The device layer 206 may be formed on the stop layer 204. In some embodiments, the device layer 206 is formed over the stop layer 204 in a front-end-of-line (FEOL) process. The device layer 206 includes a wide variety of devices. In some embodiments, the devices comprise active components, passive components, or a combination thereof. In some embodiments, the devices may include integrated circuits devices. The devices are, for example, transistors, capacitors, resistors, diodes, photodiodes, fuse devices, or other similar devices. In some embodiments, the device layer 206 includes a gate structure, source and drain regions, and isolation structures, such as shallow opening isolation (STI) structures (not shown). In the device layer 206, various N-type metal-oxide semiconductor (NMOS) and/or P-type metal-oxide semiconductor (PMOS) devices, such as transistors or memories and the like, may be formed and interconnected to perform one or more functions. Other devices, such as capacitors, resistors, diodes, photodiodes, fuses and the like may also be formed over the stop layer 204. The functions of the devices may include memory, processors, sensors, amplifiers, power distribution, input and/or output circuitry, or the like.
In addition, the interconnect structure (not shown) is formed over the device layer 206. In detail, the interconnect structure includes an insulating material and a plurality of metal features. The metal features are formed in the insulating material and electrically connected to the device layer 206. In some embodiments, the insulating material includes an inner-layer dielectric (ILD) layer on the device layer 206, and at least one inter-metal dielectric (IMD) layer over the ILD layer. In some embodiments, the insulating material includes silicon oxide, silicon nitride, silicon oxynitride, tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), low-k dielectric material, other suitable dielectric material, or combinations thereof. Exemplary low-k dielectric materials include FSG, carbon doped silicon oxide, Black Diamond® (Applied Materials of Santa Clara, California), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB, SiLK (Dow Chemical, Midland, Michigan), polyimide, other low-k dielectric material, or combinations thereof. In some alternatively embodiments, the insulating material may be a single layer or multiple layers. In some embodiments, the metal features include plugs and metal lines. The plugs may include contacts formed in the ILD layer, and vias formed in the IMD layer. The contacts are formed between and in connect with the device layer 206 and a bottom metal line. The vias are formed between and in connect with two metal lines. The metal features may be made of tungsten (W), copper (Cu), copper alloys, aluminum (Al), aluminum alloys, or a combination thereof. In some alternatively embodiments, a barrier layer (not shown) may be formed between the metal features and the insulating material to prevent the material of the metal features from migrating to or diffusion to the device layer 206. A material of the barrier layer includes tantalum, tantalum nitride, titanium, titanium nitride, cobalt-tungsten (CoW) or a combination thereof, for example.
The buffer layer 208 may be formed aside the device layer 206. In some embodiments, the buffer layer 208 includes at least one low-k dielectric material layer including a dielectric material having a dielectric constant less than 3.9, and may be formed by any suitable process such as a CVD process, an ALD process or the like, and then performing a planarization process on the dielectric material. In one embodiment, the dielectric material of the at least one low-k dielectric material layer comprises a porous dielectric material having a dielectric constant in a range from 2.0 to 2.8, which is known in the art as an extremely low-k (ELK) dielectric material. In the present embodiment, the buffer layer 208 is free of any metal feature therein, only includes the low-k dielectric material.
The second bonding dielectric layer 210 is formed to cover the surfaces of the second substrate 202, the device layer 206, and the buffer layer 208. In some embodiments, the second bonding dielectric layer 210 includes silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The second bonding dielectric layer 210 may be formed by depositing a dielectric material through a suitable process such as a thermal oxidation, a CVD or the like, and then performing a planarization process on the dielectric material. In some embodiments, the planarization process includes a CMP process, an etching back process, or a combination thereof.
The second wafer 200 is turned upside down, so that the first surface 200a of the second wafer faces toward the first surface 100a of the first wafer 100. In some embodiments, before the second wafer 200 is bonded to the first wafer 100, the first bonding dielectric layer 110 may be aligned with the second bonding dielectric layer 210 by using an optical sensing method. After the alignment is achieved, the first bonding dielectric layer 110 is in direct contact with the second bonding dielectric layer 210 and then bonded together by the application of pressure and heat. In this case, the bonding of the first bonding dielectric layer 110 bonded to the second bonding dielectric layer 210 may be referred to as a dielectric-to-dielectric bonding or directly bonding. After the second wafer 200 is bonded to the first wafer 100, an annealing process may be performed to strengthen the bonding between the first wafer 100 and the second wafer 200. The temperature of the annealing process may depend on the design requirement. For example, the higher the temperature of the annealing process, the greater the resulting bonding strength. In other embodiments in which the electrical components are distributed in the device layer 206 of the second wafer 200, the temperature of the annealing process is limited to relatively low so as not to damage the electrical components.
As shown in
After bonding the first wafer 100 and the second wafer 200, a support structure 300 is formed between the edge 100c of the first wafer 100 and the edge 200c of the second wafer 200. Specifically, the support structure 300 may be formed by injecting a sealant material into a gap between the edge 100c of the first wafer 100 and the edge 200c of the second wafer 200, so that the sealant material extends between the first bonding dielectric layer 110 and the second bonding dielectric layer 110 in the non-bonding region R2. Next, a curing process is performed to cure the sealant material as the support structure 300. In some embodiments, the sealant material is originally in a liquid state, and the curing process is used to convert the sealant material from the liquid state to the solid state. In some embodiments, the sealant material includes a modified epoxy-based polymer or an acrylic-based polymer, which enables the polymer cross-link with minimal volume change under the thermal treatment. In some embodiments, the temperature of the curing process is less than 400° C., which means less than the process temperature of the back-end-of-line (BEOL). As shown in
Referring to
Next, a second thinning process may be performed on the second wafer 200 to remove a second portion 212 of the second wafer 200 to a second thickness T2. In some embodiments, the second thickness T2 is in a range from about 1 μm to about 2 μm, such as 1 μm. That is, the top surface 202t1 of the second substrate 202 is thinned to the top surface 202t2 after performing the second thinning process, as shown in
Then, a third thinning process may be performed on the second wafer 200 to remove a third portion 214 of the second wafer 200 to expose the stop layer 204 and the second bonding dielectric layer 210. That is, the top surface 202t2 of the second substrate 202 is thinned to expose the top surface 210t of the second bonding dielectric layer 210 after performing the third thinning process, as shown in
Referring to
After performing the first etching process, as shown in
Referring to
Referring to
After removing the stop layer 204, a backside metallization structure 404 is formed on the device layer 206, as shown in
Then, the backside metallization structure 404 is formed in/on the dielectric layer 402. The backside metallization structure 404 may include metallization layers and the conductive vias. The metallization layers may be formed over the device layer 206 and are designed to connect the various devices to form functional circuitry. The metallization layers may be formed of conductive material (e.g., copper) with vias interconnecting the layers of conductive material and may be formed through any suitable process (such as deposition, damascene, dual damascene, or the like). In some embodiments, the backside metallization structure 404 is used to electrically connect the device layer 206 and the external components formed on the backside, thereby providing more flexible routing and effectively scaling down the chip size. As such, the thin-down method of the present application can be applied to more advanced node technology.
According to some embodiments, a method of forming a semiconductor structure includes: providing a first wafer with a first bonding dielectric layer; providing a second wafer with a device layer sandwiched between a stop layer and a second bonding dielectric layer; bonding the first wafer to the second wafer to form a stacked wafer structure; forming a support structure between an edge of the first wafer and an edge of the second wafer; performing a thinning process on a backside of the second wafer to expose the stop layer of the second wafer while the support structure is in place; performing a first etching process to remove the second bonding dielectric layer overlying the support structure; and performing a second etching process to remove the support structure and expose the first bonding dielectric layer of the first wafer.
According to some embodiments, a method of forming a semiconductor structure includes: bonding a first wafer to a second wafer by contacting a first bonding dielectric layer of the first wafer to a second bonding dielectric layer of the second wafer; forming a protective structure between an edge of the first wafer and an edge of the second wafer to cover a peripheral region of the first wafer; when the protective structure covers the peripheral region of the first wafer, removing a substrate of the second wafer from a backside of the second wafer until the second bonding dielectric layer overlying the protective structure is exposed; performing a first etching process to remove the second bonding dielectric layer overlying the protective structure and expose the protective structure; and performing a second etching process to remove the protective structure to expose the peripheral region of the first wafer.
According to some embodiments, a method of forming a semiconductor structure includes: bonding a device wafer onto a carrier wafer; forming a support structure between an edge of the device wafer and an edge of the carrier wafer, wherein the support structure surrounds a device layer of the device wafer along a closed path; removing a substrate and a portion of a bonding dielectric layer of the device wafer from a backside of the device wafer to expose the support structures while the support structure is in place; and removing the support structure through an acid etchant.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
