Claims
- 1. A method of generally identifying a defect within a memory circuit, wherein said memory circuit is connected to a cell plate, comprising:writing an input bit to said memory circuit; subjecting said memory circuit to at least one test stage; associating said defect with said test stage; associating an isolation of said cell plate with said test stage; initiating said isolation of said cell plate in relation to said test stage; reading an output bit from said memory circuit; and comparing said input bit with said output bit.
- 2. The method in claim 1, wherein:said test stage comprises a precharge cycle; and initiating further comprises initiating said isolation of said cell plate during said precharge cycle.
- 3. The method in claim 1, wherein:said test stage comprises a long RAS low period; and initiating further comprises initiating said isolation of said cell plate after said long RAS low period.
- 4. The method in claim 1, wherein:said test stage comprises a static refresh pause; and initiating further comprises initiating said isolation of said cell plate during said static refresh pause.
Parent Case Info
This application is a continuation of application Ser. No. 09/260,232, filed on Mar. 1, 1999 and issued as U.S. Pat. No. 6,028,799; which is a divisional of application Ser. No. 08/855,555, filed May 13, 1997 and issued as U.S. Pat. No. 5,877,993.
US Referenced Citations (19)
Continuations (1)
|
Number |
Date |
Country |
Parent |
09/260232 |
Mar 1999 |
US |
Child |
09/483264 |
|
US |