Patent Application
20180166373
The present invention relates to a method of making a wiring board and, more particularly, to a method of making a wiring board having an interposer, an electronic component and a base board incorporated therein.
High-speed semiconductor assemblies such as multi-chip modules often require high performance wiring boards for signal interconnection. However, as the power increases, large amount of heat generated by semiconductor chip would degrade device performance and impose thermal stress on the chip. Ceramic material, such as alumina or aluminum nitride which is thermally conductive, electrically insulative and low in CTE (Coefficient of Thermal Expansion), is often considered as a suitable material for such kind of applications. U.S. Pat. Nos. 8,895,998 and 7,670,872 disclose various wiring boards using ceramic as chip attachment pad material for better reliability. However, as there is no electronic component such as resistor decoupling capacitor or resistor incorporated therein, the electrical performance of these wiring boards is limited.
A primary objective of the present invention is to provide a method of making a wiring board having an electronic component and an interposer incorporated in a base board. The method includes depositing a dielectric layer on the base board and leveling the surface of the dielectric layer to that of the interposer so that the thickness difference between the interposer and the base board can be compensated. The dielectric material would also cover the electronic component and fill in the spaces between the base board and the interposer and between the base board and the electronic component, and therefore can mechanically bond the interposer, the electronic component and the base board together.
Another objective of the present invention is to provide a method of making the wiring board having electronic component electrically connected to the base board. The method includes depositing a routing circuitry that laterally extends on the dielectric layer and extends through the dielectric layer to form metallized vias in contact with the base board and is also electrically connected to the electronic component. The routing circuitry may further laterally extend to a top surface of the interposer and provides electrical connection between the electronic component and a built-in circuitry in the interposer.
In accordance with the foregoing and other objectives, the present invention provides a method of making a wiring board, comprising steps of: providing a base board having a top side, a bottom side, a first through opening, a second through opening and a top wiring layer at the top side thereof, wherein each of the first through opening and the second through opening has interior sidewalls extending from the top side and the bottom side; inserting an interposer into the first through opening of the base board, and inserting an electronic component into the second through opening of the base board, wherein the interposer includes a ceramic slug; forming a dielectric layer on a top surface of the electronic component and the top side of the base board and into gaps between peripheral edges of the interposer and the interior sidewalls of the first through opening and between peripheral edges of the electronic component and the interior sidewalls of the second through opening; and forming a routing circuitry on a top surface of the dielectric layer and electrically connected to the electronic component and to the base board through metallized vias.
Unless specifically indicated or using the term “then” between steps, or steps necessarily occurring in a certain order, the sequence of the above-mentioned steps is not limited to that set forth above and may be changed or reordered according to desired design.
Accordingly, the present invention provides a wiring board, comprising: a base board that includes a top side, a bottom side, a first through opening, a second through opening and a top wiring layer at the top side thereof, wherein each of the first through opening and the second through opening has interior sidewalls extending from the top side and the bottom side; an interposer disposed in the first through opening of the base board, wherein the interposer includes a ceramic slug; an electronic component disposed in the second through opening of the base board; a dielectric layer that covers a top surface of the electronic component and the top side of the base board and extends into gaps between peripheral edges of the interposer and the interior sidewalls of the first through opening and between peripheral edges of the electronic component and the interior sidewalls of the second through opening; and a routing circuitry disposed on a top surface of the dielectric layer and electrically connected to the electronic component and to the base board through metallized vias. Further, the present invention also provides a semiconductor assembly that includes a semiconductor device mounted over the top surface of the interposer of the aforementioned wiring board and electrically connected to the routing circuitry.
The wiring board, the semiconductor assembly and the method of making the same according to the present invention have numerous advantages. For instance, incorporating the interposer and the electronic component with the base board is particularly advantageous as the interposer offers CTE-compensated platform for chip attachment, the electronic component improves the electrical characteristics of the assembly, and the base board increases routing flexibility of the wiring board. Depositing the dielectric layer can provide mechanical bonds between the base board and the interposer and between the base board and the electronic component and offer a platform for high resolution circuitries disposed thereon, thereby allowing fine pitch assemblies such as flip chip and surface mount component to be assembled on the wiring board and interconnected to the electronic component by the routing circuitry.
These and other features and advantages of the present invention will be further described and more readily apparent from the detailed description of the preferred embodiments which follows.
The following detailed description of the preferred embodiments of the present invention can best be understood when read in conjunction with the following drawings, in which:
Hereafter, examples will be provided to illustrate the embodiments of the present invention. Advantages and effects of the invention will become more apparent from the following description of the present invention. It should be noted that these accompanying figures are simplified and illustrative. The quantity, shape and size of components shown in the figures may be modified according to practical conditions, and the arrangement of components may be more complex. Other various aspects also may be practiced or applied in the invention, and various modifications and variations can be made without departing from the spirit of the invention based on various concepts and applications.
Following the deposition of the seeding layer, a photoresist layer (not shown) is formed over the seeding layer. The photoresist layer may be formed by a wet process, such as a spin-on process, or by a dry process, such as lamination of a dry film. After the photoresist layer is formed, the photoresist layer is patterned to form openings, which are then filled with plated metal such as copper to form the routing circuitry 51. After metal plating, the exposed seeding layer is then removed by etching process to form electrically isolated conductive traces as desired. In this illustration, the routing circuitry 51 is a patterned metal layer, and extends from the top wiring layer 13 and the electronic component 30 in the upward direction, fills up the first via openings 403 and the second via openings 404 to form first metallized vias 513 and second metallized vias 514 in direct contact with the top wiring layer 13 and the electronic component 30, respectively, and extends laterally on the dielectric layer 40. As a result, the routing circuitry 51 provides electrical contacts on the interposer 20 and the dielectric layer 40 and is electrically coupled to the top wiring layer 13 of the base board 10 and the electronic component 30 through the first metallized vias 513 and the second metallized vias 514.
Optionally, the bottom surface of the structure may also be metallized to form a plated layer 50 as a single layer or multiple layers. The plated layer 50 is an unpatterned metal layer (typically a copper layer) that contacts the bottom metal film 15 of the base board 10, the interposer 20 and the thermally conductive material 31 of the electronic component 30 as well as the dielectric layer 40 in the first through opening 18 and the second through opening 19 and completely covers them from below. As a result, the plated layer 50 connects the interposer 20 to the bottom metal layer 13 so as to establish a larger thermal dissipation surface area than interposer 20.
Accordingly, as shown in
For purposes of brevity, any description in Embodiment 1 is incorporated herein insofar as the same is applicable, and the same description need not be repeated.
For purposes of brevity, any description in Embodiments above is incorporated herein insofar as the same is applicable, and the same description need not be repeated.
The wiring board 300 is similar to that illustrated in
As illustrated in the aforementioned embodiments, a distinctive wiring board is configured to have an interposer, an electronic component and a base board and exhibit improved reliability. Preferably, the wiring board mainly includes an interposer, an electronic component, a base board, a dielectric layer, a routing circuitry and optionally a bottom wiring layer, wherein (i) the interposer is inserted into a first through opening of the base board and has a bottom surface substantially coplanar with the bottom side of the base board; (ii) the electrical component is inserted into a second through opening of the base board and has a bottom surface substantially coplanar with the bottom side of the base board; (iii) the dielectric layer provides mechanic bonds between the interposer and the base board and between the electronic component and the base board and has a bottom surface substantially coplanar with the bottom surface of the interposer, the bottom side of the base board and the bottom surface of the electronic component; (iii) the routing circuitry is deposited on the top surface of the dielectric layer and electrically connected with the electronic component and includes metallized vias in electrical connection with the top wiring layer of the base layer and optionally further laterally extends onto a top surface of the interposer; and (iv) the bottom wiring layer is formed at the bottom side of the base board and electrically coupled to the routing circuitry through metallized through via(s) as well as the top wiring layer of the base board or/and through plated through hole(s).
The interposer can have a thickness larger than or the same as that of the base board and is incorporated with the base board by the dielectric layer. Preferably, the interposer has high elastic modulus and low coefficient of thermal expansion (for example, 2×10−6 K−1 to 10×10−6K−1). For instance, the interposer can include a ceramic slug (such as Al2O3, AIN, silicon or the like). As a result, the interposer, having CTE matching a semiconductor device to be assembled thereon, provides a CTE-compensated platform for the semiconductor device, and thus internal stresses caused by CTE mismatch can be largely compensated or reduced. Further, the interposer also provides primary heat conduction for the semiconductor device so that the heat generated by the semiconductor device can be conducted away. Additionally, the interposer may further include a built-in circuitry at the ceramic slug and electrically coupled to the routing circuitry. Preferably, the built-in circuitry provides electrical contacts at the top surface of the interposer for next-level circuitry connection.
The electronic component may be a resistor, capacitor, inductor or any other passive or active component and is incorporated with the base board by the dielectric layer. In a preferred embodiment, the electronic component is face-up disposed in the second through opening of the base board and electrically connected to the routing circuitry through metallized vias of the routing circuitry. Optionally, the bottom surface of the face-up electronic component may be provided with a thermally conductive material. As a result, the heat generated by the electronic component can be conducted away through the thermally conductive material.
The base board can enhance routing flexibility of the wiring board. Specifically, the top wiring layer of the base board can provide additional routing in electrical connection with the routing circuitry on the dielectric layer through the metallized vias embedded in the dielectric layer. Optionally, the base board may further includes one or more metallized through vias that extend through the base board in vertical directions and provide electrically connection between the top wiring layer and the bottom wiring layer. Additionally, the base board may be used for the placement accuracy of the interposer and the electronic component. Specifically, the interior sidewalls of the first amd second through openings of the base board may serve as alignment guides for the placement of the interposer and the electronic component. The interior sidewalls of the first through opening of the base board can be laterally aligned with four lateral surfaces of the interposer to define an area with the same or similar topography as the interposer and prevent the lateral displacement of the interposer. Likewise, the interior sidewalls of the second through opening of the base board can be laterally aligned with four lateral surfaces of the electronic component to define an area with the same or similar topography as the electronic component and prevent the lateral displacement of the electronic component. As a result, the interior sidewalls of the base board in close proximity to the peripheral edges of the interposer and the electronic component can provide placement accuracy for the interposer and the electronic component.
The dielectric layer can further cover the top surface of the interposer or have a top surface substantially coplanar with the top surface of the interposer. As the dielectric layer extends into gaps between the peripheral edges of the interposer and the interior sidewalls of the first through opening and between the peripheral edges of the electronic component and the interior sidewalls of the second through opening, the interposer and the electronic component can be securely boned with the base board through the dielectric layer.
The routing circuitry on the top surface of the dielectric layer may further extend onto the top surface of the interposer. As a result, the routing circuitry can provide electrical contacts on the top surface of the interposer to allow a semiconductor device to be flip-chip attached on the interposer, or provide a thermal pad on the top surface of the interposer for a semiconductor device face-up mounted thereon. When the dielectric layer further covers the top surface of the interposer, the routing circuitry preferably further includes additional metallized vias in connection with the top surface of the interposer. For instance, the additional metallized vias in the dielectric layer may contact and be electrically coupled to the built-in circuitry of the interposer so as to provide electrical connection with the interposer. Alternatively, the additional metallized vias may serve as heat pipes in contact with the top surface of the interposer for heat dissipation. The routing circuitry can be formed by metal deposition using photolithographic process. Preferably, the routing circuitry is deposited by a sputtering process and then an electrolytic plating process.
The bottom wiring layer may further laterally extend onto the bottom surface of the electronic component or/and the bottom surface of the interposer. In a preferred embodiment, the base board includes a bottom metal film that is a patterned metal film at the bottom side of the base board and electrically connected to the top wiring layer of the base board, and the bottom wiring layer is combined with the bottom metal film. As a result, the bottom wiring layer can be electrically connected to the routing circuitry through the metallized through vias in connection with the top wiring layer and the bottom metal film. The metallized through vias extend through the base board in the vertical directions and are between the top wiring layer and the bottom wiring layer. Or/Also, the bottom wiring layer may be electrically connected to the routing circuitry through plated through holes in connection with the top wiring layer and the bottom wiring layer. The plated through holes extend through the base board and the dielectric layer in the vertical directions and are between the routing circuitry and the bottom wiring layer. Accordingly, the routing circuitry and the bottom wiring layer provide electrical contacts at the top and bottom sides of the wiring board so as to offer the wiring board with stacking capability. Additionally, when the electronic component is face-down disposed in the second through opening of the base board, the bottom wiring layer would be further electrically coupled to the electronic component. As a result, the electronic component can be electrically connected to the routing circuitry through the bottom wiring layer.
For further routing, the wiring board may further include a top build-up circuitry or/and a bottom build-up circuitry. The top build-up circuitry can be provided to cover the top surface of the interposer and the top surface of the dielectric layer as well as the routing circuitry, and be electrically coupled to the routing circuitry and preferably thermally conductible to the interposer. The bottom build-up circuitry can be provided to cover the bottom surface of the interposer, the bottom side of the base board and the bottom surface of the electronic component as well as the bottom wiring layer, and be electrically connected to the bottom wiring layer and preferably thermally conductible to the interposer. In a preferred embodiment, the top build-up circuitry and the bottom build-up circuitry are multi-layered build-up circuitries without a core layer, and each includes at least one resin layer and at least one conductive trace layer that fills up via openings in the resin layer and extends laterally on the resin layer. The resin layer and the conductive trace layer are serially formed in an alternate fashion and can be in repetition when needed. The outmost conductive trace layers of the top and bottom build-up circuitries can respectively accommodate conductive joints, such as solder balls or bonding wires, for electrical communication and mechanical attachment with an assembly, an electronic device or others.
The present invention also provides a semiconductor assembly in which a semiconductor device such as chip is mounted over the top surface of the interposer of the aforementioned wiring board and electrically coupled to the routing circuitry. Specifically, the semiconductor device can be electrically connected to the wiring board using various using a wide variety of connection media including conductive bumps (such as gold or solder bumps) on the routing circuitry of the wiring board or bonding wires attached to the routing circuitry of the wiring board.
The assembly can be a first-level or second-level single-chip or multi-chip device. For instance, the assembly can be a first-level package that contains a single chip or multiple chips. Alternatively, the assembly can be a second-level module that contains a single package or multiple packages, and each package can contain a single chip or multiple chips. The semiconductor device can be a packaged or unpackaged chip. Furthermore, the semiconductor device can be a bare chip, or a wafer level packaged die, etc.
The term “cover” refers to incomplete or complete coverage in a vertical and/or lateral direction. For instance, in a preferred embodiment, the bottom build-up circuitry covers the interposer, the base board and the electronic component in the downward direction regardless of whether another element such as the bottom wiring layer is between the bottom build-up circuitry and the interposer, between the bottom build-up circuitry and the base board, and between the bottom build-up circuitry and the electronic component.
The phrases “mounted on” and “attached on” include contact and non-contact with a single or multiple support element(s). For instance, the semiconductor device can be attached on the interposer regardless of whether the semiconductor device is separated from the interposer by a the routing circuitry and the conductive bumps.
The phrase “aligned with” refers to relative position between elements regardless of whether elements are spaced from or adjacent to one another or one element is inserted into and extends into the other element. For instance, in a preferred embodiment, the interior sidewalls of the base board are laterally aligned with the peripheral edges of the interposer/electronic component since an imaginary horizontal line intersects the interior sidewalls of the base board and the peripheral edges of the interposer/electronic component, regardless of whether another element is between the interior sidewalls of the base board and the peripheral edges of the interposer/electronic component and is intersected by the line, and regardless of whether another imaginary horizontal line intersects the peripheral edges of the interposer/electronic component but not the interior sidewalls of the base board or intersects the interior sidewalls of the base board but not the peripheral edges of the interposer/electronic component. Likewise, in a preferred embodiment, some metallized vias of the routing circuitry are aligned with the interposer.
The phrase “in close proximity to” refers to a gap between elements not being wider than the maximum acceptable limit As known in the art, when the gap between the peripheral edges of the interposer/electronic component and the interior sidewalls of the base board is not narrow enough, the interposer/electronic component may not be accurately confined at a predetermined location. The maximum acceptable limit for a gap between the peripheral edges of the interposer/electronic component and the interior sidewalls of the base board can be determined depending on how accurately it is desired to dispose the interposer/electronic component at the predetermined location. Thereby, the descriptions “the peripheral edges of the interposer in close proximity to the interior sidewalls of the first through opening” and “ the peripheral edges of the electronic component in close proximity to the interior sidewalls of the second through opening” mean that the gap between the peripheral edges of the interposer/electronic component and the interior sidewalls of the through opening is narrow enough to prevent the location error of the interposer/electronic component from exceeding the maximum acceptable error limit For instance, the gaps in between the peripheral edges of the interposer and the interior sidewalls of the first through opening and between the peripheral edges of the electronic component and the interior sidewalls of the second through opening may be in a range of about 25 to 100 microns.
The phrases “electrical connection”, “electrically connected” and “electrically coupled” refer to direct and indirect electrical connection. For instance, in a preferred embodiment, the electronic component can be electrically connected to the built-in circuitry of the interposer through the routing circuitry but does not contact the built-in circuitry of the interposer.
The wiring board according to the present invention has numerous advantages. The interposer provides CTE-compensated platform for the attachment of a semiconductor device and also establish a heat dissipation pathway for spreading out the heat generated by the semiconductor device. The electronic component enhances the electrical characteristics of the semiconductor assembly. The base board provides mechanical support and enhances the routing flexibility for the wiring board. The dielectric layer provides mechanical bonds between the interposer and the base board and between the electronic component and the base board. The routing circuitry provides horizontal electrical routing and vertical electrical routing to electrically connect another horizontal electrical routing provided in the base board and the electronic component. The wiring board made by this method is reliable, inexpensive and well-suited for high volume manufacture.
The manufacturing process is highly versatile and permits a wide variety of mature electrical and mechanical connection technologies to be used in a unique and improved manner. The manufacturing process can also be performed without expensive tooling. As a result, the manufacturing process significantly enhances throughput, yield, performance and cost effectiveness compared to conventional techniques.
The embodiments described herein are exemplary and may simplify or omit elements or steps well-known to those skilled in the art to prevent obscuring the present invention. Likewise, the drawings may omit duplicative or unnecessary elements and reference labels to improve clarity.
This application is a continuation-in-part of U.S. application Ser. No. 15/605,920 filed May 25, 2017, a continuation-in-part of U.S. application Ser. No. 14/621,332 filed Feb. 12, 2015 and a continuation-in-part of U.S. application Ser. No. 14/846,987 filed Sep. 7, 2015. The U.S. application Ser. No. 15/605,920 is a continuation-in-part of U.S. application Ser. No. 14/621,332 filed Feb. 12, 2015 and a continuation-in-part of U.S. application Ser. No. 14/846,987 filed Sep. 7, 2015. The U.S. application Ser. No. 14/846,987 is a continuation-in-part of U.S. application Ser. No. 14/621,332 filed Feb. 12, 2015. The U.S. application Ser. No. 14/621,332 claims the benefit of filing date of U.S. Provisional Application Ser. No. 61/949,652 filed Mar. 7, 2014. The entirety of each of said Applications is incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 61949652 | Mar 2014 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 15605920 | May 2017 | US |
| Child | 15881119 | US | |
| Parent | 14621332 | Feb 2015 | US |
| Child | 15605920 | US | |
| Parent | 14846987 | Sep 2015 | US |
| Child | 14621332 | US | |
| Parent | 14621332 | Feb 2015 | US |
| Child | 15605920 | US | |
| Parent | 14846987 | Sep 2015 | US |
| Child | 14621332 | US | |
| Parent | 14621332 | Feb 2015 | US |
| Child | 14846987 | US |
