BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
FIGS. 1A through 1C are schematic cross-sectional views showing the steps for fabricating a structure with a nano-crystalline silicon dot layer therein according to an embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view of a structure with a nano-crystalline silicon dot layer therein replacing the oxide/nitride/oxide structure of a SONOS device.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
FIGS. 1A through 1C are schematic cross-sectional views showing the steps for fabricating a structure with a nano-crystalline silicon dot layer therein according to an embodiment of the present invention. As shown in FIG. 1A, the method includes forming a silicon layer 108 over a silicon oxide layer 102 on substrate 100. The silicon layer 108 includes a partial crystalline silicon region 104 and a partial amorphous silicon region 106. The method of forming the silicon layer 108 includes performing a chemical vapor deposition process. In one embodiment, the silicon layer 108 is formed by performing a chemical vapor deposition process at a temperature between 540° C. to 560° C. and a pressure of about 0.5 torr and using silane with a flow rate of between 100 sccm to 280 sccm as the reactive gas. After performing the chemical vapor deposition process, an annealing process can be performed to grow the crystalline silicon region 104. The annealing process is performed using a nitrogen-containing gas such as nitrogen at a temperature between 500° C. to 600° C. for an annealing period of between 3 hours to 5 hours.
As shown in FIG. 1B, an oxidation process is performed utilizing the high oxidation rate of amorphous silicon and the low oxidation rate of the crystalline silicon. Thus, all the amorphous silicon regions 106 are oxidized into silicon oxide 106a and the surface of the crystalline silicon region 104 is oxidized into silicon oxide 104a. Meanwhile, any un-oxidized interior content of the crystalline silicon region 104 form nano-crystalline silicon dots 104b, thereby completing the formation of the nano-crystalline silicon dot layer 108a. The oxidation process can be performed using a gaseous oxidizing agent, but much better using gaseous ozone or liquefied ozone with higher ozone concentration and lower process temperature. Oxidation in lower temperature process will enhance the different of oxidation rate between crystalline silicon and amorphous silicon. The concentration of the gaseous ozone is about 80% to 100%. The concentration of liquefied ozone is about 17 mg/L or more. The temperature of the liquefied ozone is between 50° C. to 80° C. and the temperature of the gaseous ozone is between 500° C. to 600° C.
Again, as shown in FIG. 1A, before forming the foregoing silicon layer 108 on the substrate 100, a dielectric layer 102 is formed over the substrate 100 in another embodiment. Moreover, after forming the nano-crystalline silicon dot layer 108a, the nano-crystalline silicon dot layer 108a may be covered with another dielectric layer 110 to form a stacked structure 120 as shown in FIG. 1C. The dielectric layer 102 is a silicon oxide layer formed, for example, by performing a thermal oxidation process. The dielectric layer 102 preferably has a thickness between 40 Å to 50 Å. The dielectric layer 110 can be fabricated using a material identical to or different from that of the dielectric layer 102. For example, the dielectric layer 110 is a silicon oxide layer formed, for example, by performing a chemical vapor deposition process. The dielectric layer 110 preferably has a thickness between 40 Å to 50 Å.
The foregoing nano-crystalline silicon dot layer can serve as a charge storage layer in a non-volatile memory device. As shown in FIG. 2, the foregoing nano-crystalline silicon dot layer can be used in a SONOS device 302 replacing the conventional oxide/nitride/oxide composite layer to serve as a charge storage layer 304 between a control gate 306 and a substrate 300.
Because the silicon oxide layer on the surface of the nano-crystalline silicon dots is derived from oxidizing the surface of the original crystalline silicon region, the coverage between the silicon oxide and the nano-crystalline silicon dots is good. In addition, the nano-crystalline silicon dots are formed in a deposition process instead of an implant process. Hence, the silicon oxide between the nano-crystalline silicon dots will not be damaged. As a result, the insulating effect between the nano-crystalline silicon dots is significantly improved. When the nano-crystalline silicon dot layer is used inside a non-volatile memory device, the device has a better reliability.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Patent Application
20080044574
